This product conforms to specifications per the terms of the Ramtron

Ramtron International Corporation

standard warranty. Production processing does not necessarily in-

1850 Ramtron Drive, Colorado Springs, CO 80921

clude testing of all parameters.

(800) 545-FRAM, (719) 481-7000, Fax (719) 481-7058

Rev. 2.2

www.ramtron.com

July 2003

Page 1 of 13

FM24CL16

16Kb FRAM Serial 3V Memory

Features

16K bit Ferroelectric Nonvolatile RAM

Organized as 2,048 x 8 bits

Unlimited Read/Write Cycles

10 year Data Retention

NoDelayTM Writes

Advanced High-Reliability Ferroelectric Process

Fast Two-wire Serial Interface

Up to 1MHz maximum bus frequency

Direct hardware replacement for EEPROM

Low Power Operation

New

2.7 - 3.6V operation

A Active Current (100 kHz) @ 3V

A Standby Current

Industry Standard Configuration

Industrial Temperature -40

C to +85

8-pin SOIC

New

"Green" 8-pin SOIC Package

Description

The FM24CL16 is a 16-kilobit nonvolatile memory
employing an advanced ferroelectric process. A
ferroelectric random access memory or FRAM is
nonvolatile and performs reads and writes like a
RAM. It provides reliable data retention for over 10
years while eliminating the complexities, overhead,
and system level reliability problems caused by
EEPROM and other nonvolatile memories.

Unlike serial EEPROMs, the FM24CL16 performs
write operations at bus speed. No write delays are
incurred. The next bus cycle may commence
immediately without the need for data polling. In
addition, the product offers unlimited write
endurance, orders of magnitude more endurance than
EEPROM. Also, FRAM exhibits much lower power
during writes than EEPROM since write operations
do not require an internally elevated power supply
voltage for write circuits.

These capabilities make the FM24CL16 ideal for
nonvolatile memory applications requiring frequent
or rapid writes. Examples range from data collection
where the number of write cycles may be critical, to
demanding industrial controls where a long write time
can cause data loss. The combination of features
allows the system to write data more frequently, with
less system overhead.

The FM24CL16 is available in an industry standard
8-pin SOIC and uses a two-wire protocol. The
specifications are guaranteed over the industrial
temperature range from -40°C to +85°C. Although
the FM24CL16 is functionally compatible with the
5V FM24C16, it offers 3V operation and up to 1MHz
bus speed.

Pin Configuration

Pin Names

Function

SDA Serial

Data/Address

SCL Serial

Clock

WP Write

Protect

VDD Supply

Voltage

VSS Ground

Ordering Information

FM24CL16-S 8-pin

SOIC

FM24CL16-G

8-pin SOIC - "Green" Assembly
Flow

VSS

SDA

SCL

VDD

FM24CL16

Rev 2.2
July 2003

Page 2 of 13

Address

Latch

256 x 64

FRAM Array

Data Latch

SDA

Counter

Serial to Parallel

Converter

Control Logic

SCL

Figure 1. Block Diagram

Pin Description

Pin Name

Type

Pin Description

SDA

I/O

Serial Data Address: This is a bi-directional data pin for the two-wire interface. It
employs an open-drain output and is intended to be wire-OR'd with other devices on the
two-wire bus. The input buffer incorporates a Schmitt trigger for noise immunity and the
output driver includes slope control for falling edges. A pull-up resistor is required.

SCL

Input

Serial Clock: The serial clock input for the two-wire interface. Data is clocked-out on
the falling edge and clocked-in on the rising edge.

Input

Write Protect: When WP is high, the entire array is write-protected. When WP is low,
all addresses may be written. This pin is internally pulled down.

VDD

Supply

Supply Voltage (3V)

VSS Supply

Ground

NC -

connect

FM24CL16

Rev 2.2
July 2003

Page 3 of 13

Overview

The FM24CL16 is a serial FRAM memory. The
memory array is logically organized as a 2,048 x 8
memory array and is accessed using an industry
standard two-wire interface. Functional operation of
the FRAM is similar to serial EEPROMs. The major
difference between the FM24CL16 and a serial
EEPROM with the same pinout relates to its superior
write performance.

Memory Architecture

When accessing the FM24CL16, the user addresses
2,048 locations each with 8 data bits. These data bits
are shifted serially. The 2,048 addresses are accessed
using the two-wire protocol, which includes a slave
address (to distinguish from other non-memory
devices), a row address, and a segment address. The
row address consists of 8-bits that specify one of 256
rows. The 3-bit segment address specifies one of 8
segments within each row. The complete 11-bit
address specifies each byte uniquely.

Most functions of the FM24CL16 either are
controlled by the two-wire interface or handled
automatically by on-board circuitry. The memory is
read or written at the speed of the two-wire bus.
Unlike an EEPROM, it is not necessary to poll the
device for a ready condition since writes occur at bus
speed. That is, by the time a new bus transaction can
be shifted into the part, a write operation is complete.
This is explained in more detail in the interface
section below.

Note that the FM24CL16 contains no power
management circuits other than a simple internal
power-on reset. It is the user's responsibility to ensure
that VDD is within data sheet tolerances to prevent
incorrect operation.

Two-wire Interface

The FM24CL16 employs a bi-directional two-wire
bus protocol using few pins and little board space.
Figure 2 illustrates a typical system configuration
using the FM24CL16 in a microcontroller-based
system. The industry standard two-wire bus is
familiar to many users but is described in this section.

By convention, any device that is sending data onto
the bus is the transmitter while the target device for
this data is the receiver. The device that is controlling
the bus is the master. The master is responsible for
generating the clock signal for all operations. Any
device on the bus that is being controlled is a slave.
The FM24CL16 is always a slave device.

The bus protocol is controlled by transition states in
the SDA and SCL signals. There are four conditions
including Start, Stop, Data bit, and Acknowledge.
Figure 3 illustrates the signal conditions that define
the four states. Detailed timing diagrams are in the
electrical specifications.

Microcontroller

SDA

SCL

FM24CL16

SDA

SCL

Other Slave

Device

VDD

Rmin = 1.1 K

Rmax = tR/Cbus

Figure 2. Typical System Configuration

FM24CL16

Rev 2.2
July 2003

Page 4 of 13

Stop

(Master)

Start

(Master)

Data bits

(Transmitter)

Data bit

(Transmitter)

Acknowledge

(Receiver)

SCL

SDA

Figure 3. Data Transfer Protocol

Stop Condition
A stop condition is indicated when the bus master
drives SDA from low to high while the SCL signal is
high. All operations using the FM24CL16 must end
with a Stop condition. If an operation is pending
when a Stop is asserted, the operation will be aborted.
The master must have control of SDA (not a memory
read) in order to assert a Stop condition.

Start Condition
A Start condition is indicated when the bus master
drives SDA from high to low while the SCL signal is
high. All read and write transactions begin with a
Start condition. An operation in progress can be
aborted by asserting a Start condition at any time.
Aborting an operation using the Start condition will
prepare the FM24CL16 for a new operation.

If during operation the power supply drops below the
specified VDD minimum, the system should issue a
Start condition prior to performing another operation.

Data/Address Transfer
All data transfers (including addresses) take place
while the SCL signal is high. Except under the two
conditions described above, the SDA signal should
not change while SCL is high. For system design
considerations, keeping SCL in a low state while idle
improves robustness.

Acknowledge
The Acknowledge takes place after the 8

data bit has

been transferred in any transaction. During this state,
the transmitter should release the SDA bus to allow
the receiver to drive it. The receiver drives the SDA
signal low to acknowledge receipt of the byte. If the
receiver does not drive SDA low, the condition is a
No-Acknowledge and the operation is aborted.

The receiver would fail to acknowledge for two
distinct reasons. First is that a byte transfer fails. In
this case, the No-Acknowledge ends the current
operation so that the part can be addressed again.
This allows the last byte to be recovered in the event
of a communication error.

Second and most common, the receiver does not
acknowledge to deliberately end an operation. For
example, during a read operation, the FM24CL16
will continue to place data onto the bus as long as
the receiver sends Acknowledges (and clocks).
When a read operation is complete and no more data
is needed, the receiver must not acknowledge the
last byte. If the receiver acknowledges the last byte,
this will cause the FM24CL16 to attempt to drive the
bus on the next clock while the master is sending a
new command such as a Stop.

Slave Address
The first byte that the FM24CL16 expects after a
Start condition is the slave address. As shown in
Figure 4, the slave address contains the device type,
the page of memory to be accessed, and a bit that
specifies if the transaction is a read or a write.

Bits 7-4 are the device type and should be set to
1010b for the FM24CL16. The device type allows
other types of functions to reside on the 2-wire bus
within an identical address range. Bits 3-1 are the
page select. They specify the 256-byte block of
memory that is targeted for the current operation. Bit
0 is the read/write bit. A 0 indicates a write
operation.

FM24CL16

Rev 2.2
July 2003

Page 5 of 13

R/W

Slave ID

Page

Select

Figure 4. Slave Address

Word Address
After the FM24CL16 (as receiver) acknowledges the
slave ID, the master will place the word address on
the bus for a write operation. The word address is the
lower 8-bits of the address to be combined with the 3-
bits of the page select to specify the exact byte to be
written. The complete 11-bit address is latched
internally.

No word address occurs for a read operation, though
the 3-bit page select is latched internally. Reads
always use the lower 8-bits that are held internally in
the address latch. That is, reads always begin at the
address following the previous access. A random read
address can be loaded by doing a write operation as
explained below.

After transmission of each data byte, just prior to the
acknowledge, the FM24CL16 increments the internal
address latch. This allows the next sequential byte to
be accessed with no additional addressing. After the
last address (7FFh) is reached, the address latch will
roll over to 000h. There is no limit on the number of
bytes that can be accessed with a single read or write
operation.

Data Transfer
After all address information has been transmitted,
data transfer between the bus master and the
FM24CL16 can begin. For a read operation the
device will place 8 data bits on the bus then wait for
an acknowledge. If the acknowledge occurs, the next
sequential byte will be transferred. If the
acknowledge is not sent, the read operation is
concluded. For a write operation, the FM24CL16 will
accept 8 data bits from the master then send an
acknowledge. All data transfer occurs MSB (most
significant bit) first.

Memory Operation

The FM24CL16 is designed to operate in a manner
very similar to other 2-wire interface memory
products. The major differences result from the
higher performance write capability of FRAM
technology. These improvements result in some
differences between the FM24CL16 and a similar
configuration EEPROM during writes. The complete
operation for both writes and reads is explained
below.

Write Operation
All writes begin with a slave ID then a word address
as previously mentioned. The bus master indicates a
write operation by setting the LSB of the Slave
Address to a 0. After addressing, the bus master
sends each byte of data to the memory and the
memory generates an acknowledge condition. Any
number of sequential bytes may be written. If the
end of the address range is reached internally, the
address counter will wrap from 7FFh to 000h.

Unlike other nonvolatile memory technologies, there
is no write delay with FRAM. The entire memory
cycle occurs in less time than a single bus clock.
Therefore, any operation including read or write can
occur immediately following a write. Acknowledge
polling, a technique used with EEPROMs to
determine if a write is complete is unnecessary and
will always return a `ready' condition.

An actual memory array write occurs after the 8

data bit is transferred. It will be complete before the
acknowledge is sent. Therefore, if the user desires to
abort a write without altering the memory contents,
this should be done using start or stop condition
prior to the 8

data bit. The FM24CL16 needs no

page buffering.

The memory array can be write protected using the
WP pin. Setting the WP pin to a high condition
(VDD) will write-protect all addresses. The
FM24CL16 will not acknowledge data bytes that are
written to protected addresses. In addition, the
address counter will not increment if writes are
attempted to these addresses. Setting WP to a low
state (VSS) will deactivate this feature.

Figure 5 and 6 below illustrates both a single-byte
and multiple-byte writes.

FM24CL16

Rev 2.2
July 2003

Page 6 of 13

Slave Address

Word Address

Data Byte

By Master

By FM24CL16

Start

Address & Data

Stop

Acknowledge

Figure 5. Single Byte Write

Slave Address

Word Address

Data Byte

By Master

By FM24CL16

Start

Address & Data

Stop

Acknowledge

Data Byte

Figure 6. Multiple Byte Write

Read Operation
There are two types of read operations. They are
current address read and selective address read. In a
current address read, the FM24CL16 uses the internal
address latch to supply the lower 8 address bits. In a
selective read, the user performs a procedure to set
these lower address bits to a specific value.

Current Address & Sequential Read
As mentioned above the FM24CL16 uses an internal
latch to supply the lower 8 address bits for a read
operation. A current address read uses the existing
value in the address latch as a starting place for the
read operation. This is the address immediately
following that of the last operation.

To perform a current address read, the bus master
supplies a slave address with the LSB set to 1. This
indicates that a read operation is requested. The 3
page select bits in the slave ID specify the block of
memory that is used for the read operation. On the
next clock, the FM24CL16 will begin shifting out
data from the current address. The current address is
the 3 bits from the slave ID combined with the 8 bits
that were in the internal address latch.

Beginning with the current address, the bus master
can read any number of bytes. Thus, a sequential read
is simply a current address read with multiple byte
transfers. After each byte, the internal address counter
will be incremented. Each time the bus master
acknowledges a byte this indicates that the
FM24CL16 should read out the next sequential byte.

There are four ways to properly terminate a read
operation. Failing to properly terminate the read will
most likely create a bus contention as the FM24CL16
attempts to read out additional data onto the bus. The
four valid methods are as follows.

1.

The bus master issues a no-acknowledge in the
9

clock cycle and a stop in the 10

clock cycle.

This is illustrated in the diagrams below. This is
the preferred method.

The bus master issues a no-acknowledge in the
9

clock cycle and a start in the 10

The bus master issues a stop in the 9

clock

cycle. Bus contention may result.

The bus master issues a start in the 9

clock

cycle. Bus contention may result.

If the internal address reaches 7FFh it will wrap
around to 000h on the next read cycle. Figures 7 and
8 show the proper operation for current address reads.

Selective (Random) Read
A simple technique allows a user to select a random
address location as the starting point for a read
operation. It uses the first two bytes of a write
operation to set the internal address byte followed by
subsequent read operations.

To perform a selective read, the bus master sends out
the slave address with the LSB set to 0. This specifies
a write operation. According to the write protocol, the
bus master then sends the word address byte that is
loaded into the internal address latch. After the
FM24CL16 acknowledges the word address, the bus
master issues a start condition. This simultaneously
aborts the write operation and allows the read

FM24CL16

Rev 2.2
July 2003

Page 7 of 13

command to be issued with the slave address set to 1.
The operation is now a current address read. This

operation is illustrated in Figure 9.

Slave Address

Data Byte

By Master

By FM24CL16

Start

Address

Stop

Acknowledge

Data

Figure 7. Current Address Read

Slave Address

Data Byte

1 P

By Master

By FM24CL16

Start

Address

Stop

Acknowledge

Data

Data Byte

Acknowledge

Figure 8. Sequential Read

Slave Address

Data Byte

1 P

By Master

By FM24CL16

Start

Address

Stop

Acknowledge

Data

Data Byte

Acknowledge

Slave Address

Word Address

Start

Address

Acknowledge

Figure 9. Selective (Random) Read

Endurance

A typical EEPROM has a write endurance
specification that is fixed. Surpassing the specified
level of cycles on an EEPROM usually leads to a
hard memory failure. The 24CL16 has no such
limitation.

Applications

The versatility of FRAM technology fits into many
diverse applications. Clearly the strength of higher
write endurance and faster writes make FRAM
superior to EEPROM in all but one-time
programmable applications. The advantage is most
obvious in data collection environments where writes
are frequent and data must be nonvolatile.

The attributes of fast writes and high write endurance
combine in many innovative ways. A short list of
ideas is provided here.

1.

Data collection. In applications where data is

collected and saved, FRAM provides a superior
alternative to other solutions. It is more cost effective
than battery backup for SRAM and provides better
write attributes than EEPROM.

2.

Configuration. Any nonvolatile memory can

retain a configuration. However, if the configuration
changes and power failure is a possibility, the higher
write endurance of FRAM allows changes to be
recorded without restriction. Any time the system
state is altered, the change can be written. This avoids
writing to memory on power down when the available
time is short and power scarce.

FM24CL16

Rev 2.2
July 2003

Page 8 of 13

High noise environments. Writing to EEPROM

in a noisy environment can be challenging. When
severe noise or power fluctuations are present, the
long write time of EEPROM creates a window of
vulnerability during which the write can be corrupted.
The fast write of FRAM is complete within a
microsecond. This time is typically too short for noise
or power fluctuation to disturb it.

4.

Time to market. In a complex system, multiple

software routines may need to access the nonvolatile
memory. In this environment the time delay
associated with programming EEPROM adds undue
complexity to the software development. Each
software routine must wait for complete programming
before allowing access to the next routine. When time
to market is critical, FRAM can eliminate this simple
obstacle. As soon as a write is issued to the
FM24CL16, it is effectively done -- no waiting.

5.

RF/ID. In the area of contactless memory, FRAM

provides an ideal solution. Since RF/ID memory is

powered by an RF field, the long programming time
and high current consumption needed to write
EEPROM is unattractive. FRAM provides a superior
solution. The FM24CL16 is suitable for multi-chip
RF/ID products.

6.

Maintenance tracking. In sophisticated systems,

the operating history and system state during a failure
is important knowledge. Maintenance can be
expedited when this information has been recorded.
Due to the high write endurance, FRAM makes an
ideal system log. In addition, the convenient 2-wire
interface of the FM24CL16 allows memory to be
distributed throughout the system using minimal
additional resources.

FM24CL16

Rev 2.2
July 2003

Page 9 of 13

Electrical Specifications

Absolute Maximum Ratings

Symbol Description Ratings

Power Supply Voltage with respect to V

-1.0V to +5.0V

Voltage on any pin with respect to V

-1.0V to +5.0V

and V

< V

+1.0V

STG

Storage

Temperature

-55

C to + 125

LEAD

Lead temperature (Soldering, 10 seconds)

300

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device.
This is a stress rating only, and the functional operation of the device at these or any other conditions above
those listed in the operational section of this specification is not implied. Exposure to absolute maximum
ratings conditions for extended periods may affect device reliability.

DC Operating Conditions (T

= -40

C to + 85

C, V

=2.7V to 3.65V unless otherwise specified)

Symbol Parameter

Min

Typ

Max

Units

Notes

Main Power Supply

2.7

3.65

VDD Supply Current
@ SCL = 100 kHz
@ SCL = 400 kHz
@ SCL = 1 MHz

150
300

Standby

Current

Input Leakage Current

Output Leakage Current

Input High Voltage

0.7 V

+ 0.5

Input Low Voltage

-0.3

0.3 V

Output Low Voltage
@ I

= 3.0 mA

0.4

Address Input Resistance (WP, A2-A0)
For V

= V

(max)

For V

= V

(min)

HYS

Input Hysteresis

0.05 V

V 4

Notes
1.

SCL toggling between V

-0.3V and V

, other inputs V

or V

-0.3V.

SCL = SDA = V

. All inputs V

or V

. Stop command issued.

or V

OUT

= V

to V

. Does not apply to pins with pull down resistors.

This parameter is characterized but not tested.

The input pull-down circuit is strong (50K

) when the input voltage is below V

and much weaker (1M

)

when the input voltage is above V

FM24CL16

Rev 2.2
July 2003

Page 10 of 13

AC Parameters (T

= -40

C to + 85

C, V

=2.7V to 3.65V unless otherwise specified)

Symbol Parameter

Min Max Min Max Min Max Units Notes

SCL

Clock

Frequency

0 100 0 400 0 1000

kHz 1

LOW

Clock

Low

Period

4.7 1.3 0.6

HIGH

Clock

High

Period

4.0 0.6 0.4

SCL Low to SDA Data Out Valid

0.9

0.55

BUF

Bus Free Before New Transmission

4.7

1.3

0.5

HD:STA

Start Condition Hold Time

4.0

0.6

0.25

SU:STA

Start Condition Setup for Repeated
Start

4.7 0.6 0.25

HD:DAT

Data

Hold

Time

0 0 0 ns

SU:DAT

Data

Setup

Time

250 100 100 ns

Input

Rise

Time

1000 300 300 ns 2

Input

Fall

Time

300 300 100 ns 2

SU:STO

Stop Condition Setup

4.0

0.6

0.25

Data Output Hold
(from SCL @ V

)

0 0 0 ns

Noise Suppression Time Constant
on SCL, SDA

50 50 50 ns

Notes : All SCL specifications as well as start and stop conditions apply to both read and write operations.
1

The speed-related specifications are guaranteed characteristic points from DC to 1 MHz.

This parameter is periodically sampled and not 100% tested.

Capacitance (T

= 25

C, f=1.0 MHz, V

= 3V)

Symbol Parameter Max

Units

Notes

I/O

Input/output capacitance (SDA)

Input

capacitance

6 pF

Notes
1

This parameter is periodically sampled and not 100% tested.

AC Test Conditions
Input Pulse Levels

0.1 V

to 0.9 V

Input rise and fall times

10 ns

Input and output timing levels

0.5 V

Equivalent AC Load Circuit

3.65V

Output

1100

100 pF

FM24CL16

Rev 2.2
July 2003

Page 11 of 13

Diagram Notes
All start and stop timing parameters apply to both read and write cycles. Clock specifications are identical for read
and write cycles. Write timing parameters apply to slave address, word address, and write data bits. Functional
relationships are illustrated in the relevant data sheet sections. These diagrams illustrate the timing parameters only.

Read Bus Timing

SU:SDA

Start

Stop Start

BUF

HIGH

1/fSCL

LOW

Acknowledge

HD:DAT

SU:D AT

SCL

SDA

Write Bus Timing

SU:STO

Start

Stop Start

Acknowledge

HD:DAT

HD:STA

SU:DAT

SCL

SDA

Data Retention

= 2.7V to 3.65V unless otherwise specified)

Parameter Min

Units

Notes

Data Retention

Years

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