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Электронный компонент: GLT4160L04-50J3

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G -LINK
GLT4160L04
4M X 4 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT
May 2001 (Rev.3.1)
G-Link Technology
2701 Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
G-Link Technology Corporation,Taiwan
6F, No. 24-2, Industry E. RD, IV, Science Based
Industrial Park, Hsin Chu, Taiwan.
- 1 -
Features :
Description :
4,194,304 words by 4 bits organization.
Fast access time and cycle time
Low power dissipation.
Read-Modify-Write,
RAS
-Only Refresh,
CAS
-Before-
RAS
Refresh, Hidden Refresh.
2,048 refresh cycles per 32ms.
Available in 300 mil 26(24) SOJ and TSOPII.
3.3V
0.3V Vcc Power Supply voltage
.
All inputs and Outputs are LVTTL compatible.
Extended Data-Out (EDO) Page access
cycle.
Self-refresh Capability
. (S-Version).
The GLT4160L04 is a high-performance
CMOS dynamic random access memory
containing 16,777,216 bits organized in a x4
configuration. The GLT4160L04 offers page
cycle access with Extended Data Output.
The GLT4160L04 has 11 row- and 11
column-addresses, and accepts 2048-cycle
refresh in 32 ms.
The GLT4160L04 provides EDO PAGE
MODE operation which allows for fast data
access within a row-address defined
boundary, up to 2048 x 4 bits with cycle
times as short as 18ns.
HIGH PERFORMANCE
40
50
60
70
Max.
RAS
Access Time, (t
RAC
)
40 ns
50 ns
60 ns
70 ns
Max. Column Address Access Time, (t
AA
)
20 ns
25 ns
30 ns
35 ns
Min. Extended Data Out Page Mode Cycle Time, (t
PC
)
18 ns
20 ns
25 ns
30 ns
Min. Read/Write Cycle Time, (t
RC
)
70 ns
84 ns
104 ns 124 ns
Max.
CAS
Access Time (t
CAC
)
12 ns
13 ns
15 ns
20 ns
G -LINK
GLT4160L04
4M X 4 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT
May 2001 (Rev.3.1)
G-Link Technology
2701 Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
G-Link Technology Corporation,Taiwan
6F, No. 24-2, Industry E. RD, IV, Science Based
Industrial Park, Hsin Chu, Taiwan.
- 2 -
Pin Configuration :
V
cc
DQ
0
A
0
A
1
A
2
A
3
1
2
3
4
5
6
8
9
10
11
12
13
22
21
19
18
17
16
15
14
26
25
24
23
A
9
A
8
A
7
A
6
OE
CAS
V
SS
DQ
3
DQ
1
WE
RAS
NC
V
CC
DQ
2
A
5
A
4
V
SS
A
10
V
cc
DQ
0
A
10
A
0
A
1
A
2
A
3
1
2
3
4
5
6
8
9
10
11
12
13
22
21
19
18
17
16
15
14
26
25
24
23
A
9
A
8
A
7
A
6
OE
CAS
V
SS
DQ
3
DQ
1
WE
RAS
NC
V
CC
DQ
2
A
5
A
4
V
SS
Pin Descriptions:
Name
Function
A
0
- A
10
Address Inputs
RAS
Row Address Strobe
CAS
Column Address Strobe
WE
Write Enable
OE
Output Enable
DQ
0
- DQ
3
Data Inputs / Outputs
V
CC
+3.3V Power Supply
V
SS
Ground
NC
No Connection
GLT4160L04
300mil 26(24) TSOPII
GLT4160L04
300mil 26(24) SOJ
G -LINK
GLT4160L04
4M X 4 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT
May 2001 (Rev.3.1)
G-Link Technology
2701 Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
G-Link Technology Corporation,Taiwan
6F, No. 24-2, Industry E. RD, IV, Science Based
Industrial Park, Hsin Chu, Taiwan.
- 3 -
Absolute Maximum Ratings*
Capacitance*
T
A
=25
C, V
CC
=3.3V
0.3V, V
SS
=0V
Operating Temperature, T
A
(ambient)
.................................................0
C to
+70
C
For Extended Temperature.................-20
C to 85
C
Storage Temperature(plastic)............-55
C to +150
C
Voltage Relative to V
SS
........................-0.5V to + 4.6V
Short Circuit Output Current...............................20mA
Power Dissipation...............................................1.0W
Symbol
C
IN1
C
IN2
C
OUT
Parameter
Address Input
RAS, CAS, WE, OE
Data Input/Output
Max.
5
7
7
Unit
pF
pF
pF
*Note: Operation above Absolute Maximum Ratings can
aversely affect device reliability.
*Note: Capacitance is sampled and not 100% tested
Electrical Specifications
l
All voltages are referenced to GND.
l
After power up, wait more than 200
s and then, execute eight
CAS
-before-
RAS
or
RAS
-only
refresh cycles as dummy cycles to initialize internal circuit.
Block Diagram :
NO.2 CLOCK
GENERATOR
COLUMN-
ADDRESS
BUFFER(11)
REFRESH
CONTROLLER
REFRESH
COUNTER
ROW
ADDRESS
BUFFERS(11)
NO.1 CLOCK
GENERATOR
11
11
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
A
9
A
10
RAS
11
11
COLUMN
DECODER
DATA-OUT
BUFFER
DATA-IN
BUFFER
SENSE AMPLIFIERS
I/O GATING
2048 x 1024 x 4
MEMORY
ARRAY
2048
2048
4
4
4
4
WE
CAS
DQ
0
DQ
1
DQ
2
DQ
3
OE
V
DD
V
SS
ROW DECODER
2048
A
0
G -LINK
GLT4160L04
4M X 4 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT
May 2001 (Rev.3.1)
G-Link Technology
2701 Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
G-Link Technology Corporation,Taiwan
6F, No. 24-2, Industry E. RD, IV, Science Based
Industrial Park, Hsin Chu, Taiwan.
- 4 -
Truth Table:
Function
RAS
CAS
WE
OE
ADDRESS
DATA-IN/OUT
t
R
t
C
DQ1-DQ4
Standby
H
H
X
X
X
X
X
High-Z
READ
L
L
H
L
ROW
COL
Data-Out
EARLY WRITE
L
L
L
X
ROW
COL
Data-In
READ WRITE
L
L
H
L
L
H
ROW
COL
Data-Out,Data-In
EDO-PAGE-MODE
1st Cycle
L
H
L
H
L
ROW
COL
Data-Out
READ
2nd cycle
L
H
L
H
L
n/a
COL
Data-Out
EDO-PAGE-MODE
1st Cycle
L
H
L
L
X
ROW
COL
Data-In
EARLY-WRITE
2nd cycle
L
H
L
L
X
n/a
COL
Data-In
EDO-PAGE-MODE
1st Cycle
L
H
L
H
L
L
H
ROW
COL
Data-Out,Data-In
READ-WRITE
2nd cycle
L
H
L
H
L
L
H
n/a
COL
Data-Out,Data-In
RAS
-ONLY REFRESH
L
H
X
X
ROW
n/a
High-Z
HIDDEN REFRESH
READ
L
H
L
L
H
L
ROW
COL
Data-Out
WRITE
L
H
L
L
L
X
ROW
COL
Data-In
CBR REFRESH
H
L
L
H
X
X
X
High-Z
SELF REFRESH
H
L
L
H
X
X
X
High-Z
G -LINK
GLT4160L04
4M X 4 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT
May 2001 (Rev.3.1)
G-Link Technology
2701 Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
G-Link Technology Corporation,Taiwan
6F, No. 24-2, Industry E. RD, IV, Science Based
Industrial Park, Hsin Chu, Taiwan.
- 5 -
DC and Operating Characteristics (1-2)
T
A
= 0
C to 70
C, -20
C to 85
C V
CC
=3.3V
0.3V, V
SS
=0V, unless otherwise specified.
Sym.
Parameter
Test Conditions
Access
Time
Min.
Typ
Max.
Unit Notes
I
LI
Input Leakage Current
(any input pin)
0V
V
IN
V
CC
+0.3V
(All other pins not under
test=0V)
-5
+5
A
I
LO
Output Leakage Current
(for High-Z State)
0V
V
out
V
CC
Output is disabled (Hiz)
-5
+5
A
I
CC1
Operating Current,
Random READ/WRITE
t
RC
= t
RC
(min.)
t
RAC
= 40ns
t
RAC
= 50ns
t
RAC
= 60ns
t
RAC
= 70ns
130
120
80
70
mA
1,2
I
CC2
Standby Current (TTL)
RAS
,
CAS
at V
IH
other inputs
V
SS
1
mA
I
CC3
Refresh Current,
RAS
-Only
RAS
cycling,
CAS
at V
IH
t
RC
= t
RC
(min.)
t
RAC
= 40ns
t
RAC
= 50ns
t
RAC
= 60ns
t
RAC
= 70ns
130
120
80
70
mA
2
I
CC4
Operating Current,
EDO Page Mode
RAS
at V
IL
,
CAS
address
cycling:t
PC
=t
PC
(min.)
t
RAC
= 40ns
t
RAC
= 50ns
t
RAC
= 60ns
t
RAC
= 70ns
130
120
80
70
mA
1,2
I
CC5
Refresh Current,
CAS
Before
RAS
RAS
,
CAS
address cycling:
t
RC
=t
RC
(min.)
t
RAC
= 40ns
t
RAC
= 50ns
t
RAC
= 60ns
t
RAC
= 70ns
130
120
80
70
mA
1
I
CC6
Standby Current, (CMOS)
RAS
V
CC
-0.2V,
CAS
V
CC
-0.2V,
All other inputs V
SS
300
A
1,5
I
CC7
Self refresh Current
RAS
=
CAS
=0.2V,
WE = OE = A
0
~A
10
=V
CC
-0.2V or
0.2V
DQ
0
~DQ
3
=V
CC
-0.2V,0.2V or
Open
300
A
V
IL
Input Low Voltage
-0.3
+0.8
V
3
V
IH
Input High Voltage
2.0
V
CC
+0.3
V
4
V
OL
Output Low Voltage
I
OL
= 2mA
0.4
V
V
OH
Output High Voltage
I
OH
= -2mA
2.4
V
Notes:
1. I
CC
is dependent on output loading when the device output is selected. Specified I
CC
(max.) is measured with the output open.
2. I
CC
is dependent upon the number of address transitions specified ICC(max.) is measured with a maximum of one transition per address cycle
in random Read/Write and EDO Fast Page Mode.
3. Specified V
IL
(min.) is steady state operation. During transitions V
IL
(min.) may undershoot to 1V for a period not to exceed 15ns. All AC
parameters are measured with V
IL
(min.)
V
SS
and V
IH
(max.)
V
CC
.
4. Specified V
IH
(max.) is steady state operation . During transitions V
IH
(max.) may overshoot to V
CC
+1V for a period not to exceed 15ns. All AC
parameters are measured with V
IL
(min.)
V
SS
and VIH(max.)
V
CC
.
5. S-Version.
G -LINK
GLT4160L04
4M X 4 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT
May 2001 (Rev.3.1)
G-Link Technology
2701 Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
G-Link Technology Corporation,Taiwan
6F, No. 24-2, Industry E. RD, IV, Science Based
Industrial Park, Hsin Chu, Taiwan.
- 6 -
AC Characteristics
T
A
=0
C to 70
C , -20
C to 85
C V
CC
= 3.3 V
0.3V, VIH/VIL = 3/0 V, V
OH
/V
OL
= 2/0.8V
An initial pause of 200
s and 8
CAS
-before-
RAS
or
RAS
-only refresh cycles are required after power-up.
40
50
60
70
Parameter
Symbol Min. Max. Min. Max. Min. Max. Min. Max. Unit Notes
Read or Write Cycle Time
t
RC
70
84
104
124
ns
Read Modify Write Cycle Time
t
RWC
91
116
140
170
ns
RAS Precharge Time
t
RP
25
30
40
50
ns
RAS Pulse Width
t
RAS
40
10K
50
10k
60
10k
70
10k
ns
Access Time from RAS
t
RAC
40
50
60
70
ns
1,2,3
Access Time from CAS
t
CAC
12
13
15
20
ns 1,5,10
Access Time from Column Address
t
AA
20
25
30
35
ns
1,5,6
CAS to Output Low-Z
t
CLZ
0
3
3
3
ns
CAS to Output High-Z
t
CEZ
3
8
3
13
3
15
3
20
ns
RAS Hold Time
t
RSH
12
13
15
20
ns
CAS Hold Time
t
CSH
34
38
45
50
ns
CAS Pulse Width
t
CAS
7
10k
8
10k
10
10k
15
10k
ns
RAS to CAS Delay Time
t
RCD
18
28
20
37
20
45
20
50
ns
RAS to Column Address Delay Time
t
RAD
13
20
15
25
15
30
15
35
ns
7
CAS to RAS Precharge Time
t
CRP
5
5
5
5
ns
Row Address Set-Up Time
t
ASR
0
0
0
0
ns
Row Address Hold Time
t
RAH
8
10
10
10
ns
Column Address Set-Up Time
t
ASC
0
0
0
0
ns
Column Address Hold Time
t
CAH
6
8
10
15
ns
Column Address to RAS Lead Time
t
RAL
20
25
30
35
ns
Column Address Hold Time Referenced to RAS
t
AR
34
40
45
50
ns
Read Command Set-Up Time
t
RCS
0
0
0
0
ns
Read Command Hold Time Referenced to CAS
t
RCH
0
0
0
0
ns
4
Read Command Hold Time Referenced to RAS
t
RRH
0
0
0
0
ns
4
Write Command Set-Up Time
t
WCS
0
0
0
0
ns
8,9
Write Command Hold Time
t
WCH
6
10
10
15
ns
Write Command Pulse Width
t
WP
6
10
10
15
ns
Write Command to RAS Lead Time
t
RWL
12
13
15
30
ns
Write Command to CAS Lead Time
t
CWL
8
8
10
15
ns
G -LINK
GLT4160L04
4M X 4 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT
May 2001 (Rev.3.1)
G-Link Technology
2701 Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
G-Link Technology Corporation,Taiwan
6F, No. 24-2, Industry E. RD, IV, Science Based
Industrial Park, Hsin Chu, Taiwan.
- 7 -
AC Characteristics
40
50
60
70
Parameter
Symbol Min. Max. Min. Max. Min. Max. Min. Max. Unit Notes
Data Set-Up Time
t
DS
0
0
0
0
ns
Data Hold Time
t
DH
7
8
10
15
ns
Data Hold Time Referenced to RAS
t
DHR
36
40
45
50
ns
RAS to WE Delay Time
t
RWD
54
67
79
94
ns
CAS to WE Delay Time
t
CWD
24
30
34
44
ns
Column Address to WE Delay Time
t
AWD
32
42
49
59
ns
CAS Precharge to WE Delay
t
CPWD
47
47
54
64
ns
RAS to CAS Precharge Time
t
RPC
0
5
5
5
ns
CAS precharge time ( CAS Before RAS counter
test cycle)
t
CPT
20
20
20
25
ns
Access Time from CAS Precharge
t
CPA
22
28
35
40
ns
EDO Page Mode Cycle Time
t
PC
18
20
25
30
ns
EDO Page Mode Read-Modify-Write Cycle Time
t
PRWC
50
47
56
71
ns
CAS Precharge Time (EDO Page Mode)
t
CP
6
8
10
10
ns
RAS Pulse Width (EDO Page Mode Only)
t
RASP
40
100k
50
100k
60
100k
70
100k
ns
RAS Hold Time from CAS precharge
t
RHCP
30
30
35
40
ns
Access Time from OE
t
OEA
12
13
15
0
20
ns
8
OE to Data Delay Time
t
OED
8
13
15
20
ns
OE to Output Low-Z
t
OLZ
3
3
0
0
ns
OE to Output High-Z
t
OEZ
3
8
3
13
3
15
3
20
ns
WE to Data Delay
t
WED
15
15
15
20
ns
OE Command Hold Time
t
OEH
7
13
15
20
ns
Data Output Hold after CAS low
t
DOH
3
5
5
5
ns
RAS to Output High-Z
t
REZ
3
8
3
13
3
15
3
20
ns
WE to Output High-Z
t
WEZ
3
10
3
13
3
15
3
20
ns
OE to CAS Hold Time
t
OCH
5
5
5
5
ns
CAS Hold Time to OE
t
CHO
5
5
5
5
ns
OE Precharge Time
t
OEP
5
5
5
5
ns
WE Puts width (EDO mixed read write cycle)
t
WPE
5
5
5
5
ns
CAS Set-Up Time for CAS -before- RAS Cycle
t
CSR
5
5
5
5
ns
G -LINK
GLT4160L04
4M X 4 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT
May 2001 (Rev.3.1)
G-Link Technology
2701 Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
G-Link Technology Corporation,Taiwan
6F, No. 24-2, Industry E. RD, IV, Science Based
Industrial Park, Hsin Chu, Taiwan.
- 8 -
40
50
60
70
Parameter
Symbol
Min. Max. Min. Max. Min. Max. Min. Max. Unit Notes
CAS Hold Time for CAS -before- RAS Cycle
t
CHR
8
10
10
15
ns
WE to RAS precharge time ( CAS Before RAS
refresh )
t
WRP
10
10
10
10
ns
WE to RAS hold time ( CAS Before RAS
refresh )
t
WRH
10
10
10
10
ns
Transition Time
t
T
2
50
2
50
2
50
2
50
ns
Refresh Period (2,048 cycles)
t
REF
32
32
32
32
ms
Refresh Period (S-Version)
t
REF
128
128
128
128
ms
RAS Pulse Width ( CAS Before RAS Self refresh
)
t
RASS
100
100
100
100
s
RAS precharge Time ( CAS Before RAS Self
refresh )
t
RPS
70
90
110
130
ns
CAS Hold Time ( CAS Before RAS Self refresh )
t
CHS
-50
-50
-50
-50
ns
G -LINK
GLT4160L04
4M X 4 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT
May 2001 (Rev.3.1)
G-Link Technology
2701 Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
G-Link Technology Corporation,Taiwan
6F, No. 24-2, Industry E. RD, IV, Science Based
Industrial Park, Hsin Chu, Taiwan.
- 9 -
TEST MODE CYCLE
40
50
60
70
Parameter
Symbol Min. Max. Min. Max. Min. Max. Min. Max. Unit
Notes
Random read or write cycle time
t
RC
89
89
109
129
ns
Read-modify-write cycle time
t
RWC
121
121
145
175
ns
Access time from RAS
t
RAC
55
55
65
75
ns
1,2,3,7
Access time from CAS
t
CAC
18
18
20
25
ns
1,3,7
Access time from column address
t
AA
30
30
35
40
ns
1,2,7
RAS pulse width
t
RAS
55
10k
55
10k
65
10k
75
10k
ns
CAS pulse width
t
CAS
13
10k
13
10k
15
10k
20
10k
ns
RAS hold time
t
RSH
18
18
20
25
ns
CAS hold time
t
CSH
43
43
50
55
ns
Column address to RAS lead time
t
RAL
30
30
35
40
ns
CAS to WE delay time
t
CWD
35
35
39
49
ns
8
RAS to WE delay time
t
RWD
72
72
84
99
ns
8
Column address to WE delay time
t
AWD
47
47
54
64
ns
8
CAS Precharge to WE delay time
t
CPWD
52
52
59
69
ns
8
EDO Page Mode cycle time
t
PC
25
25
30
35
ns
EDO page mode read-modify-write cycle time
t
PRWC
53
53
61
76
ns
RAS Pulse width (EDO page cycle)
t
RASP
55
100k
55
100k
65
100k
75
100k
ns
Access time form CAS precharge
t
CPA
33
33
40
45
ns
1
OE access time
t
OEA
18
18
20
25
ns
OE to data delay
t
OED
18
18
20
25
ns
OE command hold time
t
OEH
18
18
20
25
ns
Write command set-up time (Test mode in)
t
WTS
10
10
10
10
ns
Write command hold time (Test mode in)
t
WTH
10
10
10
10
ns
G -LINK
GLT4160L04
4M X 4 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT
May 2001 (Rev.3.1)
G-Link Technology
2701 Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
G-Link Technology Corporation,Taiwan
6F, No. 24-2, Industry E. RD, IV, Science Based
Industrial Park, Hsin Chu, Taiwan.
- 10 -
Notes:
1. Measure with a load equivalent to one TTL input and 100 pF.
2. Assumes that t
RCD
t
RCD
(max.). If t
RCD
is greater than t
RCD
(max.), access time will be t
AA
dominant.
3. Assumes that t
RAD
t
RAD
(max.). If t
RAD
is greater than t
RCD
(max.), access time will be
controlled by t
CAC
.
4. Either t
RRH
or t
RCH
must be satisfied for a Read Cycle.
5. Access time is determined by the longest of t
AA
, t
CAC
and t
CPA
.
6. Assumes that t
RAD
t
RAD
(max.).
7. Operation within the t
RAD
(max.) limit ensures that t
RAC
(max.) can be met. t
RAD
(max.)
is specified as a reference point only. If t
RAD
is greater than the specified t
RAD
(max.)
limit, the access time is controlled by t
CAA
and t
CAC
.
8. t
WCS
, t
RWD
, t
AWD
and t
CWD
are not restrictive operating parameters.
9. t
WCS
(min.) must be satisfied in an Early Write Cycle.
10. t
DS
and t
DH
are referenced to the latter occurrence of
CAS
or
WE
.
11. t
T
is measured between V
IH
(min.) and V
IL
(max.). AC-measurements assume t
T
= 2 ns.
G -LINK
GLT4160L04
4M X 4 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT
May 2001 (Rev.3.1)
G-Link Technology
2701 Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
G-Link Technology Corporation,Taiwan
6F, No. 24-2, Industry E. RD, IV, Science Based
Industrial Park, Hsin Chu, Taiwan.
- 11 -
Read CYCLE
ROW
ADDRESS
COLUMN
ADDRESS
DATA-OUT
t
RC
t
RAS
t
RP
t
CRP
t
CSH
t
RCD
t
RSH
t
CAS
t
CRP
t
ASR
t
RAH
t
RAD
t
ASC
t
CAH
t
RAL
t
RCH
t
RRH
t
AR
t
RCS
t
AA
t
OEA
t
CEZ
t
OEZ
t
CAC
t
CLZ
t
RAC
Don't Care
V
IH-
V
IL-
RAS
V
IH-
V
IL-
CAS
V
IH-
V
IL-
Address
V
IH-
V
IL-
WE
V
IH-
V
IL-
OE
V
OH-
V
OL-
DQ
Early Write Cycle
NOTE : D
OUT
= OPEN
t
RP
t
RC
t
CRP
t
CSH
t
CRP
t
RCD
t
RSH
t
CAS
t
ASR
t
RAH
t
RAD
t
ASC
t
CAH
t
RAL
t
CWL
t
RWL
t
WCR
t
WCH
t
WP
t
WCS
t
AR
t
DS
t
DH
t
DHR
DATA - IN
COLUMN
ADDRESS
ROW
ADDRESS
V
IH-
V
IL-
RAS
V
IH-
V
IL-
CAS
V
IH-
V
IL-
Address
V
IH-
V
IL-
WE
V
IH-
V
IL-
OE
V
IH-
V
IL-
DQ
Don't Care
t
RAS
G -LINK
GLT4160L04
4M X 4 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT
May 2001 (Rev.3.1)
G-Link Technology
2701 Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
G-Link Technology Corporation,Taiwan
6F, No. 24-2, Industry E. RD, IV, Science Based
Industrial Park, Hsin Chu, Taiwan.
- 12 -
OE Controlled Write Cycle
NOTE : D
OUT
= OPEN
t
RP
t
RC
t
CRP
t
CSH
t
CRP
t
RCD
t
RSH
t
CAS
t
ASR
t
RAH
t
RAD
t
ASC
t
CAH
t
RAL
DATA - IN
COLUMN
ADDRESS
ROW
ADDRESS
V
IH-
V
IL-
RAS
V
IH-
V
IL-
CAS
V
IH-
V
IL-
Address
V
IH-
V
IL-
WE
V
IH-
V
IL-
OE
V
IH-
V
IL-
DQ
Don't Care
t
RAS
t
RCS
t
CWL
t
RWL
t
WP
t
DS
t
OED
t
OEH
t
DH
Read - Modify - Write Cycle
t
RP
t
RC
t
CRP
t
CRP
t
RCD
t
RSH
VALID
DATA-OUT
COLUMN
ADDRESS
ROW
ADDR.
V
IH-
V
IL-
RAS
V
IH-
V
IL-
CAS
V
IH-
V
IL-
Address
V
IH-
V
IL-
WE
V
IH-
V
IL-
OE
V
I/OH-
V
I/OL-
DQ
Don't Care
t
RAS
VALID
DATA-IN
t
CAS
t
ASR
t
RAH
t
RAD
t
ASC
t
CAH
t
CSH
t
AWD
t
CWD
t
RWL
t
CWL
t
WP
t
OEA
t
CLZ
t
CAC
t
AA
t
RAC
t
DH
t
DS
t
OED
t
OEZ
G -LINK
GLT4160L04
4M X 4 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT
May 2001 (Rev.3.1)
G-Link Technology
2701 Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
G-Link Technology Corporation,Taiwan
6F, No. 24-2, Industry E. RD, IV, Science Based
Industrial Park, Hsin Chu, Taiwan.
- 13 -
EDO Page Mode Read Cycle
NOTE : D
OUT
= OPEN
t
RASP
t
RP
t
CRP
t
RCD
t
CAS
t
CSH
t
CP
t
CAS
t
CAS
t
CAS
t
CP
t
CP
t
PC
t
PC
t
PC
t
CSR
t
RAH
t
RAD
t
ASC
t
ASC
t
ASC
t
ASC
t
CAH
t
CAH
t
CAH
t
CAH
t
RCS
t
RCH
t
RRH
t
OEA
t
OEA
t
CAC
t
CPA
t
AA
t
OCH
t
CPA
t
AA
t
CAC
t
OEP
t
CHO
t
AA
t
CAC
t
CPA
t
CLZ
t
OLZ
t
RAC
t
CAC
t
DOH
t
OEZ
t
OEP
t
OEZ
t
OEZ
VALID
DATA-OUT
VALID
DATA-OUT
VALID
DATA-OUT
VALID
DATA-OUT
VALID
DATA-OUT
V
IH-
V
IL-
RAS
V
IH-
V
IL-
CAS
V
IH-
V
IL-
Address
V
IH-
V
IL-
WE
V
IH-
V
IL-
OE
DQ
V
OH-
V
OL-
ROW
ADDR.
COLUMN
ADDRESS
COLUMN
ADDRESS
COL.
ADDR.
COL.
ADDR.
Don't Care
t
RHCP
EDO Page Mode Early Write Cycle
NOTE : D
OUT
= OPEN
t
RASP
t
RP
t
CRP
t
RCD
t
CAS
V
IH-
V
IL-
RAS
V
IH-
V
IL-
CAS
t
CAS
t
CAS
t
CP
t
CP
t
PC
t
PC
t
RSH
t
ASR
t
RAD
t
RAH
t
ASC
t
CAH
t
CSH
t
ASC
t
ASC
t
CAH
t
CAH
t
WCS
t
WP
t
WCH
t
WCS
t
WCS
t
WCH
t
WCH
t
WP
t
WP
t
DS
t
DS
t
DS
t
DH
t
DS
t
DS
V
IH-
V
IL-
Address
V
IH-
V
IL-
WE
V
IH-
V
IL-
OE
DQ
V
IH-
V
IL-
ROW
ADDR.
COLUMN
ADDRESS
COLUMN
ADDRESS
COLUMN
ADDRESS
VALID
DATA-IN
VALID
DATA-IN
VALID
DATA-IN
Don't Care
t
RHCP
G -LINK
GLT4160L04
4M X 4 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT
May 2001 (Rev.3.1)
G-Link Technology
2701 Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
G-Link Technology Corporation,Taiwan
6F, No. 24-2, Industry E. RD, IV, Science Based
Industrial Park, Hsin Chu, Taiwan.
- 14 -
EDO Page Mode Read - Modify - Write Cycle
NOTE : D
OUT
= OPEN
t
RASP
t
RP
V
IH-
V
IL-
RAS
V
IH-
V
IL-
CAS
Don't Care
t
CSH
t
RCD
t
CAS
t
CP
t
CAS
t
RSH
t
CRP
t
RAD
t
RAH
t
ASR
t
ASC
t
CAH
t
ASC
t
CAH
t
RAL
t
PRWC
t
RCS
t
WP
t
CWL
t
WP
t
CWL
t
RWL
t
CWD
t
AWD
t
RWD
t
OEA
t
CWD
t
AWD
t
CPWD
t
OEA
t
OEH
t
RAC
t
AA
t
CAC
t
OEZ
t
OED
t
DS
t
DH
t
AA
t
CAC
t
OEZ
t
OED
t
DS
t
DH
t
CLZ
t
CLZ
VALID
DATA-OUT
VALID
DATA-IN
VALID
DATA-OUT
VALID
DATA-IN
ROW
ADDR.
COL.
ADDR.
COL.
ADDR.
V
IH-
V
IL-
Address
V
IH-
V
IL-
WE
V
IH-
V
IL-
OE
V
I/OH-
V
I/OL-
DQ
EDO PAGE READ AND WRITE MIXED CYCLE
t
RASP
t
RP
t
CAS
t
HPC
t
CAS
t
CAS
t
CP
t
CP
t
CP
t
ASR
t
HPC
t
HPC
t
RAH
t
ASC
t
CAH
t
ASC
t
ASC
t
ASC
t
CAH
t
CAH
t
CAH
t
RCS
t
RCH
t
RCS
t
RCH
t
RCH
t
WCS
t
WCH
t
WPE
t
CPA
t
CLZ
t
WED
t
WEZ
t
RAC
t
AA
t
CAC
t
OEA
t
WEZ
t
DS
t
DH
t
AA
t
REZ
VALID
DATA-OUT
VALID
DATA-OUT
VALID
DATA-OUT
VALID
DATA-IN
ROW
ADDR
COL.
ADDR
COLUMN
ADDRESS
COLUMN
ADDRESS
COLUMN
ADDRESS
V
IH-
V
IL-
V
IH-
V
IL-
V
IH-
V
IL-
V
IH-
V
IL-
V
IH-
V
IL-
V
I/OH-
V
I/OL-
RAS
CAS
ADDRESS
WE
OE
DQ
0
~
DQ
3
Don't Care
G -LINK
GLT4160L04
4M X 4 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT
May 2001 (Rev.3.1)
G-Link Technology
2701 Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
G-Link Technology Corporation,Taiwan
6F, No. 24-2, Industry E. RD, IV, Science Based
Industrial Park, Hsin Chu, Taiwan.
- 15 -
CAS - Before - RAS Refresh Cycle
V
IH-
V
IL-
RAS
t
RAS
t
RAS
t
RP
t
RP
t
RC
t
RC
t
CSR
t
CSR
t
CHR
t
CHR
t
RPC
t
RPC
t
CRP
V
IH-
V
IL-
CAS
t
WRH
t
WRP
V
IH-
V
IL-
WE
t
WRP
t
WRH
Remark Address, OE : Don't care DQ : Hi - Z
RAS -Only Refresh Cycle
V
IH-
V
IL-
RAS
t
RAS
t
RAS
t
RP
t
RP
t
RC
t
RC
t
RPC
t
CRP
V
IH-
V
IL-
CAS
t
CRP
t
ASR
t
ASR
t
RAH
t
RAH
ROW
ADDRESS
ROW
ADDRESS
Address
V
IH-
V
IL-
Remark WE, OE : Don't care DQ : Hi - Z
Hidden Refresh Cycle ( Read )
t
RP
t
CRP
t
RCD
V
IH-
V
IL-
RAS
V
IH-
V
IL-
UCAS,LCAS
t
RAC
V
IH-
V
IL-
Address
V
IH-
V
IL-
WE
V
IH-
V
IL-
OE
DQ
V
IH-
V
IL-
ROW
ADDRESS
Don't Care
t
RP
t
CAC
t
RCS
t
ASC
t
CAH
t
ASR
t
CAH
t
RAD
t
RAL
t
RSH
t
CHR
t
RC
t
RAS
t
RAS
COLUMN
ADDRESS
t
RC
t
WRH
t
AA
t
OEA
t
CLZ
t
REZ
t
CEZ
t
WEZ
t
OEZ
DATA-OUT
OPEN
t
WRP
t
RRH
G -LINK
GLT4160L04
4M X 4 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT
May 2001 (Rev.3.1)
G-Link Technology
2701 Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
G-Link Technology Corporation,Taiwan
6F, No. 24-2, Industry E. RD, IV, Science Based
Industrial Park, Hsin Chu, Taiwan.
- 16 -
Hidden Refresh Cycle ( Write )
NOTE : D
OUT
= OPEN
t
RP
t
CRP
t
RCD
V
IH-
V
IL-
RAS
V
IH-
V
IL-
CAS
t
DS
V
IH-
V
IL-
Address
V
IH-
V
IL-
WE
V
IH-
V
IL-
OE
DQ
V
IH-
V
IL-
ROW
ADDRESS
Don't Care
t
RP
t
DH
t
WP
t
WCH
t
WCS
t
ASC
t
CAH
t
ASC
t
CAH
t
RAD
t
RSH
t
RSH
t
CHR
t
RC
t
RAS
t
RAS
COLUMN
ADDRESS
DATA-IN
t
WRP
t
WRH
G -LINK
GLT4160L04
4M X 4 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT
May 2001 (Rev.3.1)
G-Link Technology
2701 Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
G-Link Technology Corporation,Taiwan
6F, No. 24-2, Industry E. RD, IV, Science Based
Industrial Park, Hsin Chu, Taiwan.
- 17 -
CAS-Before RAS Refresh Counter Test Cycle
t
CAS
t
CPT
V
IH-
V
IL-
RAS
V
IH-
V
IL-
CAS
t
RP
t
RAS
t
CSR
t
CHR
t
RSH
t
RAL
t
ASC
t
AA
t
CAC
t
RCS
t
RRH
t
RCH
t
WRP
t
WRH
t
WRH
t
WRP
t
OEA
t
CEZ
t
OEZ
t
CLZ
t
RWL
t
CWL
t
WCH
t
WCS
t
WP
t
DS
t
DH
t
RCS
t
AWD
t
CWD
t
RWL
t
CWL
t
WP
t
DH
t
DS
t
OED
t
OEZ
t
CLZ
t
CAC
t
AA
t
OEA
OPEN
COLUMN
ADDRESS
VALID DATA-OUT
VALID DATA-IN
Don't Care
VALID
DATA-IN
VALID
DATA-OUT
V
IH-
V
IL-
Address
V
IH-
V
IL-
WE
V
IH-
V
IL-
OE
V
OH-
V
OL-
DQ
V
IH-
V
IL-
WE
V
IH-
V
IL-
OE
V
IH-
V
IL-
DQ
V
IH-
V
IL-
WE
V
IH-
V
IL-
OE
V
I/OH-
V
I/OL-
DQ
Read Cycle
Write Cycle
Read-Modify-Write
t
CAH
t
WRP
t
WRH
G -LINK
GLT4160L04
4M X 4 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT
May 2001 (Rev.3.1)
G-Link Technology
2701 Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
G-Link Technology Corporation,Taiwan
6F, No. 24-2, Industry E. RD, IV, Science Based
Industrial Park, Hsin Chu, Taiwan.
- 18 -
TEST MODE IN CYCLE
t
RP
t
RC
t
RAS
t
RP
t
RPC
t
CP
t
CSR
t
CHR
t
WTS
t
WTH
t
CEZ
OPEN
t
RPC
Don't Care
V
IH-
V
IL-
V
IH-
V
IL-
V
IH-
V
IL-
V
I/OH-
V
I/OL-
RAS
CAS
WE
DQ
Test Mode
By using the test mode, the test time can be reduced. The reason for this is that, the memory emulates the x
16-bit organization during test mode. Don't care about the input levels of the CAS input A0, A1 .
(1) Setting the mode
Executing the test mode cycle (WE , CAS before RAS refresh cycle ) sets the test mode.
(2) Write / read operation
When either a "0" or a "1" is written to the input pin in test mode, this data is written to 16 bits of memory
cell.
Next, when the data is read from the output pin at the same address, the cell be checked.
Output = "1" Normal write (all memory cells)
Output = "0" Abnormal write
(3) Refresh
Refresh in the test mode must be performed with the RAS / CAS cycle or with the WE, CAS before RAS
refresh cycle. The WE, CAS before RAS refresh cycle use the same counter as the CAS before RAS
refresh's internal counter.
(4) Mode Cancellation
The test mode is cancelled by executing one cycle of RAS only refresh cycle or CAS before RAS refresh
cycle.
G -LINK
GLT4160L04
4M X 4 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT
May 2001 (Rev.3.1)
G-Link Technology
2701 Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
G-Link Technology Corporation,Taiwan
6F, No. 24-2, Industry E. RD, IV, Science Based
Industrial Park, Hsin Chu, Taiwan.
- 19 -
CAS-BEFORE-RAS SELF REFRESH CYCLE
t
RPS
t
RASS
t
RP
t
RPC
t
CP
t
CSR
t
CEZ
OPEN
t
RPC
Don't Care
V
IH-
V
IL-
V
IH-
V
IL-
V
I/OH-
V
I/OL-
RAS
CAS
DQ
t
CHS
t
WRP
t
WRH
V
IH-
V
IL-
WE
NOTE : OE , Address = Don't Care
G -LINK
GLT4160L04
4M X 4 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT
May 2001 (Rev.3.1)
G-Link Technology
2701 Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
G-Link Technology Corporation,Taiwan
6F, No. 24-2, Industry E. RD, IV, Science Based
Industrial Park, Hsin Chu, Taiwan.
- 20 -
Ordering Information
Part Number
SPEED
POWER
FEATURE
TEMPERATURE
PACKAGE
GLT4160L04-40J3
40ns
Normal
EDO
Commercial
SOJ 300mil 26(24)L
GLT4160L04-50J3
50ns
Normal
EDO
Commercial
SOJ 300mil 26(24)L
GLT4160L04-60J3
60ns
Normal
EDO
Commercial
SOJ 300mil 26(24)L
GLT4160L04-70J3
70ns
Normal
EDO
Commercial
SOJ 300mil 26(24)L
GLT4160L04E-40J3
40ns
Normal
EDO
Extended
SOJ 300mil 26(24)L
GLT4160L04E-50J3
50ns
Normal
EDO
Extended
SOJ 300mil 26(24)L
GLT4160L04E-60J3
60ns
Normal
EDO
Extended
SOJ 300mil 26(24)L
GLT4160L04E-70J3
70ns
Normal
EDO
Extended
SOJ 300mil 26(24)L
GLT4160L04S-40J3
40ns
Self Refresh
EDO
Commercial
SOJ 300mil 26(24)L
GLT4160L04S-50J3
50ns
Self Refresh
EDO
Commercial
SOJ 300mil 26(24)L
GLT4160L04S-60J3
60ns
Self Refresh
EDO
Commercial
SOJ 300mil 26(24)L
GLT4160L04S-70J3
70ns
Self Refresh
EDO
Commercial
SOJ 300mil 26(24)L
GLT4160L04SE-40J3
40ns
Self Refresh
EDO
Extended
SOJ 300mil 26(24)L
GLT4160L04SE-50J3
50ns
Self Refresh
EDO
Extended
SOJ 300mil 26(24)L
GLT4160L04SE-60J3
60ns
Self Refresh
EDO
Extended
SOJ 300mil 26(24)L
GLT4160L04SE-70J3
70ns
Self Refresh
EDO
Extended
SOJ 300mil 26(24)L
GLT4160L04-40TC
40ns
Normal
EDO
Commercial
TSOPII 300mil 26(24)L
GLT4160L04-50TC
50ns
Normal
EDO
Commercial
TSOPII 300mil 26(24)L
GLT4160L04-60TC
60ns
Normal
EDO
Commercial
TSOPII 300mil 26(24)L
GLT4160L04-70TC
70ns
Normal
EDO
Commercial
TSOPII 300mil 26(24)L
GLT4160L04E-40TC
40ns
Normal
EDO
Extended
TSOPII 300mil 26(24)L
GLT4160L04E-50TC
50ns
Normal
EDO
Extended
TSOPII 300mil 26(24)L
GLT4160L04E-60TC
60ns
Normal
EDO
Extended
TSOPII 300mil 26(24)L
GLT4160L04E-70TC
70ns
Normal
EDO
Extended
TSOPII 300mil 26(24)L
GLT4160L04S-40TC
40ns
Self Refresh
EDO
Commercial
TSOPII 300mil 26(24)L
GLT4160L04S-50TC
50ns
Self Refresh
EDO
Commercial
TSOPII 300mil 26(24)L
GLT4160L04S-60TC
60ns
Self Refresh
EDO
Commercial
TSOPII 300mil 26(24)L
GLT4160L04S-70TC
70ns
Self Refresh
EDO
Commercial
TSOPII 300mil 26(24)L
GLT4160L04SE-40TC
40ns
Self Refresh
EDO
Extended
TSOPII 300mil 26(24)L
GLT4160L04SE-50TC
50ns
Self Refresh
EDO
Extended
TSOPII 300mil 26(24)L
GLT4160L04SE-60TC
60ns
Self Refresh
EDO
Extended
TSOPII 300mil 26(24)L
GLT4160L04SE-70TC
70ns
Self Refresh
EDO
Extended
TSOPII 300mil 26(24)L
G -LINK
GLT4160L04
4M X 4 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT
May 2001 (Rev.3.1)
G-Link Technology
2701 Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
G-Link Technology Corporation,Taiwan
6F, No. 24-2, Industry E. RD, IV, Science Based
Industrial Park, Hsin Chu, Taiwan.
- 21 -
Parts Numbers (Top Mark) Definition :
GLT 4 160 L 04 S E - 40 J3
4 : DRAM
5 : Synchronous
DRAM
6 : Standard
SRAM
7 : Cache SRAM
8 : Synchronous
Burst SRAM
9 : SGRAM
-SRAM
064 : 8K
256 : 256K
512 : 512K
100 : 1M
-DRAM
10 : 1M(C/EDO)
11 : 1M(C/FPM)
12 : 1M(H/EDO)
13 : 1M(H/FPM)
20 : 2M(EDO)
21 : 2M(FPM)
40 : 4M(EDO)
41 : 4M(FPM)
80 : 8M(EDO)
81 : 8M(FPM)
160 : 16M(EDO)
161 : 16M(FPM)
640 : 64M(EDO)
641 : 64M(FPM)
-SDRAM
40 : 4M
160 : 16M
320 : 32M,4Bank
321 : 32M,2Bank
640 : 64M
VOLTAGE
Blank : 5V
L : 3.3V
M : 2.5V
N : 2.1V
CONFIG.
04 : x04
08 : x08
16 : x16
32 : x32
SPEED
-SRAM
12 : 12ns
15 : 15ns
20 : 20ns
70 : 70ns
-DRAM
25 : 25ns
28 : 28ns
30 : 30ns
35 : 35ns
40 : 40ns
45 : 45ns
50 : 50ns
60 : 60ns
70 : 70ns
80 : 80ns
100 : 100ns
SDRAM :
5 : 5ns/200 MHZ
5.5
: 5.5ns/182 MHZ
6 : 7ns/166 MHZ
7 : 8ns/125 MHZ
10 : 10ns/100 MHZ
PACKAGE
T : PDIP(300mil)
TS : TSOP(Type I)
ST : sTSOP(Type I)
TC : TSOPll (40/44)
TD : TSOPII (44/50)
PL : PLCC
FA : 300mil SOP
FB : 330mil SOP
FC : 445mil SOP
J3 : 300mil SOJ
J4 : 400mil SOJ
P : PDIP(600mil)
Q : PQFP
TQ : TQFP
FG : 48Pin BGA 9x12
FH : 48Pin BGA 8x10
FI : 48Pin BGA 6x8
POWER
Blank : Standard
S : Self Refresh Low Power
L : Low Power
LL : Low Low Power
SL : Super Low Power
Temperature Range
E : Extended Temperature
I : Industrial Temperature
Blank : Commercial Temperature
G -LINK
GLT4160L04
4M X 4 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT
May 2001 (Rev.3.1)
G-Link Technology
2701 Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
G-Link Technology Corporation,Taiwan
6F, No. 24-2, Industry E. RD, IV, Science Based
Industrial Park, Hsin Chu, Taiwan.
- 22 -
Package Information
300mil 24/26 Lead Thin Small Outline Package SOJ
300mil 24/26 Lead Thin Small Outline Package (TSOP) TYPE II