High Speed Pipelined 1-Mbit (32Kx32)
Standard 1T-SRAM
Embedded Memory Macro
M1T1HT18PZ32E
M1T1HT18PZ32E Rev 2.doc
Page 1
2004 MoSys Inc., All Rights Reserved, 1020 Stewart Drive, Sunnyvale, CA 94085
High Performance 1T-SRAM Standard Macro
200 MHz operation
1-Clock cycle time
Pipelined read access timing
Late-late write mode timing
32-Bit wide data buses
Byte Write Enables
Simple standard SRAM interface
Fast delivery
Ultra-Dense Memory
3.8mm
2
size per macro instance
Redundancy & fuses included in macro area
Silicon-Proven 1T-SRAM Technology
Qualification programs completed
Products in volume production
High Yield and Reliability
Built-in redundancy for enhanced yield
Standard Logic Process
TSMC 0.18m CL018G process
Logic design rules
Uses 4 metal layers
Routing over macro possible in layers 5+
Power
Single voltage 1.8V Supply
Low power consumption
General Description
The M1T1HT18PZ32E macro is a 1Mbit (1,084,576 bits), high speed, embedded 1T-SRAM macro. The macro
is organized as 32K(32,768) words of 32 bits. The macro employs a pipelined read timing interface with late
write timing. Write control over individual bytes in the input data is achieved through the use of the byte write
enable (bweb) input signals. The macro is implemented using MoSys 1T -SRAM technology, resulting in
extremely high density and performance.
din[31:0]
dout[31:0]
adr[14:0]
clk
rdb
wrb
rstb
mvdd
mvddcore
mvsscore
mvss
bweb[3:0]
High Speed Pipelined 1-Mbit (32Kx32)
Standard 1T-SRAM
Embedded Memory Macro
M1T1HT18PZ32E
M1T1HT18PZ32E Rev 2.doc
Page 2
2004 MoSys Inc., All Rights Reserved, 1020 Stewart Drive, Sunnyvale, CA 94085
Memory Interface Signal List
Signal Name
Valid
Logic
Direction
Description
adr[14:0]
Positive clk edge
Positive
Input
Memory address
bweb[3:0]
Positive clk edge
Negative
Input
Memory byte write enables
bweb[n] = 0 enables data write
bweb[n] = 1 disables data write
bweb[3] controls writing of din[31:24]
bweb[2] controls writing of din[23:16]
bweb[1] controls writing of din[15:8]
bweb[0] controls writing of din[7:0]
rdb
Positive clk edge
Negative
Input
Memory read
wrb
Positive clk edge
Negative
Input
Memory write
din[31:0]
Positive clk edge
Positive
Input
Memory data in bus
dout[31:0]
Positive clk edge
Positive
Output
Memory data out bus
rstb
Positive clk edge
Negative
Input
Memory initialization reset
clk
Clock
Positive
Input
Memory Clock
mvddcore
Memory core supply voltage
mvsscore
Memory core ground
mvdd
Memory interface supply voltage
mvss
Memory interface ground
Recommended Operating Conditions
Symbol
Parameter
Condition
Min
Max
Units
VDD
Supply Voltage Range (1.8V
10%)
Operating
1.62
1.98
V
TJ
Junction Temperature
Nominal VDD
0
125
C
tCYC
Cycle Time
Operating
5.0
33*
ns
tCKH
Clock High
Operating
0.45*tCYC
0.55*tCYC
ns
tCKL
Clock Low
Operating
0.45*tCYC
0.55*tCYC
ns
Note*: Minimum clock frequency limit adjustable to meet system timing requirements
Power Requirements
Symbol
Condition
Current
per Instance
Units
IDD1
Operating current, V
DD
=1.8V, clock frequency = 200MHz,
output not loaded, memory accessed every clock
0.7
mA/MHz
IDD2
Idle current, V
DD
=1.8V, clock frequency =200MHz, memory
not accessed
0.3
mA/MHz
Input Loading
Symbol
Condition
Load Capacitance
Units
CDIN
din signal input loading
0.2
pF
CADR
adr signal input loading
0.2
pF
CCTL
rdb, wrb, bweb, rstb signal input loading
0.2
pF
CCLK
clk signal input loading
0.5
pF
High Speed Pipelined 1-Mbit (32Kx32)
Standard 1T-SRAM
Embedded Memory Macro
M1T1HT18PZ32E
M1T1HT18PZ32E Rev 2.doc
Page 3
2004 MoSys Inc., All Rights Reserved, 1020 Stewart Drive, Sunnyvale, CA 94085
AC Timing Characteristics at Recommended Operating Conditions
All times in nanoseconds
Bolded numbers reflect the critical timing parameters
Parameter
Description
Condition
Slow
Typical
Fast
tAS
Address Setup
Min.
1.0
0.8
0.6
tAH
Address Hold
Min.
0.5
0.4
0.3
tCS
Control Setup
Min.
1.0
0.8
0.6
tCH
Control Hold
Min.
0.5
0.4
0.3
tDS
Write Data Setup
Min.
1.0
0.8
0.6
tDH
Write Data Hold
Min.
0.5
0.4
0.3
tKQ
Clock to Data Valid
Max.
3.3
2.9
2.5
tKQE
Data valid extrinsic delay per pF
Max.
0.8
0.6
0.4
tKQX
Clock to Data not valid
Min.
0.8
0.6
0.4
clk
adr
bweb
dout
tCYC
tCKL tCKH
A
wrb/rdb
rD
tKQ
tKQX
tAS
tAH
control
tCS
tCH
din
wD
tDH
tDS
.
General AC Timing
High Speed Pipelined 1-Mbit (32Kx32)
Standard 1T-SRAM
Embedded Memory Macro
M1T1HT18PZ32E
M1T1HT18PZ32E Rev 2.doc
Page 4
2004 MoSys Inc., All Rights Reserved, 1020 Stewart Drive, Sunnyvale, CA 94085
Memory macro implements a synchronous reset to force state machines into a known state after power-up.
This reset does not clear the memory contents. The clock must be running for at least two cycles before the
Reset (rstb) signal will be correctly sampled as shown above. The Reset (rstb) signal must be active for at
least ten (10) clock periods to initialize all internal circuitry. Independent of the Reset (rstb) signal, after power
has stabilized to a voltage within the operating specification and the clock is operating within its timing
specifications, there must be at least 128 clock cycles before any read or write access.
clk
rdb or wrb
rstb
>10 clk
>128 clk
Initialization Timing
High Speed Pipelined 1-Mbit (32Kx32)
Standard 1T-SRAM
Embedded Memory Macro
M1T1HT18PZ32E
M1T1HT18PZ32E Rev 2.doc
Page 5
2004 MoSys Inc., All Rights Reserved, 1020 Stewart Drive, Sunnyvale, CA 94085
O
PERATION
T
RUTH
T
ABLE
rdb
wrb
Operation
0
0
Illegal
0
1
Read
1
0
Write
1
1
Nop
F
UNCTIONAL
O
PERATION
Address and command clocked in by rising clock edge. Read data transfers occur in the clock cycle following
the next clock rising edge. Write data transfers occur in the following clock cycle This standard macro uses
user-managed refresh hiding. Review conditions with MoSys to finalize the specification.
S
Single Cycle Read Timing
Single Cycle Write
clk
adr
dout
A
rdb
rD
clk
adr
bweb
din
A
wrb
rW
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