Page 1-33
NetMos
Technology
Nm9820
Single PCI UART
Rev. 1.0
Features
Single 5-V Operation
Low Power
PCI compatible single UART
Pin-to-Pin compatible to Nm9835
16 byte transmit-receive FIFO (UART)
Selectable receive trigger levels
Programmable baud rate generator
Modem control signals
5, 6, 7, 8 Bit characters selection
Even, Odd, No parity, or Force parity generations
Status report capability
Compatible with 16C550
On chip oscillator
Re-map function for legacy ports
Microsoft Compatible
128-pin VQFP package
Applications
Embedded applications
High speed modems
Monitoring equipment
Add on I/O cards
Serial networking
General Description
The Nm9820 is a PCI based single-channel high
performance UART. The Nm9820 offers 16 byte
transmit and receive FIFO compatible with standard
16C550. The Nm9820 perform serial-to-parallel
conversions on data received from a peripheral device,
and parallel-to-serial conversion on data received from
its CPU.
The Nm9820 is ideally suited for PC applications, such
as high-speed COM ports. The Nm9820 is available in
128-Pin QFP package, it is fabricated in an advanced
in submicron CMOS process to achieve low drain power
and high-speed requirements.
Ordering Information
Commercial Grade
Nm9820CV
128-VQFP
0 C to +70 C
Industrial Grade
Nm9820EV
128-VQFP
-40 C to +85 C
Page 1-34
NetMos
Technology
Nm9820
Single PCI UART
Rev. 1.0
128-Pin VQFP Package
Nm98
20CV
N.C.
VC
C
TX
A
nD
TR
A
nR
TSA
GND
RX
A
nD
S
R
A
nC
TSA
n
CDA
nR
I
A
VC
C
EE
-
C
S
EE
-
C
L
K
EE
-
D
O
EE
-
D
I
GND
nI
N
T
A
nR
E
S
ET
CL
K
EE
-
E
N
N.C.
GND
AD
3
1
AD
3
0
AD
2
9
VCC
AD28
AD27
AD26
AD25
AD24
GND
nC/BE3
IDSEL
VCC
AD23
AD22
AD21
AD20
AD19
AD18
AD17
AD16
VCC
GND
GND
nC/BE2
nFRAME
nIRDY
nTRDY
nDEVSEL
nSTOP
nLOCK
nPERR
nSERR
PAR
nC/BE1
GND
AD15
AD14
AD13
AD12
AD11
N.C.
N.C.
XT
AL
1
XT
AL
2
GND
AC
L
K
12XC
L
K
BC
L
K
6XC
L
K
3XC
L
K
VC
C
AD
0
AD
1
AD
2
AD
3
AD
4
AD
5
AD
6
AD
7
GND
GND
nC
/
B
E
0
AD
8
AD
9
AD
1
0
VC
C
N.C.
N.C.
N.C.
GND
N.C.
N.C.
N.C.
N.C.
GND
N.C.
N.C.
N.C.
N.C.
VCC
GND
N.C.
N.C.
N.C.
N.C.
N.C.
VCC
N.C.
N.C.
N.C.
N.C.
GND
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
VCC
N.C.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
Page 1-35
NetMos
Technology
Nm9820
Single PCI UART
Rev. 1.0
Pin Name
128
Type
Description
CLK
122
I
33 MHz PCI system clock input.
nRESET
121
I
PCI System reset (avtice low). Resets all internal register, sequencers, and
signals to a consistent state. During reset condition AD31-0, nSER are three-
stated.
AD31-29 126-128
I/O
Multiplexed PCI address / data bus. A bus transaction consists of an address
phase followed by one or more data phase. During the address phase AD31-
0 contain a physical address. Write data is stable and valid when nIRDY and
nTRDY are asserted (active).
AD28-24
2-6
I/O
See AD31-29 description.
AD23-16
11-18
I/O
See AD31-29 description.
AD15-11
34-38
I/O
See AD31-29 description.
AD10-8
40-42
I/O
See AD31-29 description.
AD7-0
46-53
I/O
See AD31-29 description.
nFRAME
23
I
Frame is driven by the current master to indicate the beginning and duration
of an access. nFRAME is asserted to indicate a bus transaction is beginning.
While nFRAME is active, data transfer continues.
nIRDY
24
I
Initiator Ready. During a write, nIRDY asserted indicates that the initiator is
driving valid data onto the data bus. During a read, nIRDY asserted indicates
that the initiator is ready to accept data from the Nm9820.
nTRDY
25
O
Target Ready (three-state). It is asserted when Nm9820 is ready to complete
the current data phase.
nSTOP
27
O
Nm9820 asserts nSTOP to indicate that it wishes the initiator to stop the
transaction in process on the current data phase.
nLOCK
28
I
Lock indicates an atomic operation that my require multiple transactions to
complete.
IDSEL
9
I
Initialization Device Select. It is used as a chip select during configuration
read and writes transactions.
nDEVSEL
26
O
Device Select (three-state). Nm9820 asserts nDEVSEL when the Nm9820
has decoded its address.
Page 1-36
NetMos
Technology
Nm9820
Single PCI UART
Rev. 1.0
Pin Name
128
Type
Description
nPERR
29
O
Parity Error (three-state). Is used to report parity errors during all PCI
transactions except a Special Cycle. The minimum duration of nPERR is
one clock cycle.
nSERR
30
O
System Error (open drain). This pin goes low when address parity errors are
detected.
PAR
31
I/O
Even Parity. Parity is even parity across AD31-0 and nC/BE3-0. PAR is stable
and valid one clock after the address phase. For data phase PAR is stable
and valid one clock after either nIRDY is asserted on a write transaction or
nTRDY is asserted on a read transaction.
nC/BE3
8
I
Bus Command and Byte Enable. During the address phase of a transaction,
nC/BE3-0 defines the bus command. During data phase nC/BE3-0 are used
as Byte Enables.nC/BE3 applies to byte "3".
nC/BE2
22
I
Bus Command and Byte Enable. During the address phase of a transaction,
nC/BE3-0 defines the bus command. During data phase nC/BE3-0 are used
as Byte Enables. nC/BE2 applies to byte "2".
nC/BE1
32
I
Bus Command and Byte Enable. During the address phase of a transaction,
nC/BE3-0 defines the bus command. During data phase nC/BE3-0 are used
as Byte Enables. nC/BE1 applies to byte "1".
nC/BE0
43
I
Bus Command and Byte Enable. During the address phase of a transaction,
nC/BE3-0 defines the bus command. During data phase nC/BE3-0 are used
as Byte Enables. nC/BE0 applies to byte "0".
nINTA
120
O
PCI active low interrupt output (open-drain). This signal goes low (active)
when an interrupt condition occurs.
EE-CS
115
O
External EE-Prom chip select (active high). After power on reset, Nm9820
reads the EE-Prom and loads the read-only configuration registers
sequentially from the first 64 bytes in the EE-Prom.
EE-CLK
116
O
External EE-Prom clock.
EE-DI
118
I
External EE-Prom data input.
EE-DO
117
O
External EE-Prom data output.
EE-EN
123
I
Enable/Disable external EEprom (active high, internal pull-up). External
EEprom can be disabled when this pin is tied to GND or pulled low. When
external EEprom is disabled, the default values for Nm9820 will be loaded
into PCI configuration register.
Page 1-37
NetMos
Technology
Nm9820
Single PCI UART
Rev. 1.0
Pin Name
128
Type
Description
XTAL1
62
I
Crystal oscillator input or External clock input pin (22.1184 MHz). This signal
input is used in conjunction with XTAL2 to form a feedback circuit for the
internal timing. Two external capacitors (10pF) connected from each side of
the XTAL1 and XTAL2 to GND is required to form a crystal oscillator circuit.
XTAL2
61
O
Crystal oscillator output. See XTAL1 description.
12XCLK
58
O
External clock or crystal oscillator clock divide by 12 output (1.8432 MHz
standard PC UART clock for 115.2k data rate).
6XCLK
56
O
External clock or crystal oscillator clock divide by 6 output (3.6864 MHz PC
UART clock for 230.4k data rate).
3XCLK
55
O
External clock or crystal oscillator clock divide by 3 output (7.3728 MHz UART
clock for 460.8k data rate).
ACLK
59
I
UART-A clock input. ACLK should be connected to external clock source or
one of the 12XCLK, 6XCLK, 3XCLK output pins of the Nm9820.
BCLK
57
I
UART-B clock input. BCLK should be connected to external clock source or
one of the 12XCLK, 6XCLK, 3XCLK output pins of the Nm9820.
TXA
105
O
UART-A Serial data output.
nRTSA
107
O
Active low, UART-A request-to-send signal. It is set to high (in active) after a
hardware reset or during internal loop-back mode. When low, this indicates
that Modem or data set is ready to establish a communication link. nRTSA
has no effect on the transmitter or receiver.
nDTRA
106
O
Active low, UART-A data-terminal-ready signal. It is set to high (in active)
after a hardware reset or during internal loop-back mode. When low, this
output indicates to the Modem or data set that the UART-A is ready to establish
a communication link. nDTRA has no effect on the transmitter or receiver.
RXA
109
I
UART-A, Serial data input.
nCTSA
111
I
Active low, UART-A clear-to-send signal. When low this indicates that Modem
or data set is ready to exchange data. nCTSA has no effect on the transmitter.
nDSRA
110
I
Active low, UART-A data-set-ready signal.
nCDA
112
I
Active low, UART-A Carrier-detect signal. When low this indicates that Modem
or data set has detected the data carrier. nCDA has no effect on the
transmitter.
nRIA
113
I
Active low, UART-A ring-detect signal.
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