NT512D64S8HB1G / NT512D64S8HB1GY / NT512D64S8HB0G
NT256D64S88B1G / NT256D64S88B1GY NT256D64S88B0G
NT128D64SH4B1G / NT512D72S8PB0G (ECC) / NT256D72S89B0G (ECC)
512MB, 256MB and 128MB
PC3200, PC2700 and PC2100
Unbuffered DDR DIMM

REV 2.2

Aug 3, 2004

Preliminary

© NANYA TECHNOLOGY CORPORATION

NANYA reserves the right to change products and specifications without notice.

184 pin Unbuffered DDR DIMM

Based on DDR400/333/266 256M bit B Die device

Features

· 184 Dual In-Line Memory Module (DIMM)

· Unbuffered DDR DIMM based on 256M bit die B device,

organized as either 32Mbx8 or 16Mbx16

· Performance:

PC3200 PC2700 PC2100

Speed Sort

75B

DIMM

CAS

Latency

2.5

Unit

Clock

Frequency

200

166

133 MHz

Clock

Cycle

7.5

DQ Burst Frequency

400

333

266

MHz

· Intended for 133, 166 and 200 MHz applications

· Inputs and outputs are SSTL-2 compatible

· V

= V

DDQ

= 2.5V ±

0.2V (2.6V ± 0.1V for PC3200)

· SDRAMs have 4 internal banks for concurrent operation

· Differential clock inputs

· Data is read or written on both clock edges

· DRAM DLL aligns DQ and DQS transitions with clock transitions

· Address and control signals are fully synchronous to positive

clock edge

· Programmable Operation:

- DIMM

CAS

Latency: 2, 2.5, 3

- Burst Type: Sequential or Interleave

- Burst Length: 2, 4, 8

- Operation: Burst Read and Write

· Auto Refresh (CBR) and Self Refresh Modes

· Automatic and controlled precharge commands

· 7.8

s Max. Average Periodic Refresh Interval

· Serial Presence Detect EEPROM

· Gold contacts

· SDRAMs are packaged in TSOP packages

· "Green" packaging lead free

Description

NT512D64S8HB0G, NT512D64S8HB1G, NT512D64S8HB1GY, NT512D72S8PB0G, NT256D64SH88B0G, NT256D64SH88B1G,

NT256D64SH88B1GY, NT256D72S89B0G and NT128D64SH4B1G are unbuffered 184-Pin Double Data Rate (DDR) Synchronous DRAM

Dual In-Line Memory Modules (DIMM). NT512D64S8HB1GY and NT256D64SH88B1GY are packaged using lead free technology.

NT512D64S8HB0G, NT512D64S8HB1G and NT512D64S8HB1GY are 512MB modules organized as dual ranks using sixteen 32Mx8

TSOP devices. NT512D72S8PB0G has ECC and is organized as dual ranks using eighteen 32Mx8 TSOP devices. NT256D64SH88B0G,

NT256D64SH88B1G and NT256D64SH88B1GY are 256MB modules organized as single rank using eight 32Mx8 TSOP devices.

NT256D72S89B0G has ECC and is organized as single rank using nine 32Mx8 TSOP devices. NT128D64SH4B1G are 128MB modules,

organized as single rank using four 16Mx16 TSOP devices.

Depending on the speed grade, these DIMMs are intended for use in applications operating up to 200 MHz clock speeds and achieves

high-speed data transfer rates of up to 400 MHz. Prior to any access operation, the device

CAS

latency and burst type/ length/operation

type must be programmed into the DIMM by address inputs and I/O inputs BA0 and BA1 using the mode register set cycle.

The DIMM uses a serial EEPROM and through the use of a standard IIC protocol the serial presence-detect implementation (SPD) can be

accessed. The first 128 bytes of the SPD data are programmed with the module characteristics as defined by JEDEC.

NT512D64S8HB1G / NT512D64S8HB1GY / NT512D64S8HB0G
NT256D64S88B1G / NT256D64S88B1GY NT256D64S88B0G
NT128D64SH4B1G / NT512D72S8PB0G (ECC) / NT256D72S89B0G (ECC)
Unbuffered DDR DIMM

REV 2.2

Aug 3, 2004

Preliminary

© NANYA TECHNOLOGY CORPORATION

NANYA reserves the right to change products and specifications without notice.

Ordering Information

Part Number

Organization

Speed Power

Leads

NT512D72S8PB0G-5T

64Mx72

NT512D64S8HB1G-5T

NT512D64S8HB1GY-5T

(lead free)

64Mx64

NT256D72S890G-5T

32Mx72

NT256D64S88B1G-5T

NT256D64S88B1GY-5T

(lead free)

32Mx64

NT128D64SH4B1G-5T

16Mx64

DDR400

PC3200

3-3-3

200MHz (5ns @ CL = 3)

166MHz (6ns @ CL = 2.5)

2.6V

NT512D64S8HB1G-6K

NT512D64S8HB1GY-6K

(lead free)

64Mx64

NT256D64S88B1GY-6K

(lead free)

NT256D64S88B0G-6K

32Mx64

NT128D64SH4B1G-6K

16Mx64

DDR333

PC2700

2.5-3-3

166MHz (6ns @ CL = 2.5)

133MHz (7.5ns @ CL = 2)

NT512D64S8HB0G-75B

64Mx64

NT256D64S88B0G-75B

32Mx64

NT128D64SH4B1G-75B

16Mx64

DDR266B

PC2100

2.5-3-3

133MHz (7.5ns @ CL = 2.5)

100MHz (10ns @ CL = 2)

2.5V

Gold

For the closest sales office or information, please visit:

www.nanya.com

Nanya Technology Corporation

Hwa Ya Technology Park 669

Fu Hsing 3rd Rd., Kueishan,

Taoyuan, 333, Taiwan, R.O.C.

Tel: +886-3-328-1688

NT512D64S8HB1G / NT512D64S8HB1GY / NT512D64S8HB0G
NT256D64S88B1G / NT256D64S88B1GY NT256D64S88B0G
NT128D64SH4B1G / NT512D72S8PB0G (ECC) / NT256D72S89B0G (ECC)
Unbuffered DDR DIMM

REV 2.2

Aug 3, 2004

Preliminary

© NANYA TECHNOLOGY CORPORATION

NANYA reserves the right to change products and specifications without notice.

Pin Description

CK0, CK1, CK2,

CK0

CK1

CK2

Differential Clock Inputs.

DQ0-DQ63

Data input/output

CKE0, CKE1

Clock Enable

DQS0-DQS7

Bidirectional data strobes

RAS

Row

Address

Strobe

DM0-DM7

Input Data Mask

CAS

Column

Address

Strobe V

Power

Write Enable

DDQ

Supply voltage for DQs

Chip

Selects

Ground

A0-A9, A11, A12

Address Inputs

No Connect

A10/AP Address

Input/Auto-precharge

SCL Serial Presence Detect Clock Input

BA0, BA1

SDRAM Bank Address Inputs

SDA

Serial Presence Detect Data input/output

REF

Ref. Voltage for SSTL_2 inputs

SA0-2

Serial Presence Detect Address Inputs

DDID

Identification flag.

DDSPD

Serial EEPROM positive power supply

Pinout

Pin Front

Pin Back

Pin Front

Pin Back

Pin Front

Pin Back

1 V

REF

A5 124

DDQ

154

RAS

2 DQ0

94 DQ4

33 DQ24

125

155 DQ45

3 V

DQ5

126

DQ28

DQ41

156

DDQ

4 DQ1

96 V

DDQ

DQ25

127

DQ29

CAS

157

5 DQS0

97 DM0/DQS9 36 DQS3

128

DDQ

158

6 DQ2

98 DQ6

37 A4

129

DM3/DQS12 67 DQS5

159

DM5/DQS14

7 V

DQ7 38

130

A3 68

DQ42

160

8 DQ3

100

DQ26

131

DQ30

DQ43

161

DQ46

9 NC

101

40 DQ27

132

162

DQ47

10 NC

102 NC

41 A2

133 DQ31

71 NC

163 NC

11 V

103

NC 42

134

NC 72

DQ48

164

DDQ

12 DQ8

104 V

DDQ

A1 135

NC 73

DQ49

165

DQ52

13 DQ9

105 DQ12

44 NC

136 V

DDQ

166

DQ53

14 DQS1

106 DQ13

45 NC

137 CK0

CK2

167 NC

15 V

DDQ

107

DM1/DQS10

138

CK0

76 CK2

168 V

16 CK1

108 V

NC 139

DDQ

169

DM6/DQS15

CK1

109 DQ14

48 A0

140 NC

78 DQS6

170 DQ54

18 V

110

DQ15

NC 141

A10 79

DQ50

171

DQ55

19 DQ10

111 CKE1

50 V

142

NC 80

DQ51

172

DDQ

20 DQ11

112 V

DDQ

NC 143

DDQ

173

21 CKE0

113 NC

52 BA1

144 NC

82 V

DDID

174

DQ60

22 V

DDQ

114

DQ20

KEY

DQ56

175

DQ61

23 DQ16

115 A12

53 DQ32

145 V

DQ57

176

24 DQ17

116 V

DDQ

146

DQ36 85

177

DM7/DQS16

25 DQS2

117 DQ21

55 DQ33

147 DQ37

86 DQS7

178 DQ62

26 V

118

A11 56

DQS4

148

DQ58

179

DQ63

27 A9

119 DM2/DQS11 57 DQ34

149 DM4/DQS13 88 DQ59

180 V

DDQ

28 DQ18

120 V

58 V

150

DQ38

181

SA0

29 A7

121 DQ22

59 BA0

151 DQ39

90 WP

182 SA1

30 V

DDQ

122

DQ35

152

SDA

183

SA2

31 DQ19

123 DQ23

61 DQ40

153 DQ44

92 SCL

184 V

DDSPD

Note: All pin assignments are consistent for all 8-byte unbuffered versions.

NT512D64S8HB1G / NT512D64S8HB1GY / NT512D64S8HB0G
NT256D64S88B1G / NT256D64S88B1GY NT256D64S88B0G
NT128D64SH4B1G / NT512D72S8PB0G (ECC) / NT256D72S89B0G (ECC)
Unbuffered DDR DIMM

REV 2.2

Aug 3, 2004

Preliminary

© NANYA TECHNOLOGY CORPORATION

NANYA reserves the right to change products and specifications without notice.

Input/Output Functional Description

Symbol

Type

Polarity

Function

CK0, CK1, CK2,

CK0

CK1

CK2

(SSTL)

Cross

point

The system clock inputs. All address and command lines are sampled on the cross point of
the rising edge of CK and falling edge of CK. A Delay Locked Loop (DLL) circuit is driven
from the clock inputs and output timing for read operations is synchronized to the input
clock.

CKE0, CKE1

(SSTL)

Active

High

Activates the DDR SDRAM CK signal when high and deactivates the CK signal when low.

By deactivating the clocks, CKE low initiates the Power Down mode or the Self Refresh

mode.

(SSTL)

Active

Low

Enables the associated DDR SDRAM command decoder when low and disables the

command decoder when high. When the command decoder is disabled, new commands are

ignored but previous operations continue. Physical Bank 0 is selected by S0; Bank 1 is

selected by S1.

RAS

CAS

(SSTL)

Active

Low

When sampled at the positive rising edge of the clock,

RAS

CAS

define the operation to

be executed by the SDRAM.

REF

Supply

Reference voltage for SSTL-2 inputs

DDQ

Supply

Isolated power supply for the DDR SDRAM output buffers to provide improved noise

immunity

BA0, BA1

(SSTL) -

Selects which SDRAM bank is to be active.

A0 - A9

A10/AP

A11, A12

(SSTL) -

During a Bank Activate command cycle, A0-A12 defines the row address (RA0-RA12) when

sampled at the rising clock edge.

During a Read or Write command cycle, A0-A9 defines the column address (CA0-CA9)

when sampled at the rising clock edge. In addition to the column address, AP is used to

invoke auto-precharge operation at the end of the Burst Read or Write cycle. If AP is high,

auto-precharge is selected and BA0/BA1 defines the bank to be precharged. If AP is low,

auto-precharge is disabled.

During a Precharge command cycle, AP is used in conjunction with BA0/BA1 to control

which bank(s) to precharge. If AP is high all 4 banks will be precharged regardless of the

state of BA0/BA1. If AP is low, then BA0/BA1 are used to define which bank to pre-charge.

DQ0 - DQ63

(SSTL) -

Data and Check Bit input/output pins operate in the same manner as on conventional

DRAMs.

DQS0 - DQS7,

DQS9 DQS16

(SSTL)

Active

High

Data strobes: Output with read data, input with write data. Edge aligned with read data,

centered on write data. Used to capture write data.

CB0 CB7

(SSTL)

Data Check Bit Input/Output pins. Used on ECC modules and is not used on x64 modules.

DM0 DM8

Input

Active

High

The data write masks, associated with one data byte. In Write mode, DM operates as a byte
mask by allowing input data to be written if it is low but blocks the write operation if it is high.
In Read mode, DM lines have no effect. DM8 is associated with check bits CB0-CB7, and is
not used on x64 modules.

, V

Supply

Power and ground for the DDR SDRAM input buffers and core logic

SA0 SA2

Address inputs. Connected to either V

or V

on the system board to configure the Serial

Presence Detect EEPROM address.

SDA

This bi-directional pin is used to transfer data into or out of the SPD EEPROM. A resistor

must be connected from the SDA bus line to V DD to act as a pull-up.

SCL

This signal is used to clock data into and out of the SPD EEPROM. A resistor may be

connected from the SCL bus time to V DD to act as a pull-up.

DDSPD

Supply

Serial EEPROM positive power supply.

NT512D64S8HB1G / NT512D64S8HB1GY / NT512D64S8HB0G
NT256D64S88B1G / NT256D64S88B1GY NT256D64S88B0G
NT128D64SH4B1G / NT512D72S8PB0G (ECC) / NT256D72S89B0G (ECC)
Unbuffered DDR DIMM

REV 2.2

Aug 3, 2004

Preliminary

© NANYA TECHNOLOGY CORPORATION

NANYA reserves the right to change products and specifications without notice.

Functional Block Diagram

2 Ranks, 16 devices, 32Mx8 DDR SDRAMs

Serial PD

SCL

SDA

SA0

SA2

SA1

A0-A13

RAS

BA0-BA1

BA0-BA1 : SDRAMs D0-D15

A0-A13 : SDRAMs D0-D15

RAS

: SDRAMs D0-D15

CKE0

CAS

: SDRAMs D0-D15

CKE : SDRAMs D0-D7

CKE : SDRAMs D8-D15

: SDRAMs D0-D15

CKE1

DDSPD

REF

DDID

DDQ

Strap: see Note 4

SPD

D0-D15

* Wire per Clock Loading Table/

Wiring Diagrams

* Clock Wiring

Clock Input

SDRAMs

*CK0/

CK0

*CK1/

CK1

*CK2/

CK2

4 SDRAMs
6 SDRAMs
6 SDRAMs

Notes :

1. DQ-to-I/O wiring is shown as recommended but may be changed.

2. DQ/DQS/DM/CKE/S relationships must be maintained as shown.

3. DQ, DQS, DM/DQS resistors: 22 Ohms.

4. V

DDID

strap connections (for memory device V

, V

DDQ

STRAP OUT (OPEN): V

= V

DDQ

STRAP IN (V

): V

is not equal to V

DDQ

DM0/DQS9

DQ0

DQ1

DQ2

DQ7

DQ4

DQ6

DQ5

DQ3

DQ8

DQ9

DQ10

DQ15

DQ12

DQ14

DQ13

DQ11

DQ16

DQ17

DQ18

DQ23

DQ20

DQ22

DQ21

DQ19

DQ24

DQ25

DQ26

DQ31

DQ28

DQ30

DQ29

DQ27

I/O 7
I/O 6

I/O 3

I/O 4

I/O 5

I/O 0

I/O 1

I/O 2

I/O 7
I/O 6

I/O 3

I/O 4

I/O 5

I/O 0

I/O 1

I/O 2

DQS0

DM4/DQS13

DQS4

I/O 7
I/O 6

I/O 3

I/O 4

I/O 5

I/O 0

I/O 1

I/O 2

DM1/DQS10

DQS1

DQS

DM2/DQS11

DQS2

DM3/DQS12

DQS3

DQS

DQ32

DQ33

DQ34

DQ39

DQ36

DQ38

DQ37

DQ35

DQ40

DQ41

DQ42

DQ47

DQ44

DQ46

DQ45

DQ43

I/O 7
I/O 6

I/O 3

I/O 4

I/O 5

I/O 0

I/O 1

I/O 2

DQS

DQS5

DM5/DQS14

DQ48

DQ49

DQ50

DQ55

DQ52

DQ54

DQ53

DQ51

DQ56

DQ57

DQ58

DQ63

DQ60

DQ62

DQ61

DQ59

DQS6

DM6/DQS15

DQS7

DM7/DQS16

DQS

I/O 0
I/O 1

I/O 4

I/O 3

I/O 2

I/O 7

I/O 6

I/O 5

DQS

I/O 0
I/O 1

I/O 4

I/O 3

I/O 2

I/O 7

I/O 6

I/O 5

DQS

I/O 0
I/O 1

I/O 4

I/O 3

I/O 2

I/O 7

I/O 6

I/O 5

D10

DQS

I/O 0
I/O 1

I/O 4

I/O 3

I/O 2

I/O 7

I/O 6

I/O 5

D11

DQS

I/O 7
I/O 6

I/O 3

I/O 4

I/O 5

I/O 0

I/O 1

I/O 2

I/O 7
I/O 6

I/O 3

I/O 4

I/O 5

I/O 0

I/O 1

I/O 2

I/O 7
I/O 6

I/O 3

I/O 4

I/O 5

I/O 0

I/O 1

I/O 2

DQS

I/O 7
I/O 6

I/O 3

I/O 4

I/O 5

I/O 0

I/O 1

I/O 2

DQS

I/O 0
I/O 1

I/O 4

I/O 3

I/O 2

I/O 7

I/O 6

I/O 5

D12

DQS

I/O 0
I/O 1

I/O 4

I/O 3

I/O 2

I/O 7

I/O 6

I/O 5

D13

DQS

I/O 0
I/O 1

I/O 4

I/O 3

I/O 2

I/O 7

I/O 6

I/O 5

D14

DQS

I/O 0
I/O 1

I/O 4

I/O 3

I/O 2

I/O 7

I/O 6

I/O 5

D15

DQS

NT512D64S8HB1G / NT512D64S8HB1GY / NT512D64S8HB0G
NT256D64S88B1G / NT256D64S88B1GY NT256D64S88B0G
NT128D64SH4B1G / NT512D72S8PB0G (ECC) / NT256D72S89B0G (ECC)
Unbuffered DDR DIMM

REV 2.2

Aug 3, 2004

Preliminary

© NANYA TECHNOLOGY CORPORATION

NANYA reserves the right to change products and specifications without notice.

Functional Block Diagram

1 Rank, 8 devices, 32Mx8 DDR SDRAMs

Serial PD

SCL

SDA

SA0

SA2

SA1

A0-A13

RAS

BA0-BA1

BA0-BA1 : SDRAMs D0-D7

A0-A13 : SDRAMs D0-D7

RAS

: SDRAMs D0-D7

CKE0

CAS

: SDRAMs D0-D7

CKE : SDRAMs D0-D7

: SDRAMs D0-D7

DDSPD

REF

DDID

DDQ

Strap: see Note 4

SPD

D0-D7

* Wire per Clock Loading Table/

Wiring Diagrams

* Clock Wiring

Clock Input

SDRAMs

*CK0/

CK0

*CK1/

CK1

*CK2/

CK2

2 SDRAMs
3 SDRAMs
3 SDRAMs

Notes :

1. DQ-to-I/O wiring is shown as recommended but may be changed.
2. DQ/DQS/DM/CKE/S relationships must be maintained as shown.
3. DQ, DQS, DM/DQS resistors: 22 Ohms.
4. V

DDID

strap connections (for memory device V

, V

DDQ

STRAP OUT (OPEN): V

= V

DDQ

STRAP IN (V

): V

is not equal to V

DDQ

DM0/DQS9

DQ0

DQ1

DQ2

DQ7

DQ4

DQ6

DQ5

DQ3

DQ8

DQ9

DQ10

DQ15

DQ12

DQ14

DQ13

DQ11

DQ16

DQ17

DQ18

DQ23

DQ20

DQ22

DQ21

DQ19

DQ24

DQ25

DQ26

DQ31

DQ28

DQ30

DQ29

DQ27

I/O 7
I/O 6

I/O 3

I/O 4

I/O 5

I/O 0

I/O 1

I/O 2

I/O 7
I/O 6

I/O 3

I/O 4

I/O 5

I/O 0

I/O 1

I/O 2

I/O 7
I/O 6

I/O 3

I/O 4

I/O 5

I/O 0

I/O 1

I/O 2

DQS0

DM4/DQS13

DQS4

DQS

I/O 7
I/O 6

I/O 3

I/O 4

I/O 5

I/O 0

I/O 1

I/O 2

DQS

DM1/DQS10

DQS1

DQS

DM2/DQS11

DQS2

DM3/DQS12

DQS3

DQS

DQ32

DQ33

DQ34

DQ39

DQ36

DQ38

DQ37

DQ35

DQ40

DQ41

DQ42

DQ47

DQ44

DQ46

DQ45

DQ43

I/O 7
I/O 6

I/O 3

I/O 4

I/O 5

I/O 0

I/O 1

I/O 2

DQS

I/O 7
I/O 6

I/O 3

I/O 4

I/O 5

I/O 0

I/O 1

I/O 2

DQS

DQS5

DM5/DQS14

DQ48

DQ49

DQ50

DQ55

DQ52

DQ54

DQ53

DQ51

I/O 7
I/O 6

I/O 3

I/O 4

I/O 5

I/O 0

I/O 1

I/O 2

DQS

DQ56

DQ57

DQ58

DQ63

DQ60

DQ62

DQ61

DQ59

I/O 7
I/O 6

I/O 3

I/O 4

I/O 5

I/O 0

I/O 1

I/O 2

DQS

DQS6

DM6/DQS15

DQS7

DM7/DQS16

NT512D64S8HB1G / NT512D64S8HB1GY / NT512D64S8HB0G
NT256D64S88B1G / NT256D64S88B1GY NT256D64S88B0G
NT128D64SH4B1G / NT512D72S8PB0G (ECC) / NT256D72S89B0G (ECC)
Unbuffered DDR DIMM

REV 2.2

Aug 3, 2004

Preliminary

© NANYA TECHNOLOGY CORPORATION

NANYA reserves the right to change products and specifications without notice.

Functional Block Diagram

1 Rank, 4 devices, 16Mx16 DDR SDRAMs

Serial PD

SCL

SDA

SA0

SA2

SA1

A0-A13

RAS

BA0-BA1

BA0-BA1 : SDRAMs D0-D3

A0-A13 : SDRAMs D0-D3

RAS

: SDRAMs D0-D3

CKE0

CAS

: SDRAMs D0-D3

CKE : SDRAMs D0-D3

: SDRAMs D0-D3

DDSPD

REF

DDID

DDQ

Strap: see Note 4

SPD

D0-D3

* Wire per Clock Loading Table/

Wiring Diagrams

* Clock Wiring

Clock Input

SDRAMs

*CK0/

CK0

*CK1/

CK1

*CK2/

CK2

NC
2 SDRAMs
2 SDRAMs

DM1/DQS10

DQ8

DQ9

DQ10

DQ15

DQ12

DQ14

DQ13

DQ11

DQ0

DQ1

DQ2

DQ7

DQ4

DQ6

DQ5

DQ3

DQ24

DQ25

DQ26

DQ31

DQ28

DQ30

DQ29

DQ27

DQ16

DQ17

DQ18

DQ23

DQ20

DQ22

DQ21

DQ19

DQS1

DM5/DQS14

DQS5

DM0/DQS9

DQS0

DM3/DQS12

DQS3

DM2/DQS11

DQS2

DQ40

DQ41

DQ42

DQ47

DQ44

DQ46

DQ45

DQ43

DQ32

DQ33

DQ34

DQ39

DQ36

DQ38

DQ37

DQ35

DQS4

DM4/DQS13

DQ56

DQ57

DQ58

DQ63

DQ60

DQ62

DQ61

DQ59

DQ48

DQ49

DQ50

DQ55

DQ52

DQ54

DQ53

DQ51

DQS7

DM7/DQS16

DQS6

DM6/DQS15

I/O 6
I/O 4

I/O 5

I/O 0

I/O 2

I/O 3

I/O 1

I/O 7

LDM

I/O 8

I/O 10

I/O 11

I/O 14

I/O 12

I/O 13

I/O 15

I/O 9

UDM

UDQS

LDQS

I/O 6
I/O 4

I/O 5

I/O 0

I/O 2

I/O 3

I/O 1

I/O 7

LDM

I/O 8

I/O 10

I/O 11

I/O 14

I/O 12

I/O 13

I/O 15

I/O 9

UDM

UDQS

LDQS

I/O 6
I/O 4

I/O 5

I/O 0

I/O 2

I/O 3

I/O 1

I/O 7

LDM

I/O 8

I/O 10

I/O 11

I/O 14

I/O 12

I/O 13

I/O 15

I/O 9

UDM

UDQS

LDQS

I/O 6
I/O 4

I/O 5

I/O 0

I/O 2

I/O 3

I/O 1

I/O 7

LDM

I/O 8

I/O 10

I/O 11

I/O 14

I/O 12

I/O 13

I/O 15

I/O 9

UDM

UDQS

LDQS

Notes :

1. DQ-to-I/O wiring is shown as recommended but may be changed.
2. DQ/DQS/DM/CKE/S relationships must be maintained as shown.
3. DQ, DQS, DM/DQS resistors: 22 Ohms.
4. V

DDID

strap connections (for memory device V

, V

DDQ

STRAP OUT (OPEN): V

= V

DDQ

STRAP IN (V

): V

is not equal to V

DDQ

NT512D64S8HB1G / NT512D64S8HB1GY / NT512D64S8HB0G
NT256D64S88B1G / NT256D64S88B1GY NT256D64S88B0G
NT128D64SH4B1G / NT512D72S8PB0G (ECC) / NT256D72S89B0G (ECC)
Unbuffered DDR DIMM

REV 2.2

Aug 3, 2004

Preliminary

© NANYA TECHNOLOGY CORPORATION

NANYA reserves the right to change products and specifications without notice.

Functional Block Diagram

2 Ranks, 18 devices (ECC), 32Mx8 DDR SDRAMs

Serial PD

SCL

SDA

SA0

SA2

SA1

3. DQ/DQS/DM/DQS resistors are 22 Ohms.

Notes :

1. DQ-to-I/O wring may be changed within a byte.

2. DQ/DQS/DM/CKE/S relationships are maintained as shown.

4. V

DDID

strap connections (for memory device V

, V

DDQ

STRAP OUT (OPEN): V

= V

DDQ

STRAP IN (V

): V

is not equal to V

DDQ

DDSPD

REF

DDID

DDQ

Strap: see Note 4

SPD

D0-D8

A0-A13

RAS

BA0-BA1

BA0-BA1 : SDRAMs D0-D17

A0-A13 : SDRAMs D0-D17

RAS

: SDRAMs D0-D17

CKE0

CAS

: SDRAMs D0-D17

CKE : SDRAMs D0-D8

CKE : SDRAMs D9-D17

: SDRAMs D0-D17

CKE1

* Wire per Clock Loading Table/

Wiring Diagrams

* Clock Wiring

Clock Input

SDRAMs

*CK0/

CK0

*CK1/

CK1

*CK2/

CK2

6 SDRAMs
6 SDRAMs
6 SDRAMs

DM0/DQS9

DQ0

DQ1

DQ2

DQ7

DQ4

DQ6

DQ5

DQ3

DQ8

DQ9

DQ10

DQ15

DQ12

DQ14

DQ13

DQ11

DQ16

DQ17

DQ18

DQ23

DQ20

DQ22

DQ21

DQ19

DQ24

DQ25

DQ26

DQ31

DQ28

DQ30

DQ29

DQ27

DQS0

DM4/DQS13

DQS4

DM1/DQS10

DQS1

DM2/DQS11

DQS2

DM3/DQS12

DQS3

DQ32

DQ33

DQ34

DQ39

DQ36

DQ38

DQ37

DQ35

DQ40

DQ41

DQ42

DQ47

DQ44

DQ46

DQ45

DQ43

DQS5

DM5/DQS14

DQ48

DQ49

DQ50

DQ55

DQ52

DQ54

DQ53

DQ51

DQ56

DQ57

DQ58

DQ63

DQ60

DQ62

DQ61

DQ59

DQS6

DM6/DQS15

DQS7

DM7/DQS16

CB0

CB1

CB2

CB7

CB4

CB6

CB5

CB3

DM8/DQS17

DQS8

I/O 7
I/O 6

I/O 3

I/O 4

I/O 5

I/O 0

I/O 1

I/O 2

DQS

I/O 0
I/O 1

I/O 4

I/O 3

I/O 2

I/O 7

I/O 6

I/O 5

DQS

I/O 7
I/O 6

I/O 3

I/O 4

I/O 5

I/O 0

I/O 1

I/O 2

DQS

I/O 0
I/O 1

I/O 4

I/O 3

I/O 2

I/O 7

I/O 6

I/O 5

D10

DQS

I/O 7
I/O 6

I/O 3

I/O 4

I/O 5

I/O 0

I/O 1

I/O 2

DQS

I/O 0
I/O 1

I/O 4

I/O 3

I/O 2

I/O 7

I/O 6

I/O 5

D11

DQS

I/O 7
I/O 6

I/O 3

I/O 4

I/O 5

I/O 0

I/O 1

I/O 2

DQS

I/O 0
I/O 1

I/O 4

I/O 3

I/O 2

I/O 7

I/O 6

I/O 5

D12

DQS

I/O 7
I/O 6

I/O 3

I/O 4

I/O 5

I/O 0

I/O 1

I/O 2

DQS

I/O 0
I/O 1

I/O 4

I/O 3

I/O 2

I/O 7

I/O 6

I/O 5

D17

DQS

I/O 7
I/O 6

I/O 3

I/O 4

I/O 5

I/O 0

I/O 1

I/O 2

DQS

I/O 0
I/O 1

I/O 4

I/O 3

I/O 2

I/O 7

I/O 6

I/O 5

D13

DQS

I/O 7
I/O 6

I/O 3

I/O 4

I/O 5

I/O 0

I/O 1

I/O 2

DQS

I/O 0
I/O 1

I/O 4

I/O 3

I/O 2

I/O 7

I/O 6

I/O 5

D14

DQS

I/O 7
I/O 6

I/O 3

I/O 4

I/O 5

I/O 0

I/O 1

I/O 2

DQS

I/O 0
I/O 1

I/O 4

I/O 3

I/O 2

I/O 7

I/O 6

I/O 5

D15

DQS

I/O 7
I/O 6

I/O 3

I/O 4

I/O 5

I/O 0

I/O 1

I/O 2

DQS

I/O 0
I/O 1

I/O 4

I/O 3

I/O 2

I/O 7

I/O 6

I/O 5

D16

DQS

NT512D64S8HB1G / NT512D64S8HB1GY / NT512D64S8HB0G
NT256D64S88B1G / NT256D64S88B1GY NT256D64S88B0G
NT128D64SH4B1G / NT512D72S8PB0G (ECC) / NT256D72S89B0G (ECC)
Unbuffered DDR DIMM

REV 2.2

Aug 3, 2004

Preliminary

© NANYA TECHNOLOGY CORPORATION

NANYA reserves the right to change products and specifications without notice.

Functional Block Diagram

1 Rank, 9 devices (ECC), 32Mx8 DDR SDRAMs

DM0/DQS9

DQ0

DQ1

DQ2

DQ7

DQ4

DQ6

DQ5

DQ3

DQ8

DQ9

DQ10

DQ15

DQ12

DQ14

DQ13

DQ11

DQS0

DM4/DQS13

DQS4

DM1/DQS10

DQS1

DM2/DQS11

DQS2

DM3/DQS12

DQS3

DQ32

DQ33

DQ34

DQ39

DQ36

DQ38

DQ37

DQ35

DQS5

DM5/DQS14

DQS6

DM6/DQS15

DQS7

DM7/DQS16

DQ16

DQ17

DQ18

DQ23

DQ20

DQ22

DQ21

DQ19

DQ24

DQ25

DQ26

DQ31

DQ28

DQ30

DQ29

DQ27

DQ40

DQ41

DQ42

DQ47

DQ44

DQ46

DQ45

DQ43

DQ48

DQ49

DQ50

DQ55

DQ52

DQ54

DQ53

DQ51

DQ56

DQ57

DQ58

DQ63

DQ60

DQ62

DQ61

DQ59

Serial PD

SCL

SDA

SA0

SA2

SA1

Notes :

1. DQ-to-I/O wring may be changed within a byte.
2. DQ/DQS/DM/CKE/S relationships are maintained as shown.
3. DQ/DQS/DM/DQS resistors are 22 Ohms.

4. V

DDID

strap connections (for memory device V

, V

DDQ

STRAP OUT (OPEN): V

= V

DDQ

STRAP IN (V

): V

is not equal to V

DDQ

CB0

CB1

CB2

CB7

CB4

CB6

CB5

CB3

DM8/DQS17

DQS8

DDSPD

REF

DDID

DDQ

Strap: see Note 4

SPD

D0-D8

A0-A13

RAS

BA0-BA1

BA0-BA1 : SDRAMs D0-D8

A0-A13 : SDRAMs D0-D8

RAS

: SDRAMs D0-D8

CKE0

CAS

: SDRAMs D0-D8

CKE : SDRAMs D0-D8

: SDRAMs D0-D8

I/O 7
I/O 6

I/O 3

I/O 4

I/O 5

I/O 0

I/O 1

I/O 2

DQS

I/O 7
I/O 6

I/O 3

I/O 4

I/O 5

I/O 0

I/O 1

I/O 2

DQS

I/O 7
I/O 6

I/O 3

I/O 4

I/O 5

I/O 0

I/O 1

I/O 2

DQS

I/O 7
I/O 6

I/O 3

I/O 4

I/O 5

I/O 0

I/O 1

I/O 2

DQS

I/O 7
I/O 6

I/O 3

I/O 4

I/O 5

I/O 0

I/O 1

I/O 2

DQS

I/O 7
I/O 6

I/O 3

I/O 4

I/O 5

I/O 0

I/O 1

I/O 2

DQS

I/O 7
I/O 6

I/O 3

I/O 4

I/O 5

I/O 0

I/O 1

I/O 2

DQS

I/O 7
I/O 6

I/O 3

I/O 4

I/O 5

I/O 0

I/O 1

I/O 2

DQS

I/O 7
I/O 6

I/O 3

I/O 4

I/O 5

I/O 0

I/O 1

I/O 2

DQS

* Wire per Clock Loading Table/

Wiring Diagrams

* Clock Wiring

Clock Input

SDRAMs

*CK0/

CK0

*CK1/

CK1

*CK2/

CK2

3 SDRAMs
3 SDRAMs
3 SDRAMs

NT512D64S8HB1G / NT512D64S8HB1GY / NT512D64S8HB0G
NT256D64S88B1G / NT256D64S88B1GY NT256D64S88B0G
NT128D64SH4B1G / NT512D72S8PB0G (ECC) / NT256D72S89B0G (ECC)
Unbuffered DDR DIMM

REV 2.2

Aug 3, 2004

Preliminary

© NANYA TECHNOLOGY CORPORATION

NANYA reserves the right to change products and specifications without notice.

Serial Presence Detect

SPD Description

Byte Description

Number of Serial PD Bytes Written during Production

Maximum Data Access Time from Clock at CL=1

Total Number of Bytes in Serial PD device

Minimum Row Precharge Time (t

)

Fundamental Memory Type

Minimum Row Active to Row Active delay (t

RRD

)

Number of Row Addresses on Assembly

Minimum RAS to CAS delay (t

RCD

)

Number of Column Addresses on Assembly

Minimum RAS Pulse Width (t

RAS

)

Number of DIMM Rank

Module Bank Density

Data Width of Assembly

Address and Command Setup Time Before Clock

Data Width of Assembly (cont')

Address and Command Hold Time After Clock

Voltage Interface Level of this Assembly

Data Input Setup Time Before Clock

DDR SDRAM Device Cycle Time

CL=2.5

Data Input Hold Time After Clock

DDR SDRAM Device Access Time from Clock

CL=2.5

36-40 Reserved

DIMM Configuration Type

Minimum Active/Auto-refresh Time (t

)

12 Refresh

Rate/Type

Auto-refresh to Active/Auto-refresh Command Period

RFC

)

Primary DDR SDRAM Width

Max Cycle Time (t

CK max

)

Error Checking DDR SDRAM Device Width

Maximum DQS-DQ Skew Time (t

DQSQ

)

DDR SDRAM Device Attr: Min CLK Delay, Random Col

Access

Maximum Read Data Hold Skew Factor (t

QHS

)

DDR SDRAM Device Attributes: Burst Length

Supported

46-61 Reserved

DDR SDRAM Device Attributes: Number of Device

Banks

62 SPD

Revision

DDR SDRAM Device Attributes:

CAS Latencies Supported

63 Checksum

Data

DDR SDRAM Device Attributes: CS Latency

64-71

Manufacturer's JEDEC ID Code

20 DDR

SDRAM

Device

Attributes:

Latency

Module Manufacturing Location

DDR SDRAM Device Attributes:

73-90

Module Part number

22 DDR

SDRAM

Device

Attributes:

General 91-92

Module

Revision

Code

Minimum Clock Cycle

CL=2.5

93-94

Module Manufacturing Data

yy= Binary coded decimal year code, 0-99(Decimal),

00-63(Hex)

ww= Binary coded decimal year code, 01-52(Decimal),

01-34(Hex)

Maximum Data Access Time from Clock at

CL=2

95-98

Module Serial Number

Minimum Clock Cycle Time at CL=1

99-127

Reserved

NT512D64S8HB1G / NT512D64S8HB1GY / NT512D64S8HB0G
NT256D64S88B1G / NT256D64S88B1GY NT256D64S88B0G
NT128D64SH4B1G / NT512D72S8PB0G (ECC) / NT256D72S89B0G (ECC)
Unbuffered DDR DIMM

REV 2.2

Aug 3, 2004

Preliminary

© NANYA TECHNOLOGY CORPORATION

NANYA reserves the right to change products and specifications without notice.

SPD Values for NT512D64S8HBxGx

PC3200 (5T)

PC2700 (6K)

PC2100 (75B)

Byte

Value

Hex

Value

Hex

Value

Hex

128

256

SDRAM DDR

x64

SSTL 2.5V

5.0ns

6.0ns

7.5ns

6.0ns

7.0ns

7.5ns

Non-Parity

SR/1x(7.8us)

N/A

1 Clock

2,4,8

2/2.5/3

2/2.5

Differential Clock

±0.1V Tolerance

±0.2V Tolerance

6ns

7.5ns

10ns

0.70ns

0.75ns

7.5ns

N/A

7.5ns

N/A

15ns

18ns

20ns

10ns

12ns

15ns

18ns

20ns

40ns

42ns

45ns

256MB

0.60ns

0.75ns

0.90ns

0.60ns

0.75ns

0.90ns

0.40ns

0.45ns

0.50ns

0.40ns

0.45ns

0.50ns

36-40

Reserved

55ns

60ns

65ns

70ns

72ns

75ns

8ns

12ns

0.4ns

0.5ns

0.50ns

0.55ns

0.75ns

46-61

Reserved

Initial

Checksum

64-71 NANYA

7F7F7F0B

00000000

NANYA

7F7F7F0B

00000000

NANYA

7F7F7F0B

00000000

Assembly

73-90

Module PN

91-92

Revision

93-94

Year/Week Code

95-98

Serial Number

99-127

Reserved

NT512D64S8HB1G / NT512D64S8HB1GY / NT512D64S8HB0G
NT256D64S88B1G / NT256D64S88B1GY NT256D64S88B0G
NT128D64SH4B1G / NT512D72S8PB0G (ECC) / NT256D72S89B0G (ECC)
Unbuffered DDR DIMM

REV 2.2

Aug 3, 2004

Preliminary

© NANYA TECHNOLOGY CORPORATION

NANYA reserves the right to change products and specifications without notice.

SPD Values for NT256D64S88BxGx

PC3200 (5T)

PC2700 (6K)

PC2100 (75B)

Byte

Value

Hex

Value

Hex

Value

Hex

128

256

SDRAM DDR

x64

SSTL 2.5V

5.0ns

6.0ns

7.5ns

6.0ns

7.0ns

7.5ns

Non-Parity

SR/1x(7.8us)

N/A

1 Clock

2,4,8

2.5/3

2/2.5

Differential Clock

±0.1V Tolerance

±0.2V Tolerance

5ns

7.5ns

10ns

0.60ns

0.70ns

0.75ns

N/A

15ns

18ns

20ns

10ns

12ns

15ns

18ns

20ns

40ns

42ns

45ns

256MB

0.60ns

0.75ns

0.90ns

0.60ns

0.75ns

0.90ns

0.40ns

0.45ns

0.50ns

0.40ns

0.45ns

0.50ns

36-40

Reserved

60ns

72ns

12ns

0.4ns

0.55ns

46-61

Reserved

Initial

Checksum

64-71 NANYA

7F7F7F0B

00000000

NANYA

7F7F7F0B

00000000

NANYA

7F7F7F0B

00000000

Assembly

73-90

Module PN

91-92

Revision

93-94

Year/Week Code

95-98

Serial Number

99-127

Reserved

NT512D64S8HB1G / NT512D64S8HB1GY / NT512D64S8HB0G
NT256D64S88B1G / NT256D64S88B1GY NT256D64S88B0G
NT128D64SH4B1G / NT512D72S8PB0G (ECC) / NT256D72S89B0G (ECC)
Unbuffered DDR DIMM

REV 2.2

Aug 3, 2004

Preliminary

© NANYA TECHNOLOGY CORPORATION

NANYA reserves the right to change products and specifications without notice.

SPD Values for NT128D64SH4B1G

PC3200 (5T)

PC2700 (6K)

PC2100 (75B)

Byte

Value

Hex

Value

Hex

Value

Hex

128

256

SDRAM DDR

x64

SSTL 2.5V

5.0ns

6.0ns

7.5ns

6.0ns

7.0ns

7.5ns

Non-Parity

SR/1x(7.8us)

x16

N/A

1 Clock

2,4,8

2.5/3

2/2.5

Differential Clock

±0.1V Tolerance

±0.2V Tolerance

5ns

7.5ns

10ns

0.60ns

0.70ns

0.75ns

N/A

15ns

18ns

20ns

10ns

12ns

15ns

18ns

20ns

40ns

42ns

45ns

128MB

0.60ns

0.75ns

0.90ns

0.60ns

0.75ns

0.90ns

0.40ns

0.45ns

0.50ns

0.40ns

0.45ns

0.50ns

36-40

Reserved

60ns

72ns

12ns

0.4ns

0.55ns

46-61

Reserved

Initial

Checksum

64-71 NANYA

7F7F7F0B

00000000

NANYA

7F7F7F0B

00000000

NANYA

7F7F7F0B

00000000

Assembly

73-90

Module PN

91-92

Revision

93-94

Year/Week Code

95-98

Serial Number

99-127

Reserved

NT512D64S8HB1G / NT512D64S8HB1GY / NT512D64S8HB0G
NT256D64S88B1G / NT256D64S88B1GY NT256D64S88B0G
NT128D64SH4B1G / NT512D72S8PB0G (ECC) / NT256D72S89B0G (ECC)
Unbuffered DDR DIMM

REV 2.2

Aug 3, 2004

Preliminary

© NANYA TECHNOLOGY CORPORATION

NANYA reserves the right to change products and specifications without notice.

SPD Values for NT512D72S8PB0G

PC3200 (5T)

Byte

Value

Hex

128

256

SDRAM DDR

x74

SSTL 2.5V

5.0ns

6.0ns

Parity

SR/1x(7.8us)

ECC Width

1 Clock

2,4,8

2.5/3

Differential Clock

±0.1V Tolerance

5ns

0.60ns

N/A

15ns

10ns

15ns

40ns

256MB

0.60ns

0.40ns

36-40

Reserved

60ns

72ns

12ns

0.4ns

0.55ns

46-61

Reserved

Initial

Checksum

64-71 NANYA

7F7F7F0B

00000000

Assembly

73-90

Module PN

91-92

Revision

93-94

Year/Week Code

95-98

Serial Number

99-127

Reserved

NT512D64S8HB1G / NT512D64S8HB1GY / NT512D64S8HB0G
NT256D64S88B1G / NT256D64S88B1GY NT256D64S88B0G
NT128D64SH4B1G / NT512D72S8PB0G (ECC) / NT256D72S89B0G (ECC)
Unbuffered DDR DIMM

REV 2.2

Aug 3, 2004

Preliminary

NANYA reserves the right to change products and specifications without notice.

SPD Values for NT256D72S89B0G

PC3200 (5T)

Byte

Value

Hex

128

256

SDRAM DDR

x72

SSTL 2.5V

5.0ns

6.0ns

Parity

SR/1x(7.8us)

ECC Width

1 Clock

2,4,8

2.5/3

Differential Clock

±0.1V Tolerance

5ns

0.60ns

N/A

15ns

10ns

15ns

40ns

256MB

0.60ns

0.40ns

36-40

Reserved

60ns

72ns

12ns

0.4ns

0.55ns

46-61

Reserved

Initial

Checksum

64-71 NANYA

7F7F7F0B

00000000

Assembly

73-90

Module PN

91-92

Revision

93-94

Year/Week Code

95-98

Serial Number

99-127

Reserved

NT512D64S8HB1G / NT512D64S8HB1GY / NT512D64S8HB0G
NT256D64S88B1G / NT256D64S88B1GY NT256D64S88B0G
NT128D64SH4B1G / NT512D72S8PB0G (ECC) / NT256D72S89B0G (ECC)
Unbuffered DDR DIMM

REV 2.2

Aug 3, 2004

Preliminary

NANYA reserves the right to change products and specifications without notice.

Absolute Maximum Ratings

Symbol

Parameter

Rating

Units

, V

OUT

Voltage on I/O pins relative to V

-0.5 to V

DDQ

+0.5

Voltage on Input relative to V

-0.5 to +3.6

Voltage on V

supply relative to V

-0.5 to +3.6

DDQ

Voltage on V

DDQ

supply relative to V

-0.5 to +3.6

Operating Temperature (Ambient)

0 to +70

°C

STG

Storage Temperature (Plastic)

-55 to +150

°C

Power Dissipation (per device component)

1 W

OUT

Short Circuit Output Current

50 mA

Note: Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is stress

rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this

specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

DC Electrical Characteristics and Operating Conditions

= 0°C ~ 70°C; V

DDQ

= V

= 2.5V±0.2V(PC2100,PC2700); T

= 0°C ~ 70°C; V

DDQ

= V

= 2.6V±0.1V(PC3200)

Symbol Parameter Min

Max

Units

Notes

Supply Voltage

PC2100, PC2700

2.3

PC3200

2.5

2.7 V

I/O Supply Voltage

PC2100, PC2700

2.3

DDQ

PC3200

2.5

2.7 V

, V

SSQ

Supply Voltage, I/O Supply Voltage

REF

I/O Reference Voltage

0.49 x

DDQ

0.51 x

DDQ

V 1,

I/O Termination Voltage (System)

REF

0.04

REF

+ 0.04

1, 3

IH (DC)

Input High (Logic1) Voltage

REF

+ 0.15

DDQ

+ 0.3

IL (DC)

Input Low (Logic0) Voltage

-0.3

REF

- 0.15

IN (DC)

Input Voltage Level, CK and

Inputs

-0.3

DDQ

+ 0.3

ID (DC)

Input Differential Voltage, CK and

Inputs

0.30

DDQ

+ 0.6

1, 4

Input Leakage Current

Any input 0V

;

All other pins not under test = 0V

-10 10

A 1

Output Leakage Current

DQs are disabled; 0V

out

DDQ

-10 10

A 1

Output High Current

OUT

DDQ

-0.373V, min V

REF

min V

)

-16.8 -

Output Low Current

OUT

= 0.373, max V

REF

max V

)

16.8 -

1. Inputs are not recognized as valid until V

REF

stabilizes.

2. V

REF

is expected to be equal to 0.5 V

DDQ

of the transmitting device, and to track variations in the DC level of the same. Peak-to-peak

noise on V

REF

may not exceed 2% of the DC value.

3. V

is not applied directly to the DIMM. V

is a system supply for signal termination resistors, is expected to be set equal to V

REF

and must track variations in the DC level of V

REF

4. V

is the magnitude of the difference between the input level on CK and the input level on

NT512D64S8HB1G / NT512D64S8HB1GY / NT512D64S8HB0G
NT256D64S88B1G / NT256D64S88B1GY NT256D64S88B0G
NT128D64SH4B1G / NT512D72S8PB0G (ECC) / NT256D72S89B0G (ECC)
Unbuffered DDR DIMM

REV 2.2

Aug 3, 2004

Preliminary

NANYA reserves the right to change products and specifications without notice.

AC Characteristics

Notes 1-5 apply to the following Tables; Electrical Characteristics and DC Operating Conditions, AC Operating

Conditions, Operating, Standby, and Refresh Currents, and Electrical Characteristics and AC Timing.)

1. All voltages referenced to V

2. Tests for AC timing, IDD, and electrical, AC and DC characteristics, may be conducted at nominal reference/supply voltage levels, but the

related specifications and device operation are guaranteed for the full voltage range specified.

3. Outputs measured with equivalent load. Refer to the AC Output Load Circuit below.

4. AC timing and IDD tests may use a V

to V

swing of up to 1.5V in the test environment, but input timing is still referenced to V

REF

(or to

the crossing point for CK,

), and parameter specifications are guaranteed for the specified AC input levels under normal use conditions.

The minimum slew rate for the input signals is 1V/ns in the range between V

IL (AC)

and V

IH (AC)

unless otherwise specified.

5. The AC and DC input level specifications are as defined in the SSTL_2 Standard (i.e. the receiver effectively switches as a result of the

signal crossing the AC input level, and remains in that state as long as the signal does not ring back above (below) the DC input LOW

(HIGH) level.

AC Output Load Circuits

Timing Reference Point

50 ohms

30 pF

Output

OUT

AC Operating Conditions

= 0 °C ~ 70 °C; V

DDQ

= V

= 2.5V ± 0.2V (PC2100/PC2700); V

DDQ

= V

= 2.6V ± 0.1V (PC3200)

Symbol

Parameter/Condition

Min

Max

Unit

Notes

IH (AC)

Input High (Logic 1) Voltage.

REF

+ 0.31

1, 2

IL (AC)

Input Low (Logic 0) Voltage.

REF

- 0.31

1, 2

ID (AC)

Input Differential Voltage, CK and

Inputs

0.62

DDQ

+ 0.6

1, 2, 3

IX (AC)

Input Differential Pair Cross Point Voltage, CK and

Inputs

(0.5* V

DDQ

)

- 0.2

(0.5* V

DDQ

)

+ 0.2

1, 2, 4

1. Input slew rate = 1V/ ns.

2. Inputs are not recognized as valid until V

REF

stabilizes.

3. V

is the magnitude of the difference between the input level on CK and the input level on

4. The value of V

is expected to equal 0.5*V

DDQ

of the transmitting device and must track variations in the DC level of the same.

NT512D64S8HB1G / NT512D64S8HB1GY / NT512D64S8HB0G
NT256D64S88B1G / NT256D64S88B1GY NT256D64S88B0G
NT128D64SH4B1G / NT512D72S8PB0G (ECC) / NT256D72S89B0G (ECC)
Unbuffered DDR DIMM

REV 2.2

Aug 3, 2004

Preliminary

NANYA reserves the right to change products and specifications without notice.

Operating, Standby, and Refresh Currents

= 0 °C ~ 70 °C; V

DDQ

= V

= 2.5V ± 0.2V (PC2100/PC2700); V

DDQ

= V

= 2.6V ± 0.1V (PC3200)

Symbol

Parameter/Condition

Notes

IDD0

Operating Current: one bank; active/precharge; t

= t

RC (MIN)

; t

= t

CK (MIN)

; DQ, DM, and DQS inputs changing twice per

clock cycle; address and control inputs changing once per clock cycle

1,2

IDD1

Operating Current: one bank; active/read/precharge; Burst = 2; t

= t

RC (MIN)

; CL=2.5; t

= t

CK (MIN)

; I

OUT

= 0mA; address and

control inputs changing once per clock cycle

1,2

IDD2P Precharge Power-Down Standby Current: all banks idle; power-down mode; CKE

IL (MAX)

; t

= t

CK (MIN)

1,2

IDD2N

Idle Standby Current: CS

IH (MIN)

; all banks idle; CKE

IH (MIN)

; t

= t

CK (MIN)

; address and control inputs changing once

per clock cycle

1,2

IDD3P Active Power-Down Standby Current: one bank active; power-down mode; CKE

IL (MAX)

; t

= t

CK (MIN)

1,2

IDD3N

Active Standby Current: one bank; active/precharge; CS

IH (MIN)

; CKE

IH (MIN)

; t

= t

RAS (MAX)

; t

= t

CK (MIN)

; DQ, DM, and

DQS inputs changing twice per clock cycle; address and control inputs changing once per clock cycle

1,2

IDD4R

Operating Current: one bank; Burst = 2; reads; continuous burst; address and control inputs changing once per clock cycle;

DQ and DQS outputs changing twice per clock cycle; CL = 2.5; t

= t

CK (MIN)

; I

OUT

= 0mA

1,2

IDD4W

Operating Current: one bank; Burst = 2; writes; continuous burst; address and control inputs changing once per clock cycle;

DQ and DQS inputs changing twice per clock cycle; CL=2.5; t

= t

CK (MIN)

1,2

IDD5

Auto-Refresh Current: t

= t

RFC (MIN)

1,2,3

IDD6

Self-Refresh Current: CKE

0.2V

1,2

IDD7

Operating Current: four bank; four bank interleaving with BL = 4, address and control inputs randomly changing; 50% of

data changing at every transfer; t

= t

RC (min)

; I

OUT

= 0mA.

1,2

1. IDD specifications are tested after the device is properly initialized.

2. Input slew rate = 1V/ ns.

3. Current at 7.8

s is time averaged value of IDD5 at t

RFC (MIN)

and IDD2P over 7.8

All IDD current values are calculated from device level.

NT512D64S8HB1G / NT512D64S8HB1GY / NT512D64S8HB0G
NT256D64S88B1G / NT256D64S88B1GY NT256D64S88B0G
NT128D64SH4B1G / NT512D72S8PB0G (ECC) / NT256D72S89B0G (ECC)
Unbuffered DDR DIMM

REV 2.2

Aug 3, 2004

Preliminary

NANYA reserves the right to change products and specifications without notice.

NT512D64S8HB1Gx NT256D64S88B1Gx

NT128D64SH4B1G

Symbol

PC3200

(5T)

PC2700

(6K)

PC2100

(75B)

PC3200

(5T)

PC2700

(6K)

PC2100

(75B)

PC3200

(5T)

PC2700

(6K)

PC2100

(75B)

IDD0

1915

1755

1585

995 915 825 460 420 380

IDD1

1995 1995 1825 1035 1035 945 480 480 440

IDD2P

340 340 340 180 180 180 80 80 80

IDD2N

765 765 680 405 405 360 180 180 160

IDD3P

357 357 306 189 189 162 84 84 72

IDD3N

1275

1105

675 675 585 300 300 260

IDD4R

3275 3275 2705 1675 1675 1385 800 800 660

IDD4W

3195 3195 2625 1635 1635 1345 780 780 640

IDD5

3675 2875 2785 1875 1475 1425 900 700 680

IDD6

51 51 51 27 27 27 12 12 12

IDD7

5275 5275 4065 2675 2675 2065 1300 1300 1000

NT512D72S8PB0G

NT256256D64S89B0G

Symbol

PC3200

(5T)

PC2700

(6K)

PC2100

(75B)

PC3200

(5T)

PC2700

(6K)

PC2100

(75B)

IDD0

1915 1755 1585 995

915 825

IDD1

1995 1995 1825 1035 1035 945

IDD2P

340 340 340 180 180 180

IDD2N

765 765 680 405 405 360

IDD3P

357 357 306 189 189 162

IDD3N

1275 1275 1105 675

675 585

IDD4R

3275 3275 2705 1675 1675 1385

IDD4W

3195 3195 2625 1635 1635 1345

IDD5

3675 2875 2785 1875 1475 1425

IDD6

51 51 51 27 27 27

IDD7

5275 5275 4065 2675 2675 2065

NT512D64S8HB1G / NT512D64S8HB1GY / NT512D64S8HB0G
NT256D64S88B1G / NT256D64S88B1GY NT256D64S88B0G
NT128D64SH4B1G / NT512D72S8PB0G (ECC) / NT256D72S89B0G (ECC)
Unbuffered DDR DIMM

REV 2.2

Aug 3, 2004

Preliminary

NANYA reserves the right to change products and specifications without notice.

AC Timing Specifications for DDR SDRAM Devices Used on Module

= 0 °C ~ 70 °C; V

DDQ

= V

= 2.5V ± 0.2V (PC2100/PC2700); V

DDQ

= V

= 2.6V ± 0.1V (PC3200) (Part 1 of 2)

Symbol Parameter

PC3200

PC2700

75B

PC2100

Unit Notes

Min. Max. Min. Max. Min. Max.

DQ output access time from CK/

-0.65 +0.65 -0.7 +0.7 -0.75 +0.75 ns 1-4

DQSCK

DQS output access time from CK/

-0.55 +0.55 -0.7 +0.7 -0.75 +0.75 ns 1-4

high-level

width

0.45 0.55 0.45 0.55 0.45 0.55 t

1-4

low-level

width

0.45 0.55 0.45 0.55 0.45 0.55 t

1-4

Clock cycle time CL=3

Clock cycle time CL=2.5

7.5

1-4

Clock cycle time CL=2

7.5

1-4

DQ and DM input hold time

0.4

0.45 0.5 ns

1-4,

15, 16

DQ and DM input setup time

0.4

0.45 0.5 ns

1-4,

15, 16

DIPW

DQ and DM input pulse width (each input)

1.75

1-4

Data-out high-impedance time from CK/

-0.6 +0.6 -0.7 +0.7 -0.75

+0.75

1-4,

Data-out low-impedance time from CK/

-0.6 +0.6 -0.7 +0.7 -0.75

+0.75

1-4,

DQSQ

DQS-DQ skew (DQS & associated DQ signals) 0.4 0.45 0.5

1-4

Minimum half clk period for any given cycle;

defined by clk high (t

) or clk low (t

) time

1-4

Data output hold time from DQS

QHS

1-4

QHS

Data hold Skew Factor

0.5

0.55

0.75

1-4

DQSS

Write command to 1st DQS latching transition

0.75

1.25

0.75

1.25

0.75

1.25

1-4

DQSL

DQSH

DQS input low (high) pulse width

(write cycle)

0.35 0.35 0.35 t

1-4

DSS

DQS falling edge to CK setup time

(write cycle)

0.2 0.2 0.2 t

1-4

DSH

DQS falling edge hold time from CK

(write cycle)

0.2 0.2 0.2 t

1-4

MRD

Mode register set command cycle time

1-4

WPRES

Write

preamble

setup

time

0 0 0

1-4,

WPST

Write

postamble

0.40 0.60 0.40 0.60 0.40 0.60 t

1-4,

WPRE

Write

preamble

0.25 0.25 0.25 t

1-4

Address and control input hold time

(fast slew rate)

0.6

0.75 0.9 ns

2-4, 9,

11, 12

Address and control input setup time

(fast slew rate)

0.6

0.75 0.9 ns

2-4, 9,

11, 12

Address and control input hold time

(slow slew rate)

0.7

0.8 1.0 ns

2-4,

10, 11,

12, 14

NT512D64S8HB1G / NT512D64S8HB1GY / NT512D64S8HB0G
NT256D64S88B1G / NT256D64S88B1GY NT256D64S88B0G
NT128D64SH4B1G / NT512D72S8PB0G (ECC) / NT256D72S89B0G (ECC)
Unbuffered DDR DIMM

REV 2.2

Aug 3, 2004

Preliminary

NANYA reserves the right to change products and specifications without notice.

AC Timing Specifications for DDR SDRAM Devices Used on Module

= 0 °C ~ 70 °C; V

DDQ

= V

= 2.5V ± 0.2V (PC2100/PC2700); V

DDQ

= V

= 2.6V ± 0.1V (PC3200) (Part 2 of 2)

PC3200

PC2700

75B

PC2100

Unit Notes

Symbol Parameter

Min. Max. Min. Max. Min. Max.

Address and control input setup time

(slow slew rate)

0.7

0.8 1.0 ns

2-4,

10-12,

IPW

Input

pulse

width

2.2 2.2 2.2 ns

2-4, 12

RP RE

Read

preamble

0.9 1.1 0.9 1.1 0.9 1.1 t

1-4

RP ST

Read

postamble

0.40 0.60 0.40 0.60 0.40 0.60 t

1-4

RAS

Active to Precharge command

42ns 120us 42ns 120us 45ns 120us

1-4

Active to Active/Auto-refresh command period

1-4

RFC

Auto-refresh to Active/Auto-refresh command

period

72 75

ns 1-4

RCD

Active to Read or Write delay

1-4

RAP

Active to Read Command with Auto-precharge

1-4

Precharge

command

period

15 18 20

1-4

RRD

Active bank A to Active bank B command

1-4

Write

recovery

time

15 15 15

1-4

DAL

Auto-precharge write recovery + precharge time

) +

)

) +

)

) +

)

1-4,

WTR

Internal

write

read

command

delay

1 1 1

1-4

PDEX

Power

down

exit

time

5 6 7.5

1-4

XSNR

Exit self-refresh to non-read command

1-4

XSRD

Exit self-refresh to read command

200

1-4

REFI

Average

Periodic

Refresh

Interval

7.8 7.8 7.8

s 1-4,

NT512D64S8HB1G / NT512D64S8HB1GY / NT512D64S8HB0G
NT256D64S88B1G / NT256D64S88B1GY NT256D64S88B0G
NT128D64SH4B1G / NT512D72S8PB0G (ECC) / NT256D72S89B0G (ECC)
Unbuffered DDR DIMM

REV 2.2

Aug 3, 2004

Preliminary

NANYA reserves the right to change products and specifications without notice.

AC Timing Specification Notes

1. Input slew rate = 1V/ns.

2. The CK/

input reference level (for timing reference to CK/

) is the point at which CK and

cross: the input reference level for

signals other than CK/

is V

REF

3. Inputs are not recognized as valid until V

REF

stabilizes.

4. The Output timing reference level, as measured at the timing reference point indicated in AC Characteristics (Note 3) is V

5. t

and t

transitions occur in the same access time windows as valid data transitions. These parameters are not referred to a specific

voltage level, but specify when the device is no longer driving (HZ), or begins driving (LZ).

6. The maximum limit for this parameter is not a device limit. The device operates with a greater value for this parameter, but system

performance (bus turnaround) degrades accordingly.

7. The specific requirement is that DQS be valid (high, low, or some point on a valid transition) on or before this CK edge. A valid transition

is defined as monotonic and meeting the input slew rate specifications of the device. When no writes were previously in progress on the

bus, DQS will be transitioning from Hi-Z to logic LOW. If a previous write was in progress, DQS could be HIGH, LOW, or transitioning from

high to low at this time, depending on t

DQSS

8. A maximum of eight Auto refresh commands can be posted to any given DDR SDRAM device.

9. For command/address input slew rate >= 1.0 V/ns. Slew rate is measured between V

OH (AC)

and V

OL (AC)

10. For command/address input slew rate >= 0.5 V/ns and < 1.0 V/ns. Slew rate is measured between V

OH (AC)

and V

OL (AC)

11. CK/

slew rates are >= 1.0 V/ns.

12. These parameters guarantee device timing, but they are not necessarily tested on each device, and they may be guaranteed by design

or tester characterization.

13. For each of the terms in parentheses, if not already an integer, round to the next highest integer. t

is equal to the actual system clock

cycle time. For example, for PC2100 at CL= 2.5, t

DAL

= (15ns/7.5ns) +(20ns/7.0ns) = 2 + 3 = 5.

14. An input setup and hold time derating table is used to increase t

and t

in the case where the input slew rate is below 0.5 V/ns.

Input Slew Rate

Delta (t

)

Delta

)

Unit

Note

0.5 V/ns

1, 2

0.4 V/ns

+50

1, 2

0.3 V/ns

+100

1, 2

Input slew rate is based on the lesser of the slew rates determined by either V

IH (AC)

to V

IL (AC)

or V

IH (DC)

to V

IL (DC)

, similarly for rising

transitions.

These derating parameters may be guaranteed by design or tester characterization and are not necessarily tested on each device.

15. An input setup and hold time derating table is used to increase t

and t

in the case where the I/O slew rate is below 0.5 V/ns.

Input Slew Rate

Delta (t

) Delta

) Unit

Note

0.5 V/ns

1, 2

0.4 V/ns

+75

1, 2

0.3 V/ns

+150

1, 2

I/O slew rate is based on the lesser of the slew rates determined by either V

IH (AC)

to V

IL (AC)

or V

IH (DC)

to V

IL (DC)

, similarly for rising

transitions.

These derating parameters may be guaranteed by design or tester characterization and are not necessarily tested on each device.

16. An I/O Delta Rise, Fall Derating table is used to increase t

and t

in the case where DQ, DM, and DQS slew rates differ.

Delta Rise and Fall Rate

Delta (t

) Delta

) Unit

Note

0.0 ns/V

1-4

0.25 ns/V

+50

1-4

0.5 ns/V

+100

1-4

Input slew rate is based on the lesser of the slew rates determined by either V

IH (AC)

to V

IL (AC)

or V

IH (DC)

to V

IL (DC)

, similarly for rising

transitions.

Input slew rate is based on the larger of AC to AC delta rise, fall rate and DC to DC delta rise, fall rate.

The delta rise, fall rate is calculated as: [1/(slew rate 1)] - [1/(slew rate 2)]
For example: slew rate 1 = 0.5 V/ns; slew rate 2 = 0.4 V/ns. Delta rise, fall = (1/0.5) - (1/0.4) [ns/V] = -0.5 ns/V
Using the table above, this would result in an increase in t

and t

of 100 ps.

These derating parameters may be guaranteed by design or tester characterization and are not necessarily tested on each device.

NT512D64S8HB1G / NT512D64S8HB1GY / NT512D64S8HB0G
NT256D64S88B1G / NT256D64S88B1GY NT256D64S88B0G
NT128D64SH4B1G / NT512D72S8PB0G (ECC) / NT256D72S89B0G (ECC)
Unbuffered DDR DIMM

REV 2.2

Aug 3, 2004

Preliminary

NANYA reserves the right to change products and specifications without notice.

Revision Log

Rev Date

Modification

0.1 12/2003

Updated

format.

1.0 Dec

19,2003 Release

1.1

Feb 11, 2004

Correction to block diagram label.

Correction to SPD bank and checksum values.

Package dimension added for x8 wide devices.

2.0

Mar 4, 2004

Document reorganized by order of B die generation / size and DIMM format.

DIMM: unbuffered DIMM

Speed grades: 5T, 6K, 75B

Modules: NT512D64S8HB1G, NT256D64S88B1G, NT128D64SH4B1G

Modules: NT512D72S8PB0G, NT256D72S89B0G

Modules: NT512D64S8HB1GY, NT256D64S88B1GY

2.1

May 11, 2004

Added NT256D64S88B0G-6K speed grade to ordering information.

2.2

Aug 3, 2004

Corrected SPD contents.

Nanya Technology Corporation

Hwa Ya Technology Park 669

Fu Hsing 3rd Rd., Kueishan,

Taoyuan, 333, Taiwan, R.O.C.

Tel: +886-3-328-1688

Please visit our home page for more information:

www.nanya.com

Nanya reserves the right to make changes or deletions without any notice to any of its products. Nanya makes no guarantee, warranty or representation regarding the suitability of
its products for any particular purpose. Nanya assumes no liability arising out of the application or use of its products. All parameters can and do vary in its application and must
be validated for each customer application by the customer's technician. By purchasing Nanya products, Nanya does not convey any license under its patent rights not the rights
of others. Nanya products are not designed or intended or authorized for use in systems intended for the military or surgical implants or any other applications where life is involved
or where injury or death may occur or the loss/corruption of data or the loss of system reliability or mission critical applications. Should the buyer purchase or use Nanya products
in such unintended or unauthorized application, the Buyer and user shall indemnify and hold Nanya and its officers, employees, subsidiaries, affiliates and distributors harmless
against all claims, costs, damages, all fees and expenses directly or indirectly arising from any claim of loss, injury or death associated with unintended or unauthorized use even
if such claims alleges Nanya was negligent regarding design or manufacture of the part. Nanya and the Nanya logo are trademarks of the Nanya Technology Corporation.

Printed in Taiwan

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: NT128D64SH4B1G-6K

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: NT128D64SH4B1G-6K