NT511740D5J
16MEG : x4
CMOS with Extended Data Out
REV 1.0 May. 2000 1
NANYA TECHNOLOGY CORP.
NAYNA TECHNOLOGY CORP. reserves the right to change products and specifications without notice.
NT511740D5J
DATA SHEET
NT511740D5J
16MEG : x4
CMOS with Extended Data Out
REV 1.0 May. 2000 2
NANYA TECHNOLOGY CORP.
NAYNA TECHNOLOGY CORP. reserves the right to change products and specifications without notice.
Contents
Table of Contents.........................................................................................................................................................02
Description...................................................................................................................................................................03
Features........................................................................................................................................................................03
Product Family
............................................................................................................................................................03
Pin Assignment............................................................................................................................................................04
Electrical Characteristics ............................................................................................................................................05
Absolute Maximum Ratings
......................................................................................................................................05
Recommended DC Operating Conditions
.....................................................................................................................05
Capacitance
..........................................................................................................................................................05
DC Electrical Characteristics
.....................................................................................................................................06
AC Characteristics .......................................................................................................................................................07
Timing Waveform.........................................................................................................................................................10
Read Cycle
...........................................................................................................................................................10
Write Cycle
...........................................................................................................................................................10
Read Modify Write Cycle
..........................................................................................................................................11
Fast Page Mode Read Cycle
.....................................................................................................................................11
Fast Page Mode Write Cycle
.....................................................................................................................................12
Fast Page Mode Read Modify Write Cycle
....................................................................................................................13
RAS
-
only Refresh Cycle
........................................................................................................................................13
CAS
-before-
RAS
refresh ..................................................................................................................................14
Hidden Refresh Read..........................................................................................................................................15
Package Dimension .....................................................................................................................................................16
NT511740D5J
16MEG : x4
CMOS with Extended Data Out
REV 1.0 May. 2000 3
NANYA TECHNOLOGY CORP.
NAYNA TECHNOLOGY CORP. reserves the right to change products and specifications without notice.
DESCRIPTION
This is a family of 4,194,304 x 4 bit Extended Data Out CMOS DRAMs. Extended Data Out Mode offers high speed
random access of memory cells within the same row, so called Hyper Page Mode. Power supply voltage (+5.0V ), refresh
cycle (2K Ref), access time (-5 or -6), power consumption (Normal or Low power) and package type (SOJ) are optional
features of this family.
All of this family have
CAS
-before-
RAS
refresh,
RAS
-only refresh and Hidden refresh capabilities. Furthermore,
Self-refresh operation is available in L-version. This 4Mx4 EDO Mode DRAM family is fabricated using NANYA's advanced
CMOS process to realize high bandwidth, low power consumption and high reliability.
It may be used as main memory unit for microcomputer, high level computer and personal computer .
FEATURES
Extended Data Out Mode operation (Fast Page Mode with Extended Data Out)
TTL(5V) compatible inputs and outputs
Single +5V 10% power supply (5V product)
JEDEC Standard pinout
CAS
before
RAS
refresh, hidden refresh,
RAS
-only refresh capability
Refresh : 2048 cycles / 32 ms
Self-refresh capability (L-ver only)
Multi-bit test mode capability
Available in plastic SOJ packages
PRODUCT FAMILY
Access Time (Max.)
Family
tRAC
tCAC
tRC
tHPC
Active Power
Dissipation
Voltage
Package
NT511740D5J - 50/5L
50ns
15ns
84ns
20ns
605mW
NT511740D5J - 60/6L
60ns
17ns
104ns
25ns
550mW
5V
26(24)-pin
SOJ
NT511740D5J
16MEG : x4
CMOS with Extended Data Out
REV 1.0 May. 2000 4
NANYA TECHNOLOGY CORP.
NAYNA TECHNOLOGY CORP. reserves the right to change products and specifications without notice.
PIN CONFIGURATION
(TOP VIEW)
300mil 26(24)-pin SOJ
Pin Name Pin Function
A0-A10
Address Inputs
DQ0-DQ3 Data Input / Output
Ground
CAS
Column Address Strob
RAS
Row Address Strob
W
Read/Write Input
V
CC
Power +5.0 V ( + 3.3V )
No Connection
NC
Vss
OE
Data Output Enable
V
CC
DQ0
DQ1
W
RAS
NC
A10
A0
A1
A2
Vss
DQ3
DQ2
CAS
A5
24
23
1
2
3
4
5
6
7
8
9
10
11
22
21
20
19
18
17
16
15
14
12
A3
Vcc
Vss
A6
OE
A4
A8
A7
A9
NT511740D5J
13
NT511740D5J
16MEG : x4
CMOS with Extended Data Out
REV 1.0 May. 2000 5
NANYA TECHNOLOGY CORP.
NAYNA TECHNOLOGY CORP. reserves the right to change products and specifications without notice.
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
Parameter
Symbol
Rating
Unit
Voltage on Any Pin Relative to V
SS
V
IN
,
V
OUT
-1.0 to +7.0
V
Voltage on V
CC
Supply Relative to V
SS
V
CC
-1.0 to +7.0
V
Short Circuit Output Current
I
OS
50
mA
Power Dissipation
P
D
*
1
W
Operation Temperature
T
opr
0 to 70
C
Storage Temperature
T
stg
-55 to 150
C
*:Ta = 25C
Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded. Functional operation should
be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
Recommended Operating Conditions
(Voltage referenced to Vss, Ta = 0C to 70C )
Parameter
Symbol
Min.
Typ.
Max.
Unit
Supply Voltage
V
CC
4.5
5.0
5.5
V
Ground
V
SS
0
0
0
V
Input High Voltage
V
IH
2.4
-
Vcc+1.0
*1
V
Input Low Voltage
V
IL
-1.0
*2
-
0.8
V
*1 : V
cc
+2.0V/20ns(5V), Pulse width is measured at V
cc
*2 : -2.0V/20ns(5V), Pulse width is measured at V
ss
Capacitance
( Vcc = 5V, Ta = 25C, f = 1 MHZ )
Parameter
Symbol
Typ.
Max.
Unit
Input Capacitance (A0-A11)
C
IN1
-
5
pF
Input Capacitance (
RAS
,
CAS
,
WE
,
OE
)
C
IN2
-
7
pF
Output Capacitance (DQ0-DQ3)
C
I/O
-
7
pF
DC Characteristics
(Recommended operating conditions unless otherwise noted.)
Max
Parameter
Symbol
Min
Max
Units
Input Leakage Current (Any input 0 <= V
IN
<= V
IN
+0.5V,
all other input pins not under test =0 Volt)
I
I(L)
-5
5
uA
Output Leakage Current
(Data out is disabled, 0 <= V
OUT
<=
V
CC
)
I
O(L)
-5
5
uA
Output High Voltage Level (I
OH
= -5mA)
V
OH
2.4
-
V
5V
Output Low Voltage Level (I
OL
=4.2mA)
V
OL
-
0.4
V
NT511740D5J
16MEG : x4
CMOS with Extended Data Out
REV 1.0 May. 2000 6
NANYA TECHNOLOGY CORP.
NAYNA TECHNOLOGY CORP. reserves the right to change products and specifications without notice.
DC CHARACTERISTICS
( Continued )
Symbol
Power
Speed
Max
Units
-5
110
mA
ICC1
Don't care
-6
100
mA
Normal
2
mA
ICC2
L
Don't care
1
mA
-5
110
mA
ICC3
Don't care
-6
100
mA
-5
90
mA
ICC4
Don't care
-6
80
mA
Normal
3
mA
ICC5
L
Don't care
200
uA
-5
110
mA
ICC6
Don't care
-6
100
mA
ICC7
L
Don't care
300
uA
ICCS
L
Don't care
250
uA
ICC1* : Operating Current (
RAS
and CAS cycling @ t
RC
=min.)
ICC2 : Standby Current (
RAS
=
CAS
=
W
=V
IH
)
ICC3* :
RAS
-only Refresh Current (
RAS
=V
IH
,
RAS
cycling @ t
RC
=min.)
ICC4* : Hyper Page Mode Current (
RAS
=V
IL
,
CAS
Address cycling @ t
HPC
=min.)
ICC5 : Standby Current (
RAS
=
CAS
=
W
=V
CC
-0.2V)
ICC6* : CAS-Before-
RAS
Refresh Current (
RAS
,
CAS
c
ycling @ t
RC
=min.)
ICC7 : Battery back-up current, Average power supply current, Battery back-up mode Input high voltage (V
IH
)=VCC-0.2V,
Input low voltage (V
IL
)=0.2V,
CAS
=0.2V, DQ=Don't care, t
RC
=125us(2K/L-ver) , t
RAS
=t
RAS
min~300ns
ICCS : Self Refresh Current
(
RAS
=
CAS
=0.2V,
W
=
OE
=A0 ~ A11=VCC-0.2V or 0.2V, DQ0 ~ DQ3=VCC-0.2V, 0.2V or open )
*Note : ICC1, ICC3, ICC4 and ICC6 are dependent on output loading and cycle rates. Specified values are obtained with
the output open. ICC is specified as an average current. In ICC1, ICC3 and ICC6, address can be changed
maximum once while
RAS
=V
IL
. In ICC4, address can be changed maximum once within one hyper page mode
cycle time, t
HPC
.
NT511740D5J
16MEG : x4
CMOS with Extended Data Out
REV 1.0 May. 2000 7
NANYA TECHNOLOGY CORP.
NAYNA TECHNOLOGY CORP. reserves the right to change products and specifications without notice.
AC CHARACTERISTICS
(0
C <= Ta <= 70
C , See note 1,2) ; Test condition : VCC=5.0V 10%, V
IH
/V
IL
=2.4/0.8V, V
OH
/V
OL
=2.0/0.8V
-50
-60
Parameter
Symbol
Min
Max
Min
Max
Unit
Notes
Random read or write cycle time
t RC
84
-
104
-
ns
Read-modify-write cycle time
t RWC
110
135
ns
Access time from
RAS
t RAC
50
60
ns
3,4,10
Access time from
CAS
t CAC
13
15
ns
3,4,5
Access time from column address
t AA
25
30
ns
3,10
CAS
to output in Low-Z
t CLZ
0
0
ns
3
Output buffer turn-off delay from
CAS
t CEZ
0
0
ns
6,14
OE
to output in Low-Z
t OLZ
0
0
ns
3
Transition time (rise and fall)
t T
1
1
ns
2
RAS
precharge time
t RP
30
40
ns
RAS
pulse width
t RAS
50
60
ns
RAS
hold time
t RSH
7
10
ns
CAS
hold time
t CSH
35
40
ns
CAS
pulse width
t CAS
7
10
ns
RAS
to
CAS
delay time
t RCD
11
14
ns
4
RAS
to column address delay time
t RAD
9
12
ns
10
CAS
to
RAS
precharge time
t CRP
5
5
ns
Row address set-up time
t ASR
0
0
ns
Row address hold time
t RAH
7
10
ns
Column address set-up time
t ASC
0
0
ns
Column address hold time
t CAH
7
10
ns
Column address to
RAS
lead time
t RAL
25
30
ns
Read command set-up time
t RCS
0
0
ns
Read command hold time referenced to
CAS
t RCH
0
0
ns
8
Read command hold time referenced to
RAS
t RRH
0
0
ns
8
Write command hold time
t WCH
7
10
ns
Write command pulse width
t WP
7
10
ns
Write command to
RAS
lead time
t RWL
7
10
ns
Write command to
CAS
lead time
t CWL
7
10
ns
Data set-up time
t DS
0
0
ns
9
Data hold time
t DH
7
10
ns
9
Refresh period (2K, Normal)
t REF
32
32
ms
Refresh period (L-ver)
t REF
128
128
ms
Write command set-up time
t WCS
0
0
ns
7
NT511740D5J
16MEG : x4
CMOS with Extended Data Out
REV 1.0 May. 2000 8
NANYA TECHNOLOGY CORP.
NAYNA TECHNOLOGY CORP. reserves the right to change products and specifications without notice.
AC CHARACTERISTICS
(Continued )
-50
-60
Parameter
Symbol
Min
Max
Min
Max
Unit
Notes
CAS
to
W
delay time
t CWD
30
34
ns
7
RAS
to
W
delay time
t RWD
67
79
ns
7
Column address to
W
delay time
t AWD
42
49
ns
7
CAS
precharge to
W
delay time
t CPWD
47
54
ns
CAS
set-up time (
CAS
-before-
RAS
refresh) t CSR
5
5
ns
CAS
hold time (
CAS
-before-
RAS
refresh)
t CHR
10
10
ns
RAS
to CAS precharge time
t RPC
5
5
ns
Access time from
CAS
precharge
t CPA
28
35
ns
3
Hyper Page cycle time
t HPC
20
25
ns
13
Hyper Page read-modify-write cycle time
t HPRWC
47
56
ns
13
CAS
precharge time (Hyper Page cycle)
t CP
7
10
ns
RAS
pulse width (Hyper Page cycle)
t RASP
50
100k
60
100k
ns
RAS
hold time from
CAS
precharge
t RHCP
30
35
ns
OE
access time
t OEA
13
15
ns
OE
to data delay
t OED
12
15
ns
Output buffer turn off delay time from
OE
t OEZ
3
3
ns
6
OE
command hold time
t OEH
7
10
ns
Write command set-up time (Test mode in)
t WTS
7
10
ns
11
Write command hold time (Test mode in)
t WTH
10
10
ns
11
W
to
RAS
precharge time(C-B-R refresh)
t WRP
10
10
ns
W
to
RAS
hold time(C-B-R refresh)
t WRH
10
10
ns
Output data hold time
t DOH
5
5
ns
Output buffer turn off delay from
RAS
t REZ
0
0
ns
6,14
Output buffer turn off delay from
W
t WEZ
0
0
ns
6
W
to data delay
t WED
10
10
ns
OE
to
CAS
hold time
t OCH
5
5
ns
CAS
hold time to OE
t CHO
5
5
ns
OE
precharge time
t OEP
7
10
ns
W
pulse width (Hyper Page Cycle)
t WPE
7
10
ns
RAS
pulse width (C-B-R self refresh)
t RASS
100
100
ns
15,16,17
RAS
precharge time (C-B-R self refresh)
t RPS
90
110
ns
15,16,17
CAS
hold time (C-B-R self refresh)
t CHS
-50
-50
ns
15,16,17
NT511740D5J
16MEG : x4
CMOS with Extended Data Out
REV 1.0 May. 2000 9
NANYA TECHNOLOGY CORP.
NAYNA TECHNOLOGY CORP. reserves the right to change products and specifications without notice.
NOTES
1. An initial pause of 200us is required after power-up followed by any 8
RAS
-only refresh or
CAS
-before-
RAS
refresh
Cycles before proper device operation is achieved.
2. VIH(min) and VlL(max) are reference levels for measuring timing of input signals. Transition times are measured between
VIH(min) and
VI
L(max) and are assumed to be 2ns for all inputs.
3. Measured with a load equivalent to 2 TTL(5V)/1 TTL(3.3V) loads and 100pF.
4. Operation within the t RCD(max) limit insures that tRAC(max) can be met. tRCD(max) is specified as a reference point
only. If tRCD
is greater than the specified tRCD (max) limit, then access time is controlled exclusively by tCAC.
5. Assumes that tRCD >= tRCD(max).
6. This parameter defines the time at which the output achieves the open circuit condition and is not referenced to VOH
or
VOL.
7. tWCS, tRWD, tCWD and tAWD
are non restrictive operating parameters. They are included in the data sheet as
electrical characteristics only. If t WCS >= t WCS(min), the cycle is an early write cycle and the data output will remain
high impedance for the duration of the cycle. If t CWD >= t CWD(min), t RWD >= t RWD(min) and tAWD >= tAWD(min),
then the cycle is a read-modify-write cycle and the data output will contain the data read from the selected address. If
neither of the above conditions is satisfied, the condition of the data out is indeterminate. Either tRCH
or tRRH
must be
satisfied for a read cycle.
8. These parameters are referenced to
CAS
falling edge in early write cycles and to
W
falling edge in
OE
controlled
Write Cycle and read-modify-write cycles.
9. Operation within the tRAD (max) limit insures that tRAD(max) can be met. tRAD(max) is specified as a reference point
only. If tRAD
is greater than the specified
tRA
D(max) limit, then access time is controlled by tAA .
10. These specifications are applied in the test mode.
11. In test mode read cycle, the value of tRAC, tAA, tCAC
is delayed by 2ns to 5ns for the specified values. These
Parameters should specified in test mode cycles by adding the above value to the specified value in this data sheet.
12. tASC>= 6ns, Assume t
T
= 2.0ns
13. If
RAS
goes high before
CAS
high going, the open circuit condition of the output is achieved by CAS high going.
If
CAS
goes high before
RAS
high going, the open circuit condition of the output is achieved by
RAS
high going.
14. If tRASS>= 100us, then
RAS
precharge time must use
t
RPS
instead of
t
RP
.
15. For RAS-only refresh and burst
CAS
-before-
RAS
refresh mode, 2048(2K) cycles of burst refresh must be executed
within 32ms before and after self refresh, in order to meet refresh specification..
16. For distributed
CAS
-before-
RAS
with 15.6us interval
CAS
-before-
RAS
refresh should be executed with in 15.6us
immediately before and after self refresh in order to meet refresh specification.
NT511740D5J
16MEG : x4
CMOS with Extended Data Out
REV 1.0 May. 2000 10
NANYA TECHNOLOGY CORP.
NAYNA TECHNOLOGY CORP. reserves the right to change products and specifications without notice.
TIMING WAVEFORM
Open
"H" or "L"
tASR
tCRP
tRAH
tRAS
tRP
tRC
tCRP
tRCD
tCAS
tRSH
tCSH
tCAH
tCEZ
tOEZ
tCLZ
tRAC
tCAC
tOEA
tREZ
tROH
tAA
tRCS
tRRH
tRCH
tRAD
tASC
tRAL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
DQ
OE
WE
Address
CAS
RAS
Row
Column
Read Cycle
Valid Data-out
Open
"H" or "L"
t
ASR
t
CRP
t
RAH
t
RAS
t
RP
t
RC
t
CRP
t
RCD
t
CAS
t
RSH
t
CSH
t
CAH
t
DS
t
DH
t
RWL
t
WP
t
WCS
t
RAD
t
ASC
t
RAL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
DQ
OE
WE
Address
CAS
RAS
Row
Column
Write Cycle(Early Write)
t
WCH
t
CWL
Valid data-in
NT511740D5J
16MEG : x4
CMOS with Extended Data Out
REV 1.0 May. 2000 11
NANYA TECHNOLOGY CORP.
NAYNA TECHNOLOGY CORP. reserves the right to change products and specifications without notice.
"H" or "L"
t
ASR
t
CRP
t
RAH
t
RAS
t
RWC
t
CRP
t
RCD
t
CAS
t
RSH
t
CSH
t
CAH
t
DH
t
CLZ
t
RAC
t
CAC
t
OEA
t
AA
t
RCS
t
WP
t
ASC
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
DQ
OE
WE
Address
CAS
RAS
Row
Column
Read Modify Write Cycle
t
DS
t
OEZ
t
OED
t
OEH
t
AWD
t
RWL
t
CWL
t
CWD
t
RWD
t
RAD
t
RP
Valid
Data-out
Valid
Data-in
"H" or "L"
t
ASR
t
CRP
t
RAH
t
RASP
t
RCD
t
CAS
t
CP
t
HPC
t
CAH
t
OEZ
t
CLZ
t
RAC
t
CAC
t
AA
t
ASC
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
DQ
OE
WE
Address
CAS
RAS
Row
Fast Page Mode Read Cycle (Part-1)
t
OEA
t
AA
t
CHO
t
RCS
t
RP
t
RRH
t
REZ
t
OEA
t
RHCP
t
CAS
t
CP
t
CAS
t
RAD
t
CAH
t
ASC
t
CAH
t
ASC
t
CSH
t
CPA
t
CAC
t
DOH
t
AA
t
CAC
t
OEZ
t
OEA
t
OEP
t
OCH
t
OEP
Column
Column
Column
Valid
Data-out
Valid
Data-out
Valid
Data-out
Valid
Data-out
NT511740D5J
16MEG : x4
CMOS with Extended Data Out
REV 1.0 May. 2000 12
NANYA TECHNOLOGY CORP.
NAYNA TECHNOLOGY CORP. reserves the right to change products and specifications without notice.
"H" or "L"
t
ASR
t
CRP
t
RAH
t
RASP
t
RCD
t
CAS
t
CP
t
HPC
t
CAH
t
CLZ
t
RAC
t
CAC
t
AA
t
ASC
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
DQ
OE
WE
Address
CAS
RAS
Row
Fast Page Mode Read Cycle(Part-2)
t
AA
t
RCS
t
RP
t
CEZ
t
OEA
t
RHCP
t
CAS
t
CP
t
CAS
t
RAD
t
CAH
t
ASC
t
CAH
t
ASC
t
CSH
t
CAC
t
AA
t
CAC
t
CRP
t
DO
H
t
WEZ
t
RCS
t
RCH
t
WPE
t
CPA
Column
Column
Column
Valid
Data-out
Valid
Data-out
Valid
Data-out
"H" or "L"
t
ASR
t
CRP
t
RAH
t
RASP
t
RCD
t
CAS
t
CP
t
HPC
t
CAH
t
ASC
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
DQ
OE
WE
Address
CAS
RAS
Row
Fast page Mode Write Cycle(Early Write)
t
WCS
t
RP
t
DH
t
CAS
t
CP
t
CAS
t
RAD
t
CAH
t
ASC
t
CAH
t
ASC
t
CSH
t
HPC
t
DS
t
DH
t
DS
t
DH
t
DS
t
WCH
t
WCS
t
WCH
t
WCS
t
WCH
t
RSH
Column
Column
Column
Valid
Data-in
Valid
Data-in
Valid
Data-in
NT511740D5J
16MEG : x4
CMOS with Extended Data Out
REV 1.0 May. 2000 13
NANYA TECHNOLOGY CORP.
NAYNA TECHNOLOGY CORP. reserves the right to change products and specifications without notice.
"H" or "L"
t
ASR
t
CRP
t
RAH
t
RASP
t
RCD
t
CWD
t
CP
t
CAH
t
ASC
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
DQ
OE
WE
Address
CAS
RAS
Row
Fast Page Mode Read Modify Write Cycle
t
RCS
t
CLZ
t
RAD
t
CAH
t
CWL
t
RWL
t
CPA
t
RAC
t
DH
t
OED
t
AWD
t
CWD
t
CPWD
t
RWD
t
HPRWC
t
ASC
t
CAC
t
OEA
t
OEZ
t
DS
t
WP
t
OEH
t
OEA
t
CLZ
t
CAC
t
OED
t
OEZ
t
DS
t
WP
t
OEH
t
DH
t
AWD
t
AA
t
AA
t
RCS
Valid
Data-in
Valid
Data-out
Valid
Data-out
Valid
Data-in
Column
Column
"H" or "L"
t
ASR
t
CRP
t
RAH
t
RAS
t
RP
t
RC
t
CEZ
Open
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
DQ
Address
CAS
RAS
Row
RAS-only Refresh Cycle
t
RPC
Note:WE,OE="H" or "L"
NT511740D5J
16MEG : x4
CMOS with Extended Data Out
REV 1.0 May. 2000 14
NANYA TECHNOLOGY CORP.
NAYNA TECHNOLOGY CORP. reserves the right to change products and specifications without notice.
"H" or "L"
t
CP
t
WR
P
t
RAS
t
RP
t
RC
t
CEZ
Open
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
DQ
CAS
RAS
CAS before RAS Refresh Cycle
t
RPC
WE
t
WRH
t
WRP
t
RPC
t
CSR
t
CHR
Note:OE,Address="H" or "L"
t
RP
Open
"H" or "L"
t
ASR
t
CRP
t
RAH
t
RAS
t
RP
t
RC
t
CHR
t
RCD
t
RSH
t
CAH
t
CEZ
t
OEZ
t
CLZ
t
RAC
t
CAC
t
OEA
t
ROH
t
AA
t
RCS
t
RRH
t
RAD
t
ASC
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
DQ
OE
WE
Address
CAS
RAS
Row
Column
Hidden Refresh Read
Cycle
t
RAS
t
RP
t
RC
t
REZ
t
RAL
Valid Data-out
NT511740D5J
16MEG : x4
CMOS with Extended Data Out
REV 1.0 May. 2000 15
NANYA TECHNOLOGY CORP.
NAYNA TECHNOLOGY CORP. reserves the right to change products and specifications without notice.
"H" or "L"
t
ASR
t
CRP
t
RAH
t
RAS
t
RP
t
RC
t
CHR
t
RCD
t
RSH
t
CAH
t
DS
t
DH
t
WCS
t
WP
t
RAD
t
ASC
t
RAL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
DQ
OE
WE
Address
CAS
RAS
Row
Column
Hidden Refresh Write
Cycle
t
RAS
t
RP
t
RC
t
WCH
t
RWL
Valid Data-in
NT511740D5J
16MEG : x4
CMOS with Extended Data Out
REV 1.0 May. 2000 16
NANYA TECHNOLOGY CORP.
NAYNA TECHNOLOGY CORP. reserves the right to change products and specifications without notice.
PACKAGE DIMENSION
24/26-PIN PLASTIC SOJ (300mil)
0.95 TPY
1.27
0.50
0.38
0.81 MAX
SEATING
0.635 MIN
6.98
6.48
3.75
3.25
2.63 TYP.
PIN #1 INDEX
17.27
17.01
7.75
7.49
8.60
8.34
0.32
0.17
NOTE : All dimensions in millimeters or typical where noted.
MAX
MIN
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