NT5SV16M4DT

NT5SV8M8DT
NT5SV4M16DT

64Mb Synchronous DRAM

REV 1.1

10/01

NANYA TECHNOLOGY CORP

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

Features

· High Performance:

· Single Pulsed RAS Interface
· Fully Synchronous to Positive Clock Edge
· Four Banks controlled by BS0/BS1 (Bank Select)

· Programmable CAS Latency: 2, 3
· Programmable Burst Length: 1, 2, 4, 8, Full page
· Programmable Wrap: Sequential or Interleave
· Multiple Burst Read with Single Write Option
· Automatic and Controlled Precharge Command
· Data Mask for Read/Write control (x4, x8)
· Dual Data Mask for byte control (x16)
· Auto Refresh (CBR) and Self Refresh
· Suspend Mode and Power Down Mode
· Standard Power operation
· 4096 refresh cycles/64ms
· Random Column Address every CK (1-N Rule)
· Single 3.3V

0.3V Power Supply

· LVTTL compatible
· Package:

54-pin 400 mil TSOP-Type II

Description

The NT5SV16M4DT, NT5SV8M8DT, and NT5SV4M16DT
are four-bank Synchronous DRAMs organized as 4Mbit x 4
I/O x 4 Bank, 2Mbit x 8 I/O x 4 Bank, and 1Mbit x 16 I/O x 4
Bank, respectively. These synchronous devices achieve
high-speed data transfer rates of up to 200MHz by employing
a pipeline chip architecture that synchronizes the output data
to a system clock. The chip is fabricated with NTC's
advanced 64Mbit single transistor CMOS DRAM process
technology.

The device is designed to comply with all JEDEC standards
set for synchronous DRAM products, both electrically and
mechanically. All of the control, address, and data input/out-
put (I/O or DQ) circuits are synchronized with the positive
edge of an externally supplied clock.

RAS, CAS, WE, and CS are pulsed signals which are exam-
ined at the positive edge of each externally applied clock
(CK). Internal chip operating modes are defined by combina-
tions of these signals and a command decoder initiates the
necessary timings for each operation. A fourteen bit address
bus accepts address data in the conventional RAS/CAS mul-

tiplexing style. Twelve row addresses (A0-A11) and two bank
select addresses (BS0, BS1) are strobed with RAS. Eleven
column addresses (A0-A9) plus bank select addresses and
A10 are strobed with CAS. Column address A9 is dropped on
the x8 device, and column addresses A8 and A9 are dropped
on the x16 device.

Prior to any access operation, the CAS latency, burst length,
and burst sequence must be programmed into the device by
address inputs A0-A11, BS0, BS1 during a mode register set
cycle. In addition, it is possible to program a multiple burst
sequence with single write cycle for write through cache oper-
ation.

Operating the four memory banks in an interleave fashion
allows random access operation to occur at a higher rate
than is possible with standard DRAMs. A sequential and gap-
less data rate of up to 200MHz is possible depending on
burst length, CAS latency, and speed grade of the device.
Simultaneous operation of both decks of a stacked device is
allowed, depending on the operation being done. Auto
Refresh (CBR) and Self Refresh operation are supported.

-6K

-7K

-7

Units

Clock

Frequency

166

133

143

133

143

MHz

Clock Cycle

7.5

CL CAS Latency CL=3 CL=2 CL=3 CL=2

CL=3

CKs

Clock Access

Time

---

Clock Access

Time

5.4

1. Terminated load. See AC Characteristics on page 16.
2. Unterminated load. See AC Characteristics on page 16.

NT5SV16M4DT

NT5SV8M8DT
NT5SV4M16DT

64Mb Synchronous DRAM

REV 1.1

10/01

NANYA TECHNOLOGY CORP

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

Pin Assignments for Planar Components

(Top View)

54-pin Plastic TSOP(II) 400 mil

4Mbit x 4 I/O x 4 Bank

NT5SV16M4DT

1
2
3
4
5
6

9
10
11
12
13
14

7
8

15
16
17
18
19
20
21
22

54
53
52
51
50
49

46
45
44
43
42
41

48
47

40
39
38
37
36
35
34
33

DDQ

DQ0

SSQ

DDQ

DQ1

SSQ

NC
NC

CAS
RAS

BS0
BS1

NC
V

SSQ

NC
DQ3
V

DDQ

SSQ

NC
DQ2
V

DDQ

NC
V

NC
NC

NC
DQM
CK
CKE
NC
A11
A9

23
24
25

32
31
30

A10/AP

A0
A1
A2

A8
A7
A6
A5

26
27

29
28

A4
V

DQ0

DDQ

DQ1

SSQ

DDQ

DQ3

SSQ

DQ2

CAS
RAS

BS0
BS1

A10/AP

A0
A1
A2
A3

DQ7
V

SSQ

NC
DQ6
V

DDQ

SSQ

NC
DQ4
V

DDQ

NC
V

NC
DQ5

NC
DQM
CK
CKE
NC
A11
A9
A8
A7
A6
A5
A4
V

DQ0

DDQ

DQ1
DQ2

SSQ

DDQ

DQ5
DQ6

SSQ

DQ7

DQ3
DQ4

LDQM

CAS
RAS

BS0
BS1

A10/AP

A0
A1
A2
A3

DQ15
V

SSQ

DQ14
DQ13
V

DDQ

SSQ

DQ10
DQ9
V

DDQ

DQ8
V

DQ12
DQ11

NC
UDQM
CK
CKE
NC
A11
A9
A8
A7
A6
A5
A4
V

1Mbit x 16 I/O x 4 Bank

NT5SV4M16DT

2Mbit x 8 I/O x 4 Bank

NT5SV8M8DT

NT5SV16M4DT

NT5SV8M8DT
NT5SV4M16DT

64Mb Synchronous DRAM

REV 1.1

10/01

NANYA TECHNOLOGY CORP

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

Pin Description

Clock Input

DQ0-DQ15

Data Input/Output

CKE

Clock Enable

DQM, LDQM, UDQM

Data Mask

Chip Select

Power (+3.3V)

RAS

Row Address Strobe

Ground

CAS

Column Address Strobe

DDQ

Power for DQs (+3.3V)

Write Enable

SSQ

Ground for DQs

BS1, BS0

Bank Select

No Connection

A0 - A11

Address Inputs

Input/Output Functional Description

Symbol

Type

Polarity

Function

CLK

Input

Positive

Edge

The system clock input. All of the SDRAM inputs are sampled on the rising edge of the clock.

CKE

Input

Active High

Activates the CLK signal when high and deactivates the CLK signal when low. By deactivating the
clock, CKE low initiates the Power Down mode, Suspend mode, or the Self Refresh mode.

Input

Active Low

CS enables the command decoder when low and disables the command decoder when high. When the
command decoder is disabled, new commands are ignored but previous operations continue.

RAS, CAS,

Input

Active Low

When sampled at the positive rising edge of the clock, CAS, RAS, and WE define the operation to be
executed by the SDRAM.

BS0, BS1

Input

Selects which bank is to be active.

A0 - A11

Input

During a Bank Activate command cycle, A0-A11 defines the row address (RA0-RA11) when sampled at
the rising clock edge.
During a Read or Write command cycle, A0-A9 defines the column address (CA0-CA9) when sampled
at the rising clock edge.
A10 is used to invoke auto-precharge operation at the end of the burst read or write cycle. If A10 is
high, auto-precharge is selected and BS0, BS1 defines the bank to be precharged. If A10 is low, auto-
precharge is disabled.
During a Precharge command cycle, A10 is used in conjunction with BS0, BS1 to control which bank(s)
to precharge. If A10 is high, all banks will be precharged regardless of the state of BS. If A10 is low,
then BS0 and BS1 are used to define which bank to precharge.

DQ0 - DQ15

Input-

Output

Data Input/Output pins operate in the same manner as on conventional DRAMs.

DQM

LDQM

UDQM

Input

Active High

The Data Input/Output mask places the DQ buffers in a high impedance state when sampled high. In
x16 products, LDQM and UDQM control the lower and upper byte I/O buffers, respectively. In Read
mode, DQM has a latency of two clock cycles and controls the output buffers like an output enable.
DQM low turns the output buffers on and DQM high turns them off. In Write mode, DQM has a latency
of zero and operates as a word mask by allowing input data to be written if it is low but blocks the write
operation if DQM is high.

, V

Supply

Power and ground for the input buffers and the core logic.

DDQ

SSQ

Supply

Isolated power supply and ground for the output buffers to provide improved noise immunity.

NT5SV16M4DT

NT5SV8M8DT
NT5SV4M16DT

64Mb Synchronous DRAM

REV 1.1

10/01

NANYA TECHNOLOGY CORP

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

Ordering Information

Organization

Part Number

Speed Grade

Power

Supply

Package

Clock Frequency@CAS Latency

Note

16M x 4

NT5SV16M4DT-6K

166MHz@CL3

133MHz@CL2

PC133 , PC100

3.3 V

400mil 54-PIN

TSOP II

NT5SV16M4DT-7K

143MHz@CL3

133MHz@CL2

NT5SV16M4DT-7

143MHz@CL3

100MHz@CL2

8M x 8

NT5SV8M8DT-6K

166MHz@CL3

133MHz@CL2

NT5SV8M8DT-7K

143MHz@CL3

133MHz@CL2

NT5SV8M8DT-7

143MHz@CL3

100MHz@CL2

4M x 16

NT5SV4M16DT

166MHz@CL3

133MHz@CL2

NT5SV4M16DT-7K

143MHz@CL3

133MHz@CL2

NT5SV4M16DT-7

143MHz@CL3

100MHz@CL2

NT5SV16M4DT

NT5SV8M8DT
NT5SV4M16DT

64Mb Synchronous DRAM

REV 1.1

10/01

NANYA TECHNOLOGY CORP

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

Block Diagram

t
a

I
n
p

u
t
/
O

u
t
p
u
t

B

u
f
f
e
r
s

CKE Buffer

CLK Buffer

CKE

CLK

RAS

CAS

DQM

o
m

a
n
d

D

c
o
d

e
r

i
s
t
e
r

o
u

t
e

l
u

r
e

s
s

n
t
e

f
r
e

s
h

A1
A2
A3
A4
A5
A6
A7

A10

A8
A9

A11

Sense Amplifiers

Memory Bank 1

Cell Array

o
w

e
c
o
d
e

d
d

r
e

s
s

B

u
f
f
e
r
s

(
1
4
)

Column Decoder

Sense Amplifiers

Memory Bank 3

Cell Array

c
o

d
e

Column Decoder

Sense Amplifiers

Memory Bank 0

Cell Array

e
c
o
d
e
r

Column Decoder

Sense Amplifiers

Memory Bank 2

Cell Array

c
o

Column Decoder

a
t
a

C

o
n
t
r
o
l

C

i
r
c
u
i
t
r
y

BS1

BS0

o
n
t
r
o
l

S

i
g
n
a
l

n
e
r
a
t
o
r

Cell Array, per bank, for 4Mb x 4 DQ: 4096 Row x 1024 Col x 4 DQ (DQ0-DQ3).

Cell Array, per bank, for 2Mb x 8 DQ: 4096 Row x 512 Col x 8 DQ (DQ0-DQ7)

Cell Array, per bank, for 1Mb x 16 DQ: 4096 Row x 256 Col x 16 DQ (DQ0-DQ15).

NT5SV16M4DT

NT5SV8M8DT
NT5SV4M16DT

64Mb Synchronous DRAM

REV 1.1

10/01

NANYA TECHNOLOGY CORP

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

Mode Register Operation (Address Input For Mode Set)

A11

A10

Address

Burst Length

CAS Latency

Mode

CAS Latency

Latency

Reserved

Burst Length

Length

Sequential Interleave

Reserved Reserved

Full Page Reserved

Burst Type

Type

Sequential

Interleave

Operation Mode

M13 M12 M11 M10 M9 M8 M7

Mode

Normal

Multiple Burst with

Single Write

Operation Mode

BS1

Bus (Ax)

BS0

NT5SV16M4DT

NT5SV8M8DT
NT5SV4M16DT

64Mb Synchronous DRAM

REV 1.1

10/01

NANYA TECHNOLOGY CORP

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

Burst Mode Operation

Burst mode operation is used to provide a constant flow of data to memory locations (write cycle), or from memory locations
(read cycle). There are three parameters that define how the burst mode will operate. These parameters include burst
sequence, burst length, and operation mode. The burst sequence and burst length are programmable, and are determined by
address bits A0 - A3 during the Mode Register Set command. Operation mode is also programmable and is set by address bits
A7 - A11, BS0, and BS1.

The burst type is used to define the order in which the burst data will be delivered or stored to the SDRAM. Two types of burst
sequences are supported, sequential and interleaved. See the table below.

The burst length controls the number of bits that will be output after a Read Command, or the number of bits to be input after a
Write Command. The burst length can be programmed to have values of 1, 2, 4, 8 or full page(actual page length is dependent
on organization: x4, x8, or x16).Full page burst operation is only posible using the sequential burst type.

Burst operation mode can be normal operation or multiple burst with single write operation. Normal operation implies that the
device will perform burst operations on both read and write cycles until the desired burst length is satisfied. Multiple burst with
single write operation was added to support Write Through Cache operation. Here, the programmed burst length only applies to
read cycles. All write cycles are single write operations when this mode is selected.

Note: Page length is a function of I/O organization and column addressing.

x4 organization (CA0-CA9); Page Length = 1024 bits

x8 organization (CA0-CA8); Page Length = 512 bits

x16 organization (CA0-CA7); Page Length = 256 bits

Burst Length and Sequence

Burst Length

Starting Address (A2 A1 A0)

Sequential Addressing (decimal)

Interleave Addressing (decimal)

x x 0

0, 1

x x 1

1, 0

x 0 0

0, 1, 2, 3

x 0 1

1, 2, 3, 0

1, 0, 3, 2

x 1 0

2, 3, 0, 1

x 1 1

3, 0, 1, 2

3, 2, 1, 0

0 0 0

0, 1, 2, 3, 4, 5, 6, 7

0 0 1

1, 2, 3, 4, 5, 6, 7, 0

1, 0, 3, 2, 5, 4, 7, 6

0 1 0

2, 3, 4, 5, 6, 7, 0, 1

2, 3, 0, 1, 6, 7, 4, 5

0 1 1

3, 4, 5, 6, 7, 0, 1, 2

3, 2, 1, 0, 7, 6, 5, 4

1 0 0

4, 5, 6, 7, 0, 1, 2, 3

1 0 1

5, 6, 7, 0, 1, 2, 3, 4

5, 4, 7, 6, 1, 0, 3, 2

1 1 0

6, 7, 0, 1, 2, 3, 4, 5

6, 7, 4, 5, 2, 3, 0, 1

1 1 1

7, 0, 1, 2, 3, 4, 5, 6

7, 6, 5, 4, 3, 2, 1, 0

Full Page(Note)

n n n

Cn, Cn+1, Cn+2, .....

Not Supported

NT5SV16M4DT

NT5SV8M8DT
NT5SV4M16DT

64Mb Synchronous DRAM

REV 1.1

10/01

NANYA TECHNOLOGY CORP

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

Command Truth Table

(See note 1)

Function

Device State

CKE

RAS

CAS

DQM

BS0,

BS1

A10

A11,
A11,

A9-A0

Notes

Cycle

Current

Cycle

Mode Register Set

Idle

OP Code

Auto (CBR) Refresh

Idle

Entry Self Refresh

Idle

Exit Self Refresh

Idle (Self-
Refresh)

Single Bank Precharge

See Current
State Table

Precharge all Banks

See Current
State Table

Bank Activate

Idle

Row Address

Write

Active

Column

Write with Auto-Precharge

Active

Column

Read

Active

Column

Read with Auto-Precharge

Active

Column

Burst Termination

Active

3,8

No Operation

Any

Device Deselect

Any

Clock Suspend Mode Entry Active

Clock Suspend Mode Exit

Active

Data Write/Output Enable

Active

Data Mask/Output Disable

Active

Power Down Mode Entry

Idle/Active

6, 7

Power Down Mode Exit

Any (Power
Down)

6, 7

1. All of the SDRAM operations are defined by states of CS, WE, RAS, CAS, and DQM at the positive rising edge of the clock.Operation of

both decks of a stacked device at the same time is allowed, depending on the operation being performed on the other deck. Refer to the
Current State Truth Table.

2. Bank Select (BS0, BS1): BS0, BS1 = 0,0 selects bank 0; BS0, BS1 = 1,0 selects bank 1; BS0, BS1 = 0,1 selects bank 2; BS0, BS1 = 1,1

selects bank 3.

3. During a Burst Write cycle there is a zero clock delay; for a Burst Read cycle the delay is equal to the CAS latency.
4. During normal access mode, CKE is held high and CK is enabled. When it is low, it freezes the internal clock and extends data Read and

Write operations. One clock delay is required for mode entry and exit.

5. The DQM has two functions for the data DQ Read and Write operations. During a Read cycle, when DQM goes high at a clock timing the

data outputs are disabled and become high impedance after a two-clock delay. DQM also provides a data mask function for Write cycles.
When it activates, the Write operation at the clock is prohibited (zero clock latency).

6. All banks must be precharged before entering the Power Down Mode. (If this command is issued during a burst operation, the device

state will be Clock Suspend Mode.) The Power Down Mode does not perform any refresh operations; therefore the device can't remain in
this mode longer than the Refresh period (t

REF

) of the device. One clock delay is required for mode entry and exit.

7. A No Operation or Device Deselect Command is required on the next clock edge following CKE going high.
8. Device state is full page burst operation. Use of this command to terminate other burst length operations is illegal.

NT5SV16M4DT

NT5SV8M8DT
NT5SV4M16DT

64Mb Synchronous DRAM

REV 1.1

10/01

NANYA TECHNOLOGY CORP

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

Clock Enable (CKE) Truth Table

Current State

CKE

Command

Action

Notes

Cycle

Current

Cycle

RAS

CAS

BS0,

BS1

A11 - A0

Self Refresh

INVALID

Exit Self Refresh with Device Deselect

Exit Self Refresh with No Operation

ILLEGAL

Maintain Self Refresh

Power Down

INVALID

Power Down mode exit, all banks idle

ILLEGAL

Maintain Power Down Mode

All Banks Idle

Refer to the Idle State section of the
Current State Truth Table

CBR Refresh

OP Code

Mode Register Set

Refer to the Idle State section of the
Current State Truth Table

Entry Self Refresh

OP Code

Mode Register Set

Power Down

Any State

other than

listed above

Refer to operations in the Current State
Truth Table

Begin Clock Suspend next cycle

Exit Clock Suspend next cycle

Maintain Clock Suspend

1. For the given Current State CKE must be low in the previous cycle.
2. When CKE has a low to high transition, the clock and other inputs are re-enabled asynchronously. The minimum setup time for CKE

CES

) must be satisfied. When exiting power down mode, a NOP command (or Device Deselect Command) is required on the first rising

clock after CKE goes high (see page 26).

3. The address inputs depend on the command that is issued. See the Idle State section of the Current State Truth Table for more informa-

tion.

4. The Precharge Power Down Mode, the Self Refresh Mode, and the Mode Register Set can only be entered from the all banks idle state.
5. Must be a legal command as defined in the Current State Truth Table.

NT5SV16M4DT

NT5SV8M8DT
NT5SV4M16DT

64Mb Synchronous DRAM

REV 1.1

10/01

NANYA TECHNOLOGY CORP

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

Current State Truth Table

(Part 1 of 3)(See note 1)

Current State

Command

Action

Notes

CS RAS CAS WE BS0,BS1

A11 - A0

Description

Idle

OP Code

Mode Register Set

Set the Mode Register

Auto or Self Refresh

Start Auto or Self Refresh

2, 3

Precharge

No Operation

Row Address Bank Activate

Activate the specified bank and row

Column

Write w/o Precharge

ILLEGAL

Column

Read w/o Precharge

ILLEGAL

Burst Termination

No Operation

Device Deselect

No Operation or Power Down

Row Active

OP Code

Mode Register Set

ILLEGAL

Auto or Self Refresh

ILLEGAL

Precharge

Row Address Bank Activate

ILLEGAL

Column

Write

Start Write; Determine if Auto Precharge

7, 8

Column

Read

Start Read; Determine if Auto Precharge

7, 8

Burst Termination

No Operation

Device Deselect

No Operation

Read

OP Code

Mode Register Set

ILLEGAL

Auto or Self Refresh

ILLEGAL

Precharge

Terminate Burst; Start the Precharge

Row Address Bank Activate

ILLEGAL

Column

Write

Terminate Burst; Start the Write cycle

8, 9

Column

Read

Terminate Burst; Start a new Read cycle

8, 9

Burst Termination

Terminate the Burst

No Operation

Continue the Burst

Device Deselect

Continue the Burst

Write

OP Code

Mode Register Set

ILLEGAL

Auto or Self Refresh

ILLEGAL

Precharge

Terminate Burst; Start the Precharge

Row Address Bank Activate

ILLEGAL

Column

Write

Terminate Burst; Start a new Write cycle

8, 9

Column

Read

Terminate Burst; Start the Read cycle

8, 9

Burst Termination

Terminate the Burst

No Operation

Continue the Burst

Device Deselect

Continue the Burst

1. CKE is assumed to be active (high) in the previous cycle for all entries. The Current State is the state of the bank that the Command is

being applied to.

2. All Banks must be idle; otherwise, it is an illegal action.
3. If CKE is active (high) the SDRAM will start the Auto (CBR) Refresh operation, if CKE is inactive (low) than the Self Refresh mode is

entered.

4. The Current State refers to only one of the banks. If BS selects this bank then the action is illegal. If BS selects the bank not being refer-

enced by the Current State then the action may be legal depending on the state of that bank.

5. If CKE is inactive (low) then the Power Down mode is entered; otherwise there is a No Operation.
6. The minimum and maximum Active time (t

RAS

) must be satisfied.

7. The RAS to CAS Delay (t

RCD

) must occur before the command is given.

8. Column address A10 is used to determine if the Auto Precharge function is activated.
9. The command must satisfy any bus contention, bus turn around, and/or write recovery requirements.

10. The command is illegal if the minimum bank to bank delay time (t

RRD

) is not satisfied.

NT5SV16M4DT

NT5SV8M8DT
NT5SV4M16DT

64Mb Synchronous DRAM

REV 1.1

10/01

NANYA TECHNOLOGY CORP

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

Read with

Auto Pre-

charge

OP Code

Mode Register Set

ILLEGAL

Auto or Self Refresh

ILLEGAL

Precharge

ILLEGAL

Row Address Bank Activate

ILLEGAL

Column

Write

ILLEGAL

Column

Read

ILLEGAL

Burst Termination

ILLEGAL

No Operation

Continue the Burst

Device Deselect

Continue the Burst

Write with Auto

Precharge

OP Code

Mode Register Set

ILLEGAL

Auto or Self Refresh

ILLEGAL

Precharge

ILLEGAL

Row Address Bank Activate

ILLEGAL

Column

Write

ILLEGAL

Column

Read

ILLEGAL

Burst Termination

ILLEGAL

No Operation

Continue the Burst

Device Deselect

Continue the Burst

Precharging

OP Code

Mode Register Set

ILLEGAL

Auto or Self Refresh

ILLEGAL

Precharge

No Operation; Bank(s) idle after t

Row Address Bank Activate

ILLEGAL

Column

Write

ILLEGAL

Column

Read

ILLEGAL

Burst Termination

No Operation; Bank(s) idle after t

No Operation

No Operation; Bank(s) idle after t

Device Deselect

No Operation; Bank(s) idle after t

Row

Activating

OP Code

Mode Register Set

ILLEGAL

Auto or Self Refresh

ILLEGAL

Precharge

ILLEGAL

Row Address Bank Activate

ILLEGAL

4, 10

Column

Write

ILLEGAL

Column

Read

ILLEGAL

Burst Termination

No Operation; Row Active after t

RCD

No Operation

No Operation; Row Active after t

RCD

Device Deselect

No Operation; Row Active after t

RCD

Current State Truth Table

(Part 2 of 3)(See note 1)

Current State

Command

Action

Notes

CS RAS CAS WE BS0,BS1

A11 - A0

Description

1. CKE is assumed to be active (high) in the previous cycle for all entries. The Current State is the state of the bank that the Command is

being applied to.

2. All Banks must be idle; otherwise, it is an illegal action.
3. If CKE is active (high) the SDRAM will start the Auto (CBR) Refresh operation, if CKE is inactive (low) than the Self Refresh mode is

entered.

4. The Current State refers to only one of the banks. If BS selects this bank then the action is illegal. If BS selects the bank not being refer-

enced by the Current State then the action may be legal depending on the state of that bank.

5. If CKE is inactive (low) then the Power Down mode is entered; otherwise there is a No Operation.
6. The minimum and maximum Active time (t

RAS

) must be satisfied.

7. The RAS to CAS Delay (t

RCD

) must occur before the command is given.

8. Column address A10 is used to determine if the Auto Precharge function is activated.
9. The command must satisfy any bus contention, bus turn around, and/or write recovery requirements.

10. The command is illegal if the minimum bank to bank delay time (t

RRD

) is not satisfied.

NT5SV16M4DT

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NT5SV4M16DT

64Mb Synchronous DRAM

REV 1.1

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Write

Recovering

OP Code

Mode Register Set

ILLEGAL

Auto or Self Refresh

ILLEGAL

Precharge

ILLEGAL

Row Address Bank Activate

ILLEGAL

Column

Write

Start Write; Determine if Auto Precharge

Column

Read

Start Read; Determine if Auto Precharge

Burst Termination

No Operation; Row Active after t

DPL

No Operation

No Operation; Row Active after t

DPL

Device Deselect

No Operation; Row Active after t

DPL

Write

Recovering

with

Auto Pre-

charge

OP Code

Mode Register Set

ILLEGAL

Auto or Self Refresh

ILLEGAL

Precharge

ILLEGAL

Row Address Bank Activate

ILLEGAL

Column

Write

ILLEGAL

4, 9

Column

Read

ILLEGAL

4, 9

Burst Termination

No Operation; Precharge after t

DPL

No Operation

No Operation; Precharge after t

DPL

Device Deselect

No Operation; Precharge after t

DPL

Refreshing

OP Code

Mode Register Set

ILLEGAL

Auto or Self Refresh

ILLEGAL

Precharge

ILLEGAL

Row Address Bank Activate

ILLEGAL

Column

Write

ILLEGAL

Column

Read

ILLEGAL

Burst Termination

No Operation; Idle after t

No Operation

No Operation; Idle after t

Device Deselect

No Operation; Idle after t

Mode

Accessing

OP Code

Mode Register Set

ILLEGAL

Auto or Self Refresh

ILLEGAL

Precharge

ILLEGAL

Row Address Bank Activate

ILLEGAL

Column

Write

ILLEGAL

Column

Read

ILLEGAL

Burst Termination

ILLEGAL

No Operation

No Operation; Idle after two clock cycles

Device Deselect

No Operation; Idle after two clock cycles

Current State Truth Table

(Part 3 of 3)(See note 1)

Current State

Command

Action

Notes

CS RAS CAS WE BS0,BS1

A11 - A0

Description

1. CKE is assumed to be active (high) in the previous cycle for all entries. The Current State is the state of the bank that the Command is

being applied to.

2. All Banks must be idle; otherwise, it is an illegal action.
3. If CKE is active (high) the SDRAM will start the Auto (CBR) Refresh operation, if CKE is inactive (low) than the Self Refresh mode is

entered.

4. The Current State refers to only one of the banks. If BS selects this bank then the action is illegal. If BS selects the bank not being refer-

enced by the Current State then the action may be legal depending on the state of that bank.

5. If CKE is inactive (low) then the Power Down mode is entered; otherwise there is a No Operation.
6. The minimum and maximum Active time (t

RAS

) must be satisfied.

7. The RAS to CAS Delay (t

RCD

) must occur before the command is given.

8. Column address A10 is used to determine if the Auto Precharge function is activated.
9. The command must satisfy any bus contention, bus turn around, and/or write recovery requirements.

10. The command is illegal if the minimum bank to bank delay time (t

RRD

) is not satisfied.

NT5SV16M4DT

NT5SV8M8DT
NT5SV4M16DT

64Mb Synchronous DRAM

REV 1.1

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NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

Absolute Maximum Ratings

Symbol

Parameter

Rating

Units

Notes

Power Supply Voltage

-0.3 to +4.6

DDQ

Power Supply Voltage for Output

-0.3 to +4.6

Input Voltage

-0.3 to V

+0.3

OUT

Output Voltage

-0.3 to V

+0.3

Operating Temperature (ambient)

0 to +70

STG

Storage Temperature

-55 to +125

Power Dissipation

1.0

OUT

Short Circuit Output Current

1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating

only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this spec-
ification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

Recommended DC Operating Conditions

C to 70

Symbol

Parameter

Rating

Units

Notes

Min.

Typ.

Max.

Supply Voltage

3.0

3.3

3.6

DDQ

Supply Voltage for Output

3.0

3.3

3.6

Input High Voltage

2.0

+ 0.3

1, 2

Input Low Voltage

-0.3

0.8

1, 3

1. All voltages referenced to V

and V

SSQ

2. V

(max) = V

+ 1.2V for pulse width

5ns.

3. V

(min) = V

- 1.2V for pulse width

5ns.

Capacitance

= 25

C, f = 1MHz, V

= 3.3V

0.3V)

Symbol

Parameter

Min.

Typ

Max.

Units

Input Capacitance (A0-A11, BS0, BS1, CS, RAS, CAS, WE, CKE, DQM)

2.5

3.0

3.8

Input Capacitance (CK)

2.5

2.8

3.5

Output Capacitance (DQ0 - DQ15)

4.0

4.5

6.5

NT5SV16M4DT

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NT5SV4M16DT

64Mb Synchronous DRAM

REV 1.1

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DC Electrical Characteristics

= 0 to +70

C, V

= 3.3V

0.3V)

Symbol

Parameter

Min.

Max.

Units

I(L)

Input Leakage Current, any input
(0.0V

), All Other Pins Not Under Test = 0V

-1

O(L)

Output Leakage Current
(D

OUT

is disabled, 0.0V

OUT

DDQ

)

-1

Output Level (LVTTL)
Output "H" Level Voltage (

IOUT

= -2.0mA)

2.4

Output Level (LVTTL)
Output "L" Level Voltage (I

OUT

= +2.0mA)

0.4

DC Output Load Circuit

Output

1200

50pF

3.3 V

870

(DC) = 2.4V, I

= -2mA

(DC) = 0.4V, I

= 2mA

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NT5SV4M16DT

64Mb Synchronous DRAM

REV 1.1

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Operating, Standby, and Refresh Currents

= 0 to +70

C, V

= 3.3V

0.3V)

Parameter

Symbol

Test Condition

-6K

-7K

-7

Units

Notes

(6ns)

(7ns)

Operating Current

CC1

1 bank operation
t

= t

(min), t

= min

Active-Precharge command cycling
without burst operation

1, 2, 3

Precharge Standby Current
in Power Down Mode

CC2P

CKE

(max), t

= min,

CS = V

(min)

CC2PS

CKE

(max), t

= Infinity,

CS = V

(min)

Precharge Standby Current
in Non-Power Down Mode

CC2N

CKE

(min), t

= min,

CS = V

(min)

1, 5

CC2NS

CKE

(min), t

= Infinity,

1, 7

No Operating Current
(Active state: 4 bank)

CC3N

CKE

(min), t

= min,

CS = V

(min)

1, 5

CC3P

CKE

(max), t

= min,

1, 6

Operating Current (Burst
Mode)

CC4

= min,

Read/ Write command cycling,
Multiple banks active, gapless data,
BL = 4

1, 3, 4

Auto (CBR) Refresh Current

CC5

= min, t

= t

(min)

CBR command cycling

120

110

Self Refresh Current

CC6

CKE

0.2V

1. Currents given are valid for a single device. The total current for a stacked device depends on the operation being performed

on the other deck.

2. These parameters depend on the cycle rate and are measured with the cycle determined by the minimum value of t

and t

Input signals are changed up to three times during t

(min).

3. The specified values are obtained with the output open.
4. Input signals are changed once during t

(min).

5. Input signals are changed once during three clock cycles.
6. Active Standby Current will be higher if Clock Suspend is entered during a burst read cycle (add 1mA per DQ).
7. Input signals are stable.

NT5SV16M4DT

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NT5SV4M16DT

64Mb Synchronous DRAM

REV 1.1

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AC Characteristics

= 0 to +70

C, V

= 3.3V

0.3V)

1. An initial pause of 200

s, with DQM and CKE held high, is required after power-up. A Precharge All Banks command must

be given followed by a minimum of two Auto (CBR) Refresh cycles before or after the Mode Register Set operation.

2. The Transition time is measured between V

and V

(or between V

and V

)

3. In addition to meeting the transition rate specification, the clock and CKE must transit between V

and V

(or between V

and V

) in a monotonic manner.

4. Load Circuit A: AC timing tests have V

= 0.4 V and V

= 2.4 V with the timing referenced to the 1.40V crossover point

5. Load Circuit A: AC measurements assume t

= 1.0ns.

6. Load Circuit B: AC timing tests have V

= 0.8 V and V

= 2.0 V with the timing referenced to the 1.40V crossover point

7. Load Circuit B: AC measurements assume t

= 1.2ns.

AC Characteristics Diagrams

Output

Input

Clock

SETUP

HOLD

1.4V

Vtt = 1.4V

Output

50pF

= 50

AC Output Load Circuit (A)

CKH

CKL

Output

50pF

= 50

AC Output Load Circuit (B)

NT5SV16M4DT

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NT5SV4M16DT

64Mb Synchronous DRAM

REV 1.1

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Clock and Clock Enable Parameters

Symbol

Parameter

-6K

-7K

-7

Units

Notes

Min.

Max.

Min.

Max.

Min.

Max.

CK3

Clock Cycle Time, CAS Latency = 3

1000

CK2

Clock Cycle Time, CAS Latency = 2

7.5

1000

7.5

1000

AC3 (A)

Clock Access Time, CAS Latency = 3

AC2 (A)

Clock Access Time, CAS Latency = 2

AC3 (B)

Clock Access Time, CAS Latency = 3

5.4

AC2 (B)

Clock Access Time, CAS Latency = 2

5.4

CKH

Clock High Pulse Width

2.5

CKL

Clock Low Pulse Width

2.5

CES

Clock Enable Set-up Time

1.5

CEH

Clock Enable Hold Time

0.8

Power down mode Entry Time

7.5

Transition Time (Rise and Fall)

0.5

1. Access time is measured at 1.4V. See AC Characteristics: notes 1, 2, 3, 4, 5 and load circuit A.
2. Access time is measured at 1.4V. See AC Characteristics: notes 1, 2, 3, 6, 7 and load circuit B.

Common Parameters

Symbol

Parameter

-6K

-7K

-7

Units

Notes

Min.

Max.

Min.

Max.

Min.

Max.

Command Setup Time

1.5

Command Hold Time

0.8

Address and Bank Select Set-up Time

1.5

Address and Bank Select Hold Time

0.8

RCD

RAS to CAS Delay

Bank Cycle Time

RAS

Active Command Period

100K

Precharge Time

RRD

Bank to Bank Delay Time

1. These parameters account for the number of clock cycle and depend on the operating frequency of the clock, as follows:

the number of clock cycles = specified value of timing / clock period (count fractions as a whole number).

Mode Register Set Cycle

Symbol

Parameter

-6K

-7K

-7

Units

Min.

Max.

Min.

Max.

Min.

Max.

RSC

Mode Register Set Cycle Time

NT5SV16M4DT

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NT5SV4M16DT

64Mb Synchronous DRAM

REV 1.1

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Read Cycle

Symbol

Parameter

-6K

-7K

-7

Units

Notes

Min.

Max.

Min.

Max.

Min.

Max.

Data Out Hold Time

2, 4

Data Out to Low Impedance Time

HZ3

Data Out to High Impedance Time

2.7

5.4

2.7

5.4

2.7

5.4

HZ2

Data Out to High Impedance Time

2.7

5.4

2.7

5.4

DQZ

DQM Data Out Disable Latency

1. AC Output Load Circuit A.
2. AC Output Load Circuit B.
3. Referenced to the time at which the output achieves the open circuit condition, not to output voltage levels.
4. Data Out Hold Time with no load must meet 1.8ns (-5K, -7K, -75B).

Refresh Cycle

Symbol

Parameter

-6K

-7K

-7

Units

Notes

Min.

Max.

Min.

Max.

Min.

Max.

REF

Refresh Period

SREX

Self Refresh Exit Time

1. 4096 auto refresh cycles.

Write Cycle

Symbol

Parameter

-6K

-7K

-7

Units

Min.

Max.

Min.

Max.

Min.

Max.

Data In Set-up Time

1.5

Data In Hold Time

0.8

DPL

Data input to Precharge

Write Recovery Time

DAL3

Data In to Active Delay
CAS Latency = 3

DAL2

Data In to Active Delay
CAS Latency = 2

DQW

DQM Write Mask Latency

NT5SV16M4DT

NT5SV8M8DT
NT5SV4M16DT

64Mb Synchronous DRAM

REV 1.1

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NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

Clock Frequency and Latency

Symbol

Parameter

-6K

-7K

-7

Units

Clock Frequency

166

133

143

133

143

100

MHz

Clock Cycle Time

7.5

CAS Latency

Precharge Time

RCD

RAS to CAS Delay

Bank Cycle Time

RAS

Minimum Bank Active Time

DPL

Data In to Precharge

DAL

Data In to Active/Refresh

RRD

Bank to Bank Delay Time

Write Latency

DQW

DQM Write Mask Latency

DQZ

DQM Data Disable Latency

CSL

Clock Suspend Latency

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