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I-Cube, Inc.
[Rev. 1.6] 2/20/01
1
OCX160 Crosspoint Switch
Preliminary Data Sheet
Features
Description
The OCXTM family of SRAM-based devices are non-blocking n X n digital crosspoint switches capable of data
rates of 667 Megabits per second per port. The I/O ports are fixed as either input or output ports. The input ports
support flow-through mode only. The output ports are individually programmable to operate in either flow-
through (asynchronous) or registered (synchronous) mode. Each output register may be clocked by a global
clock or a next neighbor clock source.
The patented ActiveArray provides greater density, superior performance, and greater flexibility compared to a
traditional n:1 multiplexer architecture. The OCX devices support various operating modes covering one input to
one output at a time as well as one input to many outputs, plus a special broadcast mode to program one input to
all outputs while maintaining maximum data rates. In all modes data integrity and connections are maintained on
all unchanged data paths.
The RapidConfigure parallel interface allows fast configuration of both the Output Buffers and the switch
matrix. Readback is supported for device test and verification purposes. The OCX160 also supports the industry
standard JTAG (IEEE 1149.1) interface for boundary scan testing. The JTAG interface can also be used to
download configuration data to the device and readback data. A functional block diagram of the OCX160 is
shown in Figure 1.
Applications
Figure 1 OCX160 Functional Block Diagram
667 Mb/s port data bandwidth, >50Gb/s aggregate bandwidth
Low power CMOS, 2.5V and 3.3V power supply
SRAM-based, in-system programmable
160 configurable I/O ports
80 dedicated differential input ports
80 dedicated differential output ports
Supports LVDS and LVPECL I/O
LVTTL control interface
Output Enable control for all outputs
Non-blocking switch matrix
Patented ActiveArrayTM matrix for superior performance
Double-buffered configuration RAM cells for simultaneous
global updates
ImpliedDisconnectTM function for single cycle disconnect/
connect
Full Broadcast and multicast capability
One-to-One and One-to-Many connections
Special broadcast mode routes one input to
all outputs at maximum data rate
Registered and flow-through data modes
333 MHz synchronous mode
667 Mb/s asynchronous mode
Low jitter and signal skew
Low duty cycle distortion
RapidConfigureTM parallel interface for
configuration and readback
JTAG serial interface for configuration and
Boundary Scan testing
420 BGA package with 1.27mm ball spacing
SONET/SDH and DWDM
Digital Cross-Connects
System Backplanes and Interconnects
High Speed Test Equipment
ATM Switch Cores
Video Switching
Input
Buffers
80 x 80
Crosspoint
Switch Matrix
CLK
OE#
HW_RST#
UPDATE#
OUT[79:0]
160
2
Configuration and
Programming Logic
RCA[6:0]
RCB[6:0]
RCI[3:0]
RC_CLK#
RC_EN#
4
7
7
RapidConfigure
Signals
IN[79:0]
160
Output
Buffers
JTAG
Signals
TCK
TRST#
TMS
TDI
TDO
RCO[4:0] 5
OCX160 Crosspoint Switch--Preliminary Data Sheet
2
[Rev. 1.6] 2/20/01
I-Cube, Inc.
(This page intentionally left blank)
I-Cube, Inc.
[Rev. 1.6] 2/20/01
3
OCX160 Crosspoint Switch--Preliminary Data Sheet
Contents
1.
Introduction ........................................................................................................................... 7
1.1
Input and Output Buffers...................................................................................................... 8
1.1.1
Input and Output Port Function Mode ........................................................................... 8
1.1.2
Broadcast Mode ............................................................................................................. 9
1.2
Output Buffer Configuration ................................................................................................ 9
1.2.1
Output Control Signals................................................................................................... 9
1.2.2
Neighboring Output Port as a Clock Source .................................................................. 9
1.3
RapidConfigure Interface ....................................................................................................11
1.3.1
RapidConfigure Programming Instructions.................................................................. 11
1.3.2
ImpliedDisconnect ....................................................................................................... 13
1.4
JTAG Configuration Controller .......................................................................................... 14
1.4.1
JTAG Interface ............................................................................................................. 14
1.4.2
Output Port Configuration ........................................................................................... 14
1.4.3
Switch Matrix Configuration ....................................................................................... 14
1.4.4
Mode Control Register Configuration.......................................................................... 14
1.4.5
JTAG Architecture and Shift Registers ........................................................................ 15
1.4.6
JTAG State Machine .................................................................................................... 16
1.4.7
JTAG Input Format ...................................................................................................... 16
1.4.8
JTAG Instructions ........................................................................................................ 17
1.5
Device Reset Options ......................................................................................................... 20
2.
Pin Description .....................................................................................................................21
3.
Differential I/O Standards ...................................................................................................22
3.1
LVDS ................................................................................................................................. 22
3.2
LVPECL ............................................................................................................................. 23
3.3
Termination Resistor Packs ................................................................................................ 24
3.4
Mixed I/O Systems............................................................................................................. 24
4.
Electrical Specifications .......................................................................................................25
4.1
Absolute Maximum Ratings .............................................................................................. 25
4.2
Recommended Operating Conditions ................................................................................ 25
OCX160 Crosspoint Switch--Preliminary Data Sheet
4
[Rev. 1.6] 2/20/01
I-Cube, Inc.
4.3
Pin Capacitance ................................................................................................................. 25
4.4
DC Electrical Specifications............................................................................................... 26
4.5
AC Electrical Specifications............................................................................................... 27
4.6
Timing Diagrams ................................................................................................................ 28
5.
Package and Pinout ............................................................................................................. 32
5.1
Package Pinout ................................................................................................................... 32
5.2
Pinout by Ball Sequence..................................................................................................... 33
5.3
Pinout by Ball Name .......................................................................................................... 36
5.4
Package Dimensions........................................................................................................... 38
5.5
Package Thermal Characteristics........................................................................................ 39
6.
Power Consumption ............................................................................................................ 40
6.1
Power for LVDS I/O .......................................................................................................... 40
6.2
Power for LVPECL I/O ..................................................................................................... 41
7.
Component Availability and Ordering Information ......................................................... 42
8.
Glossary ................................................................................................................................ 42
9.
Product Status Definition .................................................................................................... 44
I-Cube, Inc.
[Rev. 1.6] 2/20/01
5
OCX160 Crosspoint Switch--Preliminary Data Sheet
Figures
Figure 1
OCX160 Functional Block Diagram .................................................................................................... 1
Figure 2
OCX160 Switch Matrix ........................................................................................................................ 7
Figure 3
Input and Output Buffer Configuration ................................................................................................ 8
Figure 4
Next Neighbor Clock Block Diagram ................................................................................................ 10
Figure 5
OCX160 JTAG Architecture .............................................................................................................. 15
Figure 6
OCX160 JTAG State Machine ........................................................................................................... 16
Figure 7
Transmitting LVDS Signal Circuit ..................................................................................................... 22
Figure 8
Receiving LVDS Signal Circuit ......................................................................................................... 22
Figure 9
Transmitting LVPECL Signal Circuit ................................................................................................ 23
Figure 10
Receiving LVPECL Signal Circuit..................................................................................................... 23
Figure 11
Registered Output Mode Timing ........................................................................................................ 28
Figure 12
Flow-Through Mode Timing .............................................................................................................. 28
Figure 13
Output Enable Timing ........................................................................................................................ 28
Figure 14
Duty Cycle Distortion ......................................................................................................................... 29
Figure 15
RapidConfigure Write Cycle .............................................................................................................. 29
Figure 16
RapidConfigure Read Cycle ............................................................................................................... 30
Figure 17
JTAG Timing ...................................................................................................................................... 30
Figure 18
Typical Performance LVDS mode ..................................................................................................... 31
Figure 19
Typical Performance LVPECL mode................................................................................................. 31
Figure 20
OCX160 Package Pinout .................................................................................................................... 32
Figure 21
OCX160 Package--Bottom, Top and Side Views ............................................................................. 38
Figure 22
Power Consumption Diagram for the OCX160 using LVDS............................................................. 40
Figure 23
Power Consumption Diagram for the OCX160 using LVPECL ........................................................ 41