Version 1.3, September 15, 2003

Proprietary to OmniVision Technologies

Advanced Information

Preliminary Datasheet

OV9625 Color CMOS SXGA (1.3 MPixel) C

AMERA

HIP

OV9121 B&W CMOS SXGA (1.3 MPixel) C

AMERA

HIP

mni

ision

General Description

The OV9625 (color) and OV9121 (black and white) are
high-performance 1.3 mega-pixel C

AMERA

HIPS

for

digital still image and video camera products.

Both devices incorporate a 1280 x 1024 (SXGA) image
array and an on-chip 10-bit A/D converter capable of
operating at up to 15 frames per second (fps) at full
resolution and an improved micro lens design to decrease
shading. Proprietary sensor technology utilizes advanced
algorithms to cancel Fixed Pattern Noise (FPN), eliminate
smearing, and drastically reduce blooming. The control
registers allow for flexible control of timing, polarity, and
CameraChip operation, which, in turn, allows the engineer
a great deal of freedom in product design.

Features

Optical Black Level Calibration (BLC)

Improved micro lens design to decrease shading

Video or snapshot operations

Programmable/Auto Exposure and Gain Control

Programmable/Auto White Balance Control

Horizontal and vertical sub-sampling (4:2 and 4:2)

Programmable image windowing

Variable frame rate control

On-chip R/G/B channel and luminance average
counter

Internal/External frame synchronization

SCCB slave interface

Power-on reset and power-down mode

Ordering Information

Product

Package

OV09625-C00A (Color, SXGA,

VGA)

CLCC-48

OV09121-C00A (B&W with

microlens, SXGA, VGA)

CLCC-48

Applications

Digital still cameras

PC camera/dual mode

Video conference applications

Machine vision

Security cameras

Biometrics

Key Specifications

Figure 1 OV9625/OV9121 Pin Diagram

Array Size

SXGA

1280 x 1024

VGA

640 x 480

Power Supply

Core

2.5VDC + 10%

Analog

3.3VDC + 10%

I/O

3.3VDC + 10%

Power

Requirements

Active

< 50 mA

Standby

< 10 µA

Output Formats (10-bit)

Raw RGB Data

Lens Size

1/2"

Max. Image

Transfer Rate

SXGA

15 fps

VGA

30 fps

Sensitivity

1.0 V/Lux-sec

S/N Ratio

54 dB

Dynamic Range

60 dB (due to ADC limitations)

Scan Mode

Progressive

Gamma Correction

N/A

Electronics

Exposure

SXGA

Up to 1050:1

VGA

Up to 500:1

Pixel Size

5.2 µm x 5.2 µm

Dark Current

28 mV/s

Fixed Pattern Noise

< 0.03% of V

PEAK-TO-PEAK

Image Area

6.66 mm x 5.32 mm

Package Dimensions

.560 in. x .560 in.

DOVDD

DOGND

HREF

CHSYNC

VSYNC

PCLK

VGA

EXPSTB

SCCB_E

RESET

FREX

PWDN

ASUB

AGND

AVDD

VcCHG

FSIN

I
G

I
T

OV9625/OV9121

Proprietary to OmniVision Technologies

Version 1.3, September 15, 2003

OV9625/OV9121

CMOS SXGA (1.3 MPixel) C

AMERA

HIP

mni

ision

Functional Description

Figure 2

shows the functional block diagram of the OV9625/OV9121 image sensor. The OV9625/OV9121 includes:

Image Sensor Array

(1280 x 1024 resolution)

Gain Control

Channel Balance

10-Bit Analog-to-Digital Converter

Black Level Compensation

SCCB Interface

Digital Video Port

Timing Generator

Figure 2 Functional Block Diagram

Column Sense Amps

l
e

Image Array

(1312 x 1036)

AMP

Gain

Control

Balance

Control

Channel
Balance

10-Bit

A/D

Timing Generator and Control Logic

PLL

RESET

PWDN

FSI

VGA

FREX

EXPSTB

XCLK

Black Level

Compensation

Digital

Video

Port

D[9:0]

PCLK

HREF

HSYNC

VSYNC

SCCB Slave

Interface

Control

Register

Bank

SIO_C

SIO_D SCCB_E

Functional Description

Version 1.3, September 15, 2003

Proprietary to OmniVision Technologies

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ision

Image Sensor Array

The OV9625/OV9121 sensor is a 1/2-inch format CMOS
imaging device. The sensor contains 1,359,232 pixels.

Figure 3

shows the active regions of sensor array.

Figure 3 Sensor Array Region

The color filters are Bayer pattern. The primary color
BG/GR array is arranged in line-alternating fashion. Of the
1,359,232 pixels, 1,310,720 are active. The other pixels
are used for black level calibration and interpolation.

The sensor array design is based on a field integration
read-out system with line-by-line transfer and an
electronic shutter with a synchronous pixel read-out
scheme.

Gain Control

When the column sample/hold circuit has sampled one
row of pixels, the pixel data will shift out one-by-one into
an analog amplifier. The amplifier gain can either be
programmed by the user or controlled by the internal
automatic gain control circuit (AGC). The gain adjustment
range is 0-24 dB.

Channel Balance

The amplified signals are then balanced with a channel
balance block. In this block, Red/Blue channel gain is
increased or decreased to match Green channel
luminance level and gamma correction is performed. The
adjustment range is 54 dB. This function can be done
manually by the user or with the internal automatic white
balance controller (AWB).

1035

1034

1033

1306

1307

1308

1309

1310

1311

Column

Dummy

Optical

Black

Dummy

1032

1024
Active
Lines

R
o
w

10-Bit Analog-to-Digital Converter

The balanced signal then will be digitized by the on-chip
10-bit ADC. It can operate at up to 12 MHz, and is fully
synchronous to the pixel clock. The actual conversion rate
is determined by the frame rate.

Black Level Compensation

After the pixel data has been digitized, black level
calibration can be performed before the data is output.
The black level calibration block subtracts the average
signal level of optical black pixels to compensate for the
dark current in the pixel output. Black level calibration can
be disabled by the user.

Windowing

OV9625/OV9121 allows the user to define window size or
region of interest (ROI), as required by the application.
Window size setting (in pixels) ranges from 2 x 4 to
1280 x 1024 (SXGA) or 2 x 2 to 640 x 480 (VGA), and can
be anywhere inside the 1312 x 1036 boundary. Note that
modifying window size or window position does not alter
the frame or pixel rate. The windowing control merely
alters the assertion of the HREF signal to be consistent
with the programmed horizontal and vertical ROI. The
default window size is 1280 x 1024. See

Figure 4

and

registers

HREFST

HREFEND

VSTRT

VEND

, and

COMM

for details. The maximum output window size is

1292 columns by 1024 rows.

Note that after writing to register

COMH

(0x12) to change

the sensor mode, registers related to the sensor's
cropping window will be reset back to its default value.

Figure 4 Windowing

Column

End

Sensor Array

Boundary

HREF

Column

Display

Window

Column

Start

Row Start

Row End

Proprietary to OmniVision Technologies

Version 1.3, September 15, 2003

OV9625/OV9121

CMOS SXGA (1.3 MPixel) C

AMERA

HIP

mni

ision

Sub-sampling Mode

Default resolution for the OV9625/OV9121 is 1280 x 1024
pixels, with all active pixels being output (see

Figure 5

The OV9625/OV9121 can be programmed to output in
640 x 480 (VGA) sized images for applications where
higher resolution image capture is not required.

Figure 5 Pixel Array

For VGA resolution, the following sub-sampling method is
available:

Progressive Sub-sampling

The entire array is sub-sampled for maximal image
quality. Both horizontal and vertical pixels are
sub-sampled to an aspect ration of 4:2 as illustrated in

Figure 6

Figure 6 Sub-Sampling Mode

i+1

n+7

n+6

n+5

n+4

n+1

n+2

n+3

Row #

i+2 i+3 i+4 i+5 i+6 i+7 i+8 i+9

Column #

n+1

n+2

n+3

n+4

n+5

n+6

n+7

i+1

i+3

i+4

i+7

i+8

i+9

Column

Row

Skipped Pixels

Slave Operation Mode

The OV9625/OV9121 can be programmed to operate in
slave mode (default is master mode).

When used as a slave device, the OV9625/OV9121
changes the HSYNC and VSYNC outputs to input pins for
use as horizontal and vertical synchronization input
triggers supplied by the master device. The master device
must provide the following signals:

System clock MCLK to XCLK1 pin

Horizontal sync MHSYNC to CHSYNC pin

Vertical frame sync MVSYNC to VSYNC pin

See

Figure 7

for slave mode connections and

Figure 8

for

detailed timing considerations. In this mode, the clock for
all devices should be the same. Otherwise, the devices
will suffer from flickering at line frequency.

Figure 7 Slave Mode Connection

Figure 8 Slave Mode Timing

Channel Average Calculator

OV9625/OV9121 provides average output level data for
the R/G/B channels along with frame-averaged luminance
level. Access to the data is via the serial control port.
Average values are calculated from 128 pixels per line (64
in VGA).

D[9:0]

CHSYNC

VSYNC

XCLK1

MHSYNC

MVSYNC

MCLK

Master
Device

OV9625

(OV9121)

NOTE:

1) T

> 6 T

clk

, Tvs > T

line

2) T

line

= 1520 x T

clk

(SXGA); T

line

= 800 x T

clk

(VGA)

3) T

frame

= 1050 x T

line

(SXGA); T

frame

= 500 x T

line

(VGA)

frame

line

clk

VSYNC

HSYNC

MCLK

Functional Description

Version 1.3, September 15, 2003

Proprietary to OmniVision Technologies

mni

ision

Reset

The

RESET

pin (pin 10) is active high. There is an internal

pull-down (weak) resistor in the sensor so the default
status of the

RESET

pin is low.

Figure 9 RESET Timing Diagram

There are two ways for a sensor reset:

Hardware reset - Pulling the

RESET

pin high and

keeping it high for at least 1 ms. As shown in

Figure 9

, after a reset has been initiated, the sensor

will be most stable after the period shown as 4096
External Clock.

Software reset - Writing 0x80 to register 0x12 (see

"COMH" on page 20

) for a software reset. If a

software reset is used, a reset operation done twice
is recommended to make sure the sensor is stable
and ready to access registers. When performing a
software reset twice, the second reset should be
initiated after the 4096 External Clock period as
shown in

Figure 9

Power-Down Mode

The

PWDN

pin (pin 7) is active high. There is an internal

pull-down (weak) resistor in the sensor so the default
status of the

PWDN

pin is low.

Figure 10 PWDN Timing Diagram

1ms

RESET

4096 External Clock

PWDN

Sensor Power Down

Two methods of power-down or standby operation are
available with the OV9625/OV9121.

Hardware power-down may be selected by pulling
the

PWDN

pin (pin 7) high (+3.3VDC). When this

occurs, the OV9625/OV9121 internal device clock is
halted and all internal counters are reset. The current
draw is less than 10 µA in this standby mode.

Software power-down can be effected by setting the

COMC

[4] register bit high. Standby current will be

less then 1 mA when in software power-down. All
register content is maintained in standby mode.

SCCB Interface

OV9625/OV9121 provides an on-chip SCCB serial control
port that allows access to all internal registers, for
complete control and monitoring of OV9625/OV9121
operation.

Refer to

OmniVision Technologies Serial Camera Control

Bus (SCCB) Specification

for detailed usage of the SCCB

interface.

Video Output

RGB Raw Data Output

The OV9625 C

AMERA

HIP

offers 10-bit RGB raw data

output.

B&W Output

The OV9121 offers 10-bit luminance signal data output.

Proprietary to OmniVision Technologies

Version 1.3, September 15, 2003

OV9625/OV9121

CMOS SXGA (1.3 MPixel) C

AMERA

HIP

mni

ision

Digital Video Port

MSB/LSB Swap

OV9625/OV9121 has a 10-bit digital video port. The MSB
and LSB can be swapped with the control registers.

Figure 11

shows some examples of connections with

external devices.

Figure 11 Connection Examples

LSB D0

MSB D0

External

Device

OV9625

(OV9121)

External

Device

OV9625

(OV9121)

MSB D9

LSB D9

Default 10-bit Connection

Swap 10-bit Connection

LSB D0

MSB D0

External

Device

OV9625

(OV9121)

External

Device

OV9625

(OV9121)

MSB D9

LSB D9

Default 8-bit Connection

Swap 8-bit Connection

Line/Pixel Timing

The OV9625/OV9121 digital video port can be
programmed to work in either master or slave mode.

In both master and slave modes, pixel data output is
synchronous with PCLK (or MCLK if port is a slave),
HREF and VSYNC. The default PCLK edge for valid data
is the negative edge but may be programmed with register
COMK[4] (see

"COMK" on page 22

) for the positive edge.

Basic line/pixel output timing is illustrated in

Figure 14

and

Figure 15

To minimize image capture circuitry and conserve
memory space, PCLK output can be programmed with
register COMK[5] (see

"COMK" on page 22

) to be

qualified by the active video period as defined by the
HREF signal. See

Figure 12

for details.

Figure 12 PCLK Output Only at Valid Pixels

Pixel Output Pattern

Table 1

shows the output data order from the

OV9625/OV9121. The data output sequence following the
first HREF and after VSYNC is: B

0,0

0,1

0,2

0,3

...

0,1278

0,1279

. After the second HREF, the output is G

1,0

1,1

1,2

1,3

... G

1,1278

1,1279

..., etc. If the

OV9625/OV9121 is programmed to output VGA
resolution data, horizontal and vertical sub-sampling will
occur. The default output sequence for the first line of
output will be: B

0,0

0,1

0,4

0,5

... B

0,1276

0,1277

. The

second line of output will be: G

1,0

1,1

1,4

1,5

... G

1,1276

1,1277

Table 1

Data Pattern

R/C

. . .

1278

1279

0,0

0,1

0,2

0,3

. . .

0,1278

0,1279

1,0

1,1

1,2

1,3

. . .

1,1278

1,1279

2,0

2,2

2,3

. . .

2,1278

2,1279

3,0

3,1

3,2

3,3

. . .

3,1278

3,1279

.
.

1022

1022,0

1022,1

1022,2

1022,3

1022,1278

1022,1279

1023

1023,0

1023,1

1023,2

1023,3

1023,1278

1023,1279

VSYNC

PCLK

HREF

PCLK

PCLK active edge positive

PCLK active edge negative

Functional Description

Version 1.3, September 15, 2003

Proprietary to OmniVision Technologies

mni

ision

Timing Generator

In general, the timing generator controls the following
functions:

Frame Exposure Mode Timing

Frame Rate Timing

Frame Rate Adjust

Frame Exposure Mode Timing

OV9625/OV9121 supports frame exposure mode.
Typically the frame exposure mode must work with the aid
of an external shutter.

The frame exposure pin,

FREX

(pin 8) is the frame

exposure mode enable pin and

EXPSTB

(pin 12) serves

as the exposure start trigger for the sensor. There are two
ways to set Frame Exposure mode:

Control both

FREX

and

EXPSTB

pins - Frame

Exposure mode can be set by pulling both FREX and
EXPSTB pins high at the same time (see

Figure 19

Control

FREX

only and keep

EXPSTB

low - In this

case, the pre-charge time is tline and sensor
exposure time is the period after pre-charge until the
shutter closes (see

Figure 18

When the external master device asserts the

FREX

high, the sensor array is quickly pre-charged and stays in
reset mode until the

EXPSTB

pin is pulled low by the

external master (sensor exposure time can be defined as
the period between

EXPSTB

low to shutter close). After

the

FREX

pin is pulled low, the video data stream is then

clocked to the output port in a line-by-line manner. After
completing one frame of data output, OV9625/OV9121
will output continuous live video data unless in single
frame transfer mode.

Figure 18

and

Figure 19

show the

detailed timing for this mode.

For frame exposure, register

AEC

(0x10) must be set to

0xFF and register

GAIN

(0x00) should be no larger than

0x10 (maximum 2x gain).

Frame Rate Timing

Default frame timing is illustrated in

Figure 16

and

Figure 17

. Refer to

Table 2

for the actual pixel rate at

different frame rates.

Frame Rate Adjust

OV9625/OV9121 offers three methods of frame rate
adjustment.

Clock prescaler (see

"CLKRC" on page 20

)

By changing the system clock divide ratio, the frame
rate and pixel rate will change together. This
method can be used for dividing the frame/pixel rate
by: 1/2, 1/3, 1/4 ... 1/64 of the input clock rate.

Line adjustment (see

"COML" on page 24

and see

"FRARL" on page 25

)

By adding dummy pixel timing in each line, the
frame rate can be changed while leaving the pixel
rate as is.

Vertical sync adjustment
By adding dummy line periods to the vertical sync
period (see

"ADDVSL" on page 25

and see

"ADDVSH" on page 25

), the frame rate can be

altered while the pixel rate remains the same.

After changing registers

COML

(0x2A) and

FRARL

(0x2B)

to adjust the dummy pixels, it is necessary to write to
register

COMH

(0x12) or

CLKRC

(0x11) to reset the

counter. Generally, OmniVision suggests users write to
register

COMH

(0x12) (to change the sensor mode) as the

last one. However, if you want to adjust the cropping
window, it is necessary to write to those registers after
changing register

COMH

(0x12). To use

COMH

to reset

the counter, it is necessary to generate a pulse on
resolution control register bit

COMH

[6].

Table 2

Frame and Pixel Rates

Frame Rage (fps)

7.5

PCLK (MHz)

9.6

NOTE: Based on 24 MHz external clock and internal PLL
on, frame rate is adjusted by the main clock divide method.

Proprietary to OmniVision Technologies

Version 1.3, September 15, 2003

OV9625/OV9121

CMOS SXGA (1.3 MPixel) C

AMERA

HIP

mni

ision

Pin Description

Table 3

Pin Description

Pin Number

Name

Pin Type

Function/Description

SVDD

Power

3.3 V power supply for the pixel array

VrHIGH

Analog

Sensor high reference - bypass to ground using a 0.1 µF capacitor

NBIT

Analog

Sensor bit line reference - bypass to ground using a 0.1 µF capacitor

DEVDD

Power

3.3 V power supply for the sensor array decoder

DEGND

Power

Ground for the sensor array decoder

VrLOW

Analog

Sensor low reference - bypass to ground using a 0.1 µF capacitor

PWDN

Input (0)

Power down mode enable, active high

FREX

Input (0)

Snapshot trigger, used to activate a snapshot sequence

No connection

RESET

Input (0)

Chip reset, active high

SCCB_E

Input (0)

SCCB interface enable, active low

EXPSTB

Input (0)

Snapshot exposure start trigger

Sensor starts exposure - only effective in snapshot mode

Sensor stays in reset mode

VGA

Input (0)

Sensor Resolution Selection

SXGA resolution (1280 x 1024)

VGA resolution (640 x 480)

FSIN

Input (0)

Frame synchronization input

VcCHG

Analog

Sensor reference - bypass to ground using a 1 µF capacitor

AVDD

Power

3.3 V power supply for analog circuits

AGND

Power

Ground for analog circuits

ASUB

Power

Ground for analog circuit substrate

VrAD2

Analog

A/D converter reference - bypass to ground using a 0.1 µF capacitor

ADVDD

Power

3.3 V power supply for A/D converter

ADGND

Power

Ground for A/D converter

DVDD

Power

2.5 V power supply for digital circuits

DGND

Power

Ground for digital circuits

Output

Digital video output bit[0]

Output

Digital video output bit[1]

Output

Digital video output bit[2]

Output

Digital video output bit[3]

Output

Digital video output bit[4]

Pin Description

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Proprietary to OmniVision Technologies

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ision

XCLK1

Input

Crystal clock input

XCLK2

Output

Crystal clock output

PCLK

Output

Pixel clock output

Output

Digital video output bit[5]

Output

Digital video output bit[6]

Output

Digital video output bit[7]

Output

Digital video output bit[8]

Output

Digital video output bit[9]

DOVDD

Power

3.3 V power supply for digital video port

DOGND

Power

Ground for digital video port

HREF

Output

Horizontal reference output

CHSYNC

Output

Horizontal synchronization output when chip is in master mode.

VSYNC

Output

Vertical synchronization output when chip is in master mode.

No connection

SIO_D

I/O

SCCB serial interface data I/O

SIO_C

Input

SCCB serial interface clock input

VcCHG

Analog

Sensor reference - bypass to ground using a 1 µF capacitor

SGND

Power

Ground for pixel array.

Input (0) represents an internal pull-down low resistor.

Table 3

Pin Description (Continued)

Pin Number

Name

Pin Type

Function/Description

Proprietary to OmniVision Technologies

Version 1.3, September 15, 2003

OV9625/OV9121

CMOS SXGA (1.3 MPixel) C

AMERA

HIP

mni

ision

Electrical Characteristics

NOTE:

Exceeding the Absolute Maximum ratings shown above invalidates all AC and DC electrical specifications and may
result in permanent device damage.

Table 4

Absolute Maximum Ratings

Ambient Storage Temperature

-40ºC to +125ºC

Supply Voltages (with respect to Ground)

DD-A

3.3V

DD-C

2.5V

DD-IO

3.3V

All Input/Output Voltages (with respect to Ground)

-0.3V to V

DD-IO

+1V

Lead Temperature, Surface-mount process

+230ºC

ESD Rating, Human Body model

2000V

Table 5

DC Characteristics (0°C < T

< 70°C)

Symbol

Parameter

Min

Typ

Max

Unit

Supply

DD-A

Supply voltage (DEVDD, ADVDD, AVDD, SVDD)

3.0

3.3

3.6

DD-IO

Supply voltage (DOVDD)

3.0

3.3

3.6

DD-C

Supply voltage (DVDD)

2.25

2.5

2.75

DD1

Active (Operating) Current

DD2

Standby Current

DD3

Standby Current

µA

Digital Inputs

Input voltage LOW

0.8

Input voltage HIGH

Input capacitor

Digital Outputs (standard loading 25 pF, 1.2 K

: to 3 V)

Output voltage HIGH

2.4

Output voltage LOW

0.6

SCCB Inputs

SIO_C and SIO_D

-0.5

SIO_C and SIO_D

2.5

3.3

+ 0.5

Electrical Characteristics

Version 1.3, September 15, 2003

Proprietary to OmniVision Technologies

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ision

Table 6

AC Characteristics (T

= 25°C, V

= 3V)

Symbol

Parameter

Min

Typ

Max

Unit

ADC Parameters

Analog bandwidth

MHz

DLE

DC differential linearity error

0.5

LSB

ILE

DC integral linearity error

LSB

Settling time for hardware reset

Settling time for software reset

Settling time for VGA/XSGA mode change

Settling time for register setting

<300

Table 7

Timing Characteristics

Symbol

Parameter

Min

Typ

Max

Unit

Oscillator and Clock Input

OSC

Frequency (XCLK1, XCLK2)

MHz

, t

Clock input rise/fall time

Clock input duty cycle

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OV9625/OV9121

CMOS SXGA (1.3 MPixel) C

AMERA

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ision

Timing Specifications

Figure 13 SCCB Timing Diagram

Table 8

SCCB Timing Specifications

Symbol

Parameter

Min

Typ

Max

Unit

SIO_C

Clock Frequency

400

KHz

LOW

Clock Low Period

1.3

HIGH

Clock High Period

600

SIO_C low to Data Out valid

100

900

BUF

Bus free time before new START

1.3

HD:STA

START condition Hold time

600

SU:STA

START condition Setup time

600

HD:DAT

Data-in Hold time

SU:DAT

Data-in Setup time

100

SU:STO

STOP condition Setup time

600

SCCB Rise/Fall times

300

Data-out Hold time

SIO_C

SU:STA

HD:STA

SIO_D

OUT

LOW

HIGH

HD:DAT

SU:DAT

BUF

SU:STO

SCCB_E

Proprietary to OmniVision Technologies

Version 1.3, September 15, 2003

OV9625/OV9121

CMOS SXGA (1.3 MPixel) C

AMERA

HIP

mni

ision

Figure 16 SXGA Frame Timing

Figure 17 VGA Frame Timing

The specifications shown in

Table 9

apply for DVDD = +2.5V, DOVDD = +3.3V, T

= 25

°C, sensor working at 15 fps,

external loading = 30 pF.

Table 9

Pixel Timing Specification

Symbol

Parameter

Min

Typ

Max

Unit

PCLK period

20.83

PCLK rising time

PCLK falling time

dphr

PCLK negative edge to HREF rising edge

dphf

PCLK negative edge to HREF negative edge

dpd

PCLK negative edge to data output delay

Data bus setup time

Data bus hold time

VSYNC

D[9:0]

HREF

1050 x tline

21284tp

4 x tline

12396tp

240tp

tline = 1520tp

1280tp

Invalid Data

Row 1

Row 2

Row 1023

Row 0

P0 - P1279

VSYNC

D[9:0]

HREF

500 x tline

6402tp

4 x tline

6558tp

160tp

tline = 800tp

640tp

Invalid Data

Row 1

Row 2

Row 479

Row 0

P0 - P639

Timing Specifications

Version 1.3, September 15, 2003

Proprietary to OmniVision Technologies

mni

ision

Figure 18 Frame Exposure Timing with EXPSTB Staying Low

Figure 19 Frame Exposure Timing with EXPSTB Asserted

NOTE

1) FREX must stay high long enough to ensure the entire sensor has been reset.
2) Shutter must be closed no later then 3040tp (1600tp for VGA) after VSYNC falling edge.

Table 10

Frame Exposure Timing Specifications

Symbol

Min

Typ

Max

Unit

tline

1520 (SXGA)

800 (VGA)

tvs

tline

tdfvr

tdfvf

tline

tdvsc

tline

tdhv

21044 (SXGA)

6402 (VGA)

tdvh

12396 (SXGA)

6558 (VGA)

tdes

1500 (SXGA)

780 (VGA)

Row 1

Row 0

Row 1199

Row X

No following live video

frame if set to transfer

single frame

D[9:0]

HREF

VSYNC

Sensor Timing

FREX

Shutter

Sensor

Precharge

Shutter Open

dfvr

line

Exposure Time

dfvf

dvsc

dvh

dhv

Row 1

Row 0

Row 1199

Row X

No following live video

frame if set to transfer

single frame

D[9:0]

HREF

VSYNC

Sensor Timing

FREX

Shutter

Sensor

Precharge

Shutter Open

dfvr

pre

Exposure Time

dfvf

dvsc

dvh

dhv

EXPSTB

des

def

Proprietary to OmniVision Technologies

Version 1.3, September 15, 2003

OV9625/OV9121

CMOS SXGA (1.3 MPixel) C

AMERA

HIP

mni

ision

OV9625/OV9121 Light Response

Figure 20 OV9625/OV9121 Light Response

OV-9620spectrum response

100

120

140

160

180

200

300nm

380nm

420nm

460nm

500nm

540nm

580nm

620nm

660nm

700nm

740nm

780nm

820nm

860nm

900nm

940nm

980nm

1020nm

1060nm

1100nm

1180nm

Wavelength

Monochrome Response

0.00

0.10

0.20

0.30

0.40

0.50

0.60

0.70

0.80

0.90

1.00

Wavelength

f
i
ci

ency

200

180

160

140

120

100

1.00

0.90

0.80

0.70

0.60

0.50

0.40

0.30

0.20

0.10

0.00

400

450

500

550

600

650

700

750

800

850

900

950

000

050

100

150

Wavelength

Efficie

ncy

Monochrome Response

Efficien

300

380

420

460

500

540

580

620

660

700

740

780

820

860

900

940

Wavelength (nm)

Normalized Spectrum Response

980

020

060

100

180

Version 1.3, September 15, 2003

Proprietary to OmniVision Technologies

mni

ision

Register Set

Table 11

provides a list and description of the Device Control registers contained in the OV9625/OV9121. The device slave

addresses are 60 for write and 61 for read.

Table 11

Device Control Register List

Address

(Hex)

Register

Name

Default

(Hex)

R/W

Description

GAIN

AGC Gain Control

Bit[7:6]:

Reserved

Bit[5:0]:

Gain control gain setting
·

Range: 1x to 8x

Set COMI[0] = 0 (see

"COMI" on page 21

) to disable AGC

BLUE

Blue gain control MSB, 8 bits (LSB 2 bits in COMA[3:2], see

"COMA" on

page 17

)

Note: This function is not available on the B&W OV9121.

RED

Red gain control MSB, 8 bits (LSB 2 bits in COMA[1:0], see

"COMA" on

page 17

)

Note: This function is not available on the B&W OV9121.

COMA

Common Control A

Bit[7:4]:

AWB update threshold

Bit[3:2]:

BLUE channel lower 2 bits gain control

Bit[1:0]:

RED channel lower 2 bits gain control

Note: This function is not available on the B&W OV9121.

COMB

Common Control B

Bit[7,4]:

AWB Update speed select

00: Slow
01: Slowest
10: Fast
11: Fast

Bit[6:5]:

AWB Step select

00: 1023 steps
01: 255 steps
10: 511 steps
11: 255 steps

Bit[3]:

Reserved

Bit[2:0]:

AEC lower 3 bits, AEC[2:0] (see

"AEC" on page 19

for

most significant 8 bits, AEC[10:3])

BAVG

B Channel Average

GbAVG

G Channel Average - picked G pixels in the same line with B pixels.

GrAVG

G Channel Average - picked G pixels in the same line with R pixels.

RAVG

R Channel Average

Proprietary to OmniVision Technologies

Version 1.3, September 15, 2003

OV9625/OV9121

CMOS SXGA (1.3 MPixel) C

AMERA

HIP

mni

ision

COMC

Common Control C

Bit[7:5]:

Reserved

Bit[4]:

Sleep or power-down mode enable

Normal

Sleep mode

Bit[3:2]:

Crystal oscillator output current

00: Weakest
11: Strongest

Bit[1:0]:

Output Drive Select

00: Weakest
01: Double capability
10: Double capability
11: Triple drive current

PIDH

Product ID Number MSB (Read only)

PIDL

Product ID Number LSB (Read only)

COMD

Common Control D

Bit[7]:

Reserved

Bit[6]:

Swap MSB and LSB at the output port

Bit[5:2]:

Reserved

Bit[1]:

Sensor precharge voltage selection

Selects internal reference as precharge voltage

Selects SVDD as precharge voltage

Bit[0]:

Snapshot option

Enable live video output after snapshot sequence

Output single frame only

COME

Common Control E

Bit[7]:

Reserved

Bit[6]:

Anti-blooming control

Anti-blooming ON

Anti-blooming OFF

Bit[5:3]:

Reserved

Bit[2]:

Clock output power-down pin status

Maintain internal default states at power-down

Tri-state the VSYNC and CHSYNC pins upon
power-down

Bit[1]:

Reserved

Bit[0]:

Digital port output

Enable data port output

Disable data port output

Table 11

Device Control Register List

Address

(Hex)

Register

Name

Default

(Hex)

R/W

Description

Version 1.3, September 15, 2003

Proprietary to OmniVision Technologies

mni

ision

COMF

Common Control F

Bit[7]:

System clock selection

Use 24 MHz system clock

Use 48 MHz system clock

Bit[6:3]:

Reserved

Bit[2]:

Port output range selection

Output data range is [001] to [3FE]

Output data range is [000] to [3FF]

Bit[1]:

Reserved

Bit[0]:

AEC option

Disable this function

Enable larger AEC step increase with correct
exposure time

COMG

Common Control G

Bit[7]:

Optical black output selection

Disable

Enable

Bit[6]:

Black level calibrate selection

Use electrical black reference

Use optical black pixels to calibrate

Bit[5:4]:

Reserved

Bit[3]:

Channel offset adjustment

Disable offset adjustment

Enable offset adjustment, B/Gb/Gr/R channel offset
levels stored in registers RBIAS (see

"BBIAS" on

page 24

), GbBIAS (see

"GbBIAS" on page 24

GrBIAS (see

"GrBIAS" on page 24

) and RBIAS (see

"RBIAS" on page 25

Bit[2]:

Data range selection

Data range limited to [010] to [3F0]

Full range

Bit[1]:

ADC black level calibration bias selection

040

010

Bit[0]:

ADC black level calibration enable

Disable

Enable

AEC

Automatic Exposure Control Most Significant 8 bits for AEC[10:3] (least
significant 3 bits, AEC[2:0], in register COMB[2:0] - see

"COMB" on

page 17

AEC[10:0]:

Exposure time

= t

LINE

x AEC[10:0]

Set COMI[2] = 0 (see

"COMI" on page 21

) to disable the AEC.

Table 11

Device Control Register List

Address

(Hex)

Register

Name

Default

(Hex)

R/W

Description

Proprietary to OmniVision Technologies

Version 1.3, September 15, 2003

OV9625/OV9121

CMOS SXGA (1.3 MPixel) C

AMERA

HIP

mni

ision

CLKRC

Clock Rate Control

Bit[7]:

Internal PLL ON/OFF selection

PLL disabled

PLL enabled

Bit[6]:

Digital video port master/slave selection

Master mode, sensor provides PCLK

Slave mode, external PCLK input from XCLK1 pin

Bit[5:0]:

Clock divider

CLK = XCLK1/(decimal value of CLKRC[5:0] + 1)

COMH

Common Control H

Bit[7]:

SRST

Initiates soft reset. All register are set to factory
default values after which the chip resumes normal
operation

Bit[6]:

Resolution selection

SXGA

VGA

Bit[5]:

Average luminance value pixel counter ON/OFF

OFF

Bit[4]:

Reserved

Bit[3]:

Master/slave selection

Master mode

Slave mode

Bit[2]:

Window output selection

Output only pixels defined by window registers

Output all pixels

Bit[1]:

Color bar test pattern

OFF

Bit[0]:

Reserved

Table 11

Device Control Register List

Address

(Hex)

Register

Name

Default

(Hex)

R/W

Description

Version 1.3, September 15, 2003

Proprietary to OmniVision Technologies

mni

ision

COMI

Common Control I

Bit[7]:

AEC speed selection

Normal

Faster AEC correction

Bit[6]:

AEC speed/step selection

Small steps (slow)

Big steps (fast)

Bit[5]:

Banding filter ON/OFF

OFF

ON, set minimum exposure to 1/120s

Bit[4]:

Banding filter option

Set to 0, if system clock is 48 MHz and the PLL is
ON.

Set to 1, if system clock is 24 MHz and the PLL is ON
or if the system clock is 48 MHz and the PLL is OFF.

Bit[3]:

Reserved

Bit[2]:

AGC auto/manual control selection

Manual

Auto

Bit[1]:

AWB auto/manual control selection

Manual

Auto

Bit[0]:

Exposure control

Manual

Auto

COMJ

Common Control J

Bit[7:6]:

AGC gain ceiling

00: 2x
01: 4x
10: 8x
11: 8x

Bit[5:4]:

Reserved

Bit[3]:

Auto banding filter

Banding filter is always ON/OFF depending on
COMI[5] setting (see

"COMI" on page 21

)

Automatically disable banding filter if light is low

Bit[2]:

VSYNC drop option

VSYNC is always output

VSYNC is dropped if frame data is dropped

Bit[1]:

Frame data drop option

Disable data drop

Drop data frame if exposure is not within tolerance.
In AEC mode, data is normally dropped when data is
out of range

Bit[0]:

Freeze current Exposure and Gain values

Normal

Freeze

Table 11

Device Control Register List

Address

(Hex)

Register

Name

Default

(Hex)

R/W

Description

Proprietary to OmniVision Technologies

Version 1.3, September 15, 2003

OV9625/OV9121

CMOS SXGA (1.3 MPixel) C

AMERA

HIP

mni

ision

COMK

Common Control K

Bit[7]:

CHSYNC pin output swap

CHSYNC

HREF

Bit[6]:

HREF pin output swap

HREF

CHSYNC

Bit[5]:

PCLK output selection

PCLK always output

PCLK output qualified by HREF

Bit[4]:

PCLK edge selection

Data valid on PCLK falling edge

Data valid on PCLK rising edge

Bit[3]:

HREF output polarity

Output positive HREF

Output negative HREF, HREF negative for data valid

Bit[2]:

Reserved

Bit[1]:

VSYNC polarity

Positive

Negative

Bit[0]:

HSYNC polarity

Positive

Negative

RSVD

Reserved

HREFST

(13 in
VGA)

Horizontal Window Start Most Significant 8 bits, LSB in register
COMM[1:0] (see

"COMM" on page 26

HREFST[9:0]: Selects the beginning of the horizontal window,

each LSB represents two pixels. Adjustment steps
must be 2 pixels.

Note:
1. HFREFST[9:0] should be less than HREFEND[9:0].
2. For maximum output window size of 1292x1024, minimum value of
this register is 0x1C.

HREFEND

(63 in
VGA)

Horizontal Window end most significant 8 bits, LSB in register
COMM[3:2] (see

"COMM" on page 26

HREFEND[9:0]: Selects the end of the horizontal window, each

LSB represents two pixels. Adjustment steps
must be 2 pixels.

Note:
1. HREFEND[9:0] should be larger than HREFST[9:0].
2. For maximum output window size of 1292x1024, maximum value of
this register is 0xBD.

Table 11

Device Control Register List

Address

(Hex)

Register

Name

Default

(Hex)

R/W

Description

Version 1.3, September 15, 2003

Proprietary to OmniVision Technologies

mni

ision

VSTRT

(02 in
VGA)

Vertical Window line start most significant 8 bits, LSB in register
COMM[4] (see

"COMM" on page 26

Bit[8:0]:

Selects the start of the vertical window, each LSB
represents four scan lines in SXGA or two scan lines in
VGA.

Note:
1. VSTRT[8:0] should be less than VEND[8:0].
2. For maximum output window size of 1292x1024, minimum value of
this register is 0x01.

VEND

(7A in

VGA)

Vertical Window line end most significant 8 bits, LSB in register
COMM[5] (see

"COMM" on page 26

Bit[8:0]:

Selects the end of the vertical window, each LSB
represents four scan lines in SXGA and two scan lines in
VGA.

Note:
1. VEND[8:0] should be larger than VSTRT[8:0].
2. For maximum output window size of 1292x1024, maximum value of
this register is 0x81.

PSHFT

Pixel Shift

Bit[7:0]:

Pixel delay count. Provides a method to fine tune the
output timing of the pixel data relative to the HREF pulse.
It physically shifts the video data output time in units of
pixel clock counts. The largest delay count is [FF] and is
equal to 255 x PCLK.

MIDH

Manufacturer ID Byte High

(Read only = 0x7F)

MIDL

Manufacturer ID Byte Low

(Read only = 0xA2)

1E-1F

RSVD

Reserved

BOFF

B Channel Offset Adjustment - auto controlled by internal circuit if
COMG[0] = 1 (see

"COMG" on page 19

)

Bit[7]:

Offset direction

Add BOFF[6:0]

Subtract BOFF[6:0]

Bit[6:0]:

B channel offset adjustment value

GbOFF

Gb Channel Offset Adjustment - auto controlled by internal circuit if
COMG[0] = 1 (see

"COMG" on page 19

)

Bit[7]:

Offset direction

Add GbOFF[6:0]

Subtract GbOFF[6:0]

Bit[6:0]:

Gb channel offset adjustment value

GrOFF

Gr Channel Offset Adjustment - auto controlled by internal circuit if
COMG[0] = 1 (see

"COMG" on page 19

)

Bit[7]:

Offset direction

Add GrOFF[6:0]

Subtract GrOFF[6:0]

Bit[6:0]:

Gr channel offset adjustment value

Table 11

Device Control Register List

Address

(Hex)

Register

Name

Default

(Hex)

R/W

Description

Proprietary to OmniVision Technologies

Version 1.3, September 15, 2003

OV9625/OV9121

CMOS SXGA (1.3 MPixel) C

AMERA

HIP

mni

ision

ROFF

R Channel Offset Adjustment - auto controlled by internal circuit if
COMG[0] = 1 (see

"COMG" on page 19

)

Bit[7]:

Offset direction

Add ROFF[6:0]

Subtract ROFF[6:0]

Bit[6:0]:

R channel offset adjustment value

AEW

Luminance Signal High Range for AEC/AGC Operation

AEC/AGC values will decrease in auto mode when average
luminance is greater than AEW[7:0]

AEB

Luminance Signal Low Range for AEC/AGC Operation

AEC/AGC values will increase in auto mode when average
luminance is less than AEB[7:0].

Fast Mode Large Step Range Thresholds - effective only in AEC/AGC
fast mode (COMI[7] = 1, see

"COMI" on page 21

)

Bit[7:4]:

High threshold

Bit[3:0]:

Low threshold

AEC/AGC may change in larger steps when luminance average is
greater than VV[7:4] or less than VV[3:0].

BBIAS

B Channel Offset Manual Adjustment Value - effective only when
COMG[3] = 1 (see

"COMG" on page 19

Bit[7]:

Offset direction

Add BBIAS[6:0]

Subtract BBIAS[6:0]

Bit[6:0]:

B channel offset adjustment value

GbBIAS

Gb Channel Offset Manual Adjustment Value - effective only when
COMG[3] = 1 (see

"COMG" on page 19

Bit[7]:

Offset direction

Add GbBIAS[6:0]

Subtract GbBIAS[6:0]

Bit[6:0]:

Gb channel offset adjustment value

GrBIAS

Gr Channel Offset Manual Adjustment Value - effective only when
COMG[3] = 1 (see

"COMG" on page 19

Bit[7]:

Offset direction

Add GrBIAS[6:0]

Subtract GrBIAS[6:0]

Bit[6:0]:

Gr channel offset adjustment value

COML

Common Control L

Bit[7]:

Line interval adjustment. Interval adjustment value is in
COML[6:5] and FRARL[7:0] (see

"FRARL" on page 25

Disabled

Enabled

Bit[6:5]:

Line interval adjust value MSB 2 bits

Bit[4]:

Reserved

Bit[3:2]:

HSYNC timing end point adjustment MSB 2 bits

Bit[1:0]:

HSYNC timing start point adjustment MSB 2 bits

Table 11

Device Control Register List

Address

(Hex)

Register

Name

Default

(Hex)

R/W

Description

Version 1.3, September 15, 2003

Proprietary to OmniVision Technologies

mni

ision

FRARL

Line Interval Adjustment Value LSB 8 bits

The frame rate will be adjusted by changing the line interval. Each LSB
will add 2/1520 T

frame

in SXGA and 2/800 T

frame

in VGA mode to the

frame period.

RBIAS

R Channel Offset Manual Adjustment Value - effective only when
COMG[3] = 1 (see

"COMG" on page 19

Bit[7]:

Offset direction

Add RBIAS[6:0]

Subtract RBIAS[6:0]

Bit[6:0]:

R channel offset adjustment value

ADDVSL

VSYNC Pulse Width LSB 8 bits

Bit[7:0]:

Line periods added to VSYNC width. Default VSYNC
output width is 4 x t

line

. Each LSB count will add 1 x t

line

to the VSYNC active period.

ADDVSH

VSYNC Pulse width MSB 8 bits

Bit[7:0]:

Line periods added to VSYNC width. Default VSYNC
output width is 4 x t

line

. Each MSB count will add

256 x t

line

to the VSYNC active period.

YAVG

Luminance Average

This register will auto update when COMH[5] = 1 (see

"COMH" on

page 20

). Average Luminance is calculated from the B/Gb/Gr/R

channel average as follows:

(

BAVG

[7:0] +

GbAVG

[7:0] +

GrAVG

[7:0] +

RAVG

[7:0])/4

HSDY

HSYNC Position and Width Start Point Lower 8 bits

This register and COML[1:0] (see

"COML" on page 24

) define the

HSYNC start position, each LSB will shift HSYNC start point by 1 pixel
period.

HEDY

HSYNC Position and Width End Point Lower 8 bits

This register and COML[3:2] (see

"COML" on page 24

) define the

HSYNC start position, each LSB will shift HSYNC start point by 1 pixel
period.

Table 11

Device Control Register List

Address

(Hex)

Register

Name

Default

(Hex)

R/W

Description

Proprietary to OmniVision Technologies

Version 1.3, September 15, 2003

OV9625/OV9121

CMOS SXGA (1.3 MPixel) C

AMERA

HIP

mni

ision

COMM

(0Ffor

VGA)

Common Control M

Bit[7:6]:

Reserved

Bit[5]:

Vertical window end position LSB (MSBs in register
VEND[7:0] - see

"VEND" on page 23

)

Bit[4]:

Vertical window start position LSB (MSBs in register
VSTRT[7:0] - see

"VSTRT" on page 23

)

Bit[3:2]:

Horizontal window end position LSBs (MSBs in register
HREFST[7:0] - see

"HREFEND" on page 22

)

Bit[1:0]:

Horizontal window start position LSBs (MSBs in register
HREFST[7:0] - see

"HREFST" on page 22

)

Note: For maximum output window size of 1292x1024, value of this
register should be 0x0D.

CHLF

Current Control

Bit[7:6]:

Sensor current control
00:

Minimum

11:

Maximum

Bit[5]:

Sensor current range control
0:

CHLF[7:6] current control at normal range

CHLF[7:6] current at half range

Bit[4]:

Sensor current double ON/OFF
0:

Normal

Double current

Bit[3]:

Sensor buffer current control
0:

Normal

Half current

Bit[2]:

Column buffer current control
0:

Normal

Half current

Bit[1]:

Analog DSP current control
0:

Normal

Half current

Bit[0]:

ADC current control
0:

Normal

Half current

RSVD

Reserved

VBLM

Reference Voltage Control

VCHG

Sensor Precharge Voltage Control

Bit[7]:

Reserved

Bit[6:4]:

Sensor precharge voltage control
000: Lowest voltage
111: Highest voltage

Bit[3:0]:

Sensor array common reference control
000: Lowest voltage
111: Highest voltage

Table 11

Device Control Register List

Address

(Hex)

Register

Name

Default

(Hex)

R/W

Description

Version 1.3, September 15, 2003

Proprietary to OmniVision Technologies

mni

ision

ADC

ADC Reference Control

Bit[7:4]:

Reserved

Bit[3]:

ADC input signal range
0:

Input signal x 1

Input signal x 0.7

Bit[2:0]:

ADC range control
000: Minimum
111: Maximum

ACOM

Analog Common Control

Bit[7]:

Analog gain control
0:

Normal

Gain increase 1.5x

Bit[6]:

Analog black level calibration control
0:

Analog BLC ON

Analog BLC OFF

Bit[5:0]:

Reserved

NOTE: All other registers are factory-reserved. Please contact OmniVision Technologies for reference register settings.

Table 11

Device Control Register List

Address

(Hex)

Register

Name

Default

(Hex)

R/W

Description

Proprietary to OmniVision Technologies

Version 1.3, September 15, 2003

OV9625/OV9121

CMOS SXGA (1.3 MPixel) C

AMERA

HIP

mni

ision

Package Specifications

The OV9625/OV9121 uses a 48-pin ceramic package. Refer to

Figure 21

for package information and

Figure 22

for the array

center on the chip.

Figure 21 OV9625/OV9121 Package Specifications

Table 12

OV9625/OV9121 Package Dimensions

Dimensions

Millimeters (mm)

Inches (in.)

Package Size

14.22 + 0.30 / -0.13 SQ

.560 + .012 / - .005 SQ

Package Height

2.23 + 0.28

.088 + .011

Substrate Height

0.51 + 0.05

.020 + .002

Cavity Size

8.89 + 0.13 SQ

.350 + .005 SQ

Castellation Height

1.14 + 0.13

.045 + .005

Pin #1 Pad Size

0.51 x 2.16

.020 x .085

Pad Size

0.51 x 1.02

.020 x .040

Pad Pitch

1.02 + 0.08

.040 + .003

Package Edge to First Lead Center

1.524 + 0.25 / -0.13

.06 + .010 / - .005

End-to-End Pad Center-Center

11.18 + 0.13

.440 + .005

Glass Size

12.40 + 0.10 SQ / 13.00 + 0.10 SQ

.488 + .004 SQ / .512 + .004 SQ

Glass Height

0.55 + 0.05

.022 + .002

.022 ± .004

0.0287

Image

Plane

.001 to .005 TYP

.030 ± .002

.065 ± .007

.088 ± .011

.020 ± .002

.015 ± .002

.350 SQ ± .005

.430 SQ ± .005

.032 MIN

.560 SQ + .012 / - .005

Pin 1
Index

.06 + .010 / - .005

.085 TYP

R .0075

(48 PLCS)

R .0075

(4 CORNERS)

.040 TYP

.040 ± .003

.440 ± .005

.020 TYP

.488

.012 TYP
REF

± .004

Proprietary to OmniVision Technologies

Version 1.3, September 15, 2003

OV9625/OV9121

CMOS SXGA (1.3 MPixel) C

AMERA

HIP

mni

ision

Note:

All information shown herein is current as of the revision and publication date. Please refer
to the OmniVision web site

(http://www.ovt.com

) to obtain the current versions of all

documentation.

OmniVision Technologies, Inc. reserves the right to make changes to their products or to
discontinue any product or service without further notice (It is advisable to obtain current product
documentation prior to placing orders).

Reproduction of information in OmniVision product documentation and specifications is
permissible only if reproduction is without alteration and is accompanied by all associated
warranties, conditions, limitations and notices. In such cases, OmniVision is not responsible
or liable for any information reproduced.

This document is provided with no warranties whatsoever, including any warranty of
merchantability, non-infringement, fitness for any particular purpose, or any warranty
otherwise arising out of any proposal, specification or sample. Furthermore, OmniVision
Technologies Inc. disclaims all liability, including liability for infringement of any proprietary
rights, relating to use of information in this document. No license, expressed or implied, by
estoppels or otherwise, to any intellectual property rights is granted herein.

`OmniVision', `CameraChip' are trademarks of OmniVision Technologies, Inc. All other trade,
product or service names referenced in this release may be trademarks or registered trademarks of
their respective holders. Third-party brands, names, and trademarks are the property of their
respective owners.

For further information, please feel free to contact OmniVision at

info@ovt.com

OmniVision Technologies, Inc.
1341 Orleans Drive
Sunnyvale, CA USA
(408) 542-3000

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