QL2009

3.3V and 5.0V pASIC

2 FPGA

Combining Speed, Density, Low Cost and Flexibility

3-35

Ultimate Verilog/VHDL Silicon Solution

-Abundant, high-speed interconnect eliminates manual routing
-Flexible logic cell provides high efficiency and performance
-Design tools produce fast, efficient Verilog/VHDL synthesis

Speed, Density, Low Cost and Flexibility in One Device

-16-bit counter speeds exceeding 200 MHz
-9,000 usable ASIC gates, 16,000 usable PLD gates, 225 I/Os
-3-layer metal ViaLink

process for small die sizes

-100% routable and pin-out maintainable

Advanced Logic Cell and I/O Capabilities

-Complex functions (up to 16 inputs) in a single logic cell
-High synthesis gate utilization from logic cell fragments
-Full IEEE Standard JTAG boundary scan capability
-Individually-controlled input/feedback registers and OEs on all I/O pins

Other Important Family Features

-3.3V and 5.0V operation with low standby power
-I/O pin-compatibility between different devices in the same packages
-PCI compliant (at 5.0V), full speed 33 MHz implementations
-High design security provided by security fuses

... 9,000

usable ASIC gates,

225 I/O pins

672

Logic

Cells

pAS

I
C 2

QL2009

Block Diagram

Rev. C

pASIC 2

HIGHLIGHTS

QL2009

3-36

The QL2009 is a 9,000 usable ASIC gate,16,000 usable PLD gate member of
the pASIC 2 family of FPGAs. pASIC 2 FPGAs employ a unique combination
of architecture, technology, and software tools to provide high speed, high
usable density, low price, and flexibility in the same devices. The flexibility
and speed make pASIC 2 devices an efficient and high performance silicon
solution for designs described using HDLs such as Verilog and VHDL, as well
as schematics.

The QL2009 contains 672 logic cells. With 225 maximum I/Os, the QL2009
is available in 144-pin TQFP, 208-PQFP, and 256-pin PBGA packages.

Software support for the complete pASIC families, including the QL2009, is
available through three basic packages. The turnkey QuickWorks

package

provides the most complete FPGA software solution from design entry to logic
synthesis (by Synplicity, Inc.), to place and route, to simulation. The
QuickTools

and QuickChip

packages provide a solution for designers

who use Cadence, Mentor, Synopsys, Viewlogic, Veribest, or other third-party
tools for design entry, synthesis, or simulation.

Total of 225 I/O Pins

- 217 bidirectional input/output pins, PCI-compliant at 5.0V

in -1/-2 speed grades
- 4 high-drive input-only pins
- 4 high-drive input/distributed network pins

Four Low-Skew (less than 0.5ns) Distributed Networks

- Two array networks available to logic cell flip-flop clock, set, and

reset - each driven by an input-only pin

- Two global clock/control networks available to F1 logic input, and

logic cell flip-flop clock, set, reset; input and I/O register clock, reset,
enable; and output enable controls - each driven by an input-only pin, or
any input or I/O pin, or any logic cell output or I/O cell feedback

High Performance

- Input + logic cell + output delays under 6 ns
- Datapath speeds exceeding 225 MHz
- Counter speeds over 200 MHz

PRODUCT

SUMMARY

FEATURES

QL2009

3-38

PQFP 208 and TQFP 144 Pinout Table

208

144

Function

208

144

Function

208

144

Function

208

144

Function

208

144

Function

PQFP TQFP

I/O

GND

I/O

127

GND

169

117

I/O

128

I/O

170

118

I/O

129

171

119

I/O

130

ACLK / I

172

120

I/O

131

VCC

173

I/O

132

174

I/O

133

GCLK / I

175

121

I/O

134

VCC

176

I/O

135

I/O

177

122

GND

VCC

I/O

136

I/O

178

123

I/O

GND

137

I/O

179

124

I/O

GND

TDI

I/O

138

I/O

180

I/O

VCC

139

I/O

181

125

I/O

140

I/O

182

126

GND

I/O

141

I/O

183

127

I/O

100

I/O

142

I/O

184

128

I/O

GND

101

I/O

143

I/O

185

129

I/O

102

I/O

144

100

I/O

186

I/O

VCC

103

TRSTB

145

VCC

187

130

VCC

I/O

104

TMS

146

101

I/O

188

131

I/O

105

I/O

147

102

GND

189

132

I/O

106

I/O

148

103

I/O

190

I/O

GND

I/O

107

I/O

149

104

I/O

191

133

I/O

108

I/O

150

I/O

192

134

I/O

109

I/O

151

105

I/O

193

I/O

ACLK / I

I/O

110

I/O

152

106

I/O

194

135

I/O

VCC

I/O

111

I/O

153

I/O

195

136

I/O

112

I/O

154

107

I/O

196

I/O

GCLK / I

I/O

113

I/O

155

I/O

197

137

I/O

VCC

I/O

114

VCC

156

108

I/O

198

I/O

GND

115

I/O

157

109

TCK

199

138

GND

I/O

116

GND

158

110

STM

200

139

I/O

117

I/O

159

111

I/O

201

VCC

I/O

118

I/O

160

I/O

202

140

I/O

119

I/O

161

112

I/O

203

I/O

GND

120

I/O

162

113

I/O

204

141

I/O

121

I/O

163

GND

205

142

I/O

122

I/O

164

I/O

206

I/O

123

I/O

165

114

VCC

207

143

TDO

I/O

124

I/O

166

115

I/O

208

144

I/O

VCC

125

I/O

167

116

I/O

126

I/O

168

I/O

QL2009

3-40

PBGA 256 Pinout Table

256

Function

256

Function

256

Function

256

Function

256

Function

256

Function

PBGA

VSS

I/O

E19

I/O

ACLK / I

T17

I/O

V20

I/O

E20

I/O

T18

I/O

GCLK / I

T19

I/O

L17

VCC

T20

I/O

TDI

I/O

L18

I/O

VCC

L19

I/O

C10

I/O

F17

VCC

L20

I/O

C11

I/O

F18

I/O

VSS

I/O

C12

I/O

F19

I/O

A10

I/O

C13

I/O

F20

I/O

VCC

I/O

A11

I/O

C14

I/O

W10

I/O

A12

I/O

C15

I/O

M17

I/O

VSS

W11

I/O

A13

I/O

C16

I/O

M18

I/O

W12

I/O

A14

I/O

C17

I/O

M19

I/O

U10

VCC

W13

I/O

A15

I/O

C18

I/O

G17

I/O

M20

I/O

U11

I/O

W14

I/O

A16

I/O

C19

I/O

G18

I/O

U12

I/O

W15

I/O

A17

I/O

C20

I/O

G19

I/O

U13

VSS

W16

I/O

A18

I/O

G20

I/O

U14

I/O

W17

I/O

A19

TCK

I/O

VSS

U15

VCC

W18

I/O

A20

I/O

N17

VSS

U16

I/O

W19

I/O

TDO

VSS

I/O

N18

I/O

U17

VSS

W20

TRSTB

I/O

VSS

N19

I/O

U18

I/O

VCC

H17

VSS

N20

I/O

U19

I/O

H18

I/O

U20

I/O

VSS

H19

I/O

H20

I/O

D10

I/O

D11

VCC

I/O

P17

I/O

D12

I/O

P18

I/O

B10

I/O

D13

VSS

I/O

P19

I/O

B11

I/O

D14

I/O

J17

I/O

P20

I/O

Y10

I/O

B12

I/O

D15

VCC

J18

I/O

Y11

I/O

B13

I/O

D16

I/O

J19

I/O

Y12

I/O

B14

I/O

D17

VSS

J20

GCLK / I

I/O

V10

I/O

Y13

I/O

B15

I/O

D18

I/O

VCC

V11

I/O

Y14

I/O

B16

I/O

D19

I/O

R17

VCC

V12

I/O

Y15

I/O

B17

I/O

D20

I/O

R18

I/O

V13

I/O

Y16

I/O

B18

STM

I/O

VCC

R19

I/O

V14

I/O

Y17

I/O

B19

I/O

K17

R20

I/O

V15

I/O

Y18

I/O

B20

I/O

K18

ACLK / I

I/O

V16

I/O

Y19

I/O

K19

I/O

V17

I/O

Y20

I/O

E17

I/O

K20

I/O

V18

I/O

E18

I/O

V19

TMS

QL2009

3-41

PIN DESCRIPTIONS

Pin

Function

Description

TDI

Test Data In for JTAG

Hold HIGH during normal operation. Connect to
VCC if not used for JTAG.

TRSTB

Active low Reset for JTAG

Hold LOW during normal operation. Connect to
ground if not used for JTAG.

TMS

Test Mode Select for JTAG

Hold HIGH during normal operation. Connect to
VCC if not used for JTAG.

TCK

Test Clock for JTAG

Hold HIGH or LOW during normal operation.
Connect to VCC or ground if not used for JTAG.

TDO

Test data out for JTAG

Output that must be left unconnected if not used for JTAG.

STM

Special Test Mode

Must be grounded during normal operation.

I/ACLK

High-drive input and/or array
network driver

Can be configured as either or both.

I/GCLK

High-drive input and/or global
network driver

Can be configured as either or both.

High-drive input

Use for input signals with high fanout.

I/O

Input/Output pin

Can be configured as an input and/or output.

VCC

Power supply pin

Connect to 3.3V supply.

GND

Ground pin

Connect to ground.

pAS

I
C 2

ORDERING
INFORMATION

QL 2009 - 1 PQ208 C

QuickLogic

pASIC device

pASIC 2 device

part number

Speed Grade
X = quick
0 = fast
1 = faster
2 = fastest

Operating Range

C = Commercial
I = Industrial

Package Code

PF144 = 144-pin TQFP
PQ208 = 208-pin PQFP
PB256 = 256-pin PBGA

QL2009

3-42

ABSOLUTE MAXIMUM RATINGS

Supply Voltage .................... -0.5 to 7.0V

Storage Temperature................ -65

C to + 150

Input Voltage ............. -0.5 to VCC +0.5V

Lead Temperature ................................ 300

ESD Pad Protection ...................

2000V

DC Input Current ......................

20 mA

Latch-up Immunity ...................

200 mA

5 Volt

OPERATING RANGE

Symbol

Parameter

Industrial

Commercial

Unit

Min

Max

Min

Max

VCC

Supply Voltage

4.5

5.5

4.75

5.25

Ambient Temperature

-40

Case Temperature

-X Speed Grade

0.4

2.75

0.46

2.55

Delay Factor

-0 Speed Grade

0.4

2.00

0.46

1.85

-1 Speed Grade

0.4

1.61

0.46

1.50

-2 Speed Grade

0.4

1.35

0.46

1.25

DC CHARACTERISTICS over 5V operating range

Symbol

Parameter

Conditions

Min

Max

Unit

VIH

Input HIGH Voltage

2.0

VIL

Input LOW Voltage

0.8

IOH = -4 mA

3.7

VOH

Output HIGH Voltage

IOH = -24 mA/-16 mA [1]

2.4

IOH = -10

VCC-0.1

VOL

Output LOW Voltage

IOL = 24 mA/16 mA [1]

0.45

IOL = 10

0.1

Input Leakage Current

VI = VCC or GND

-10

IOZ

3-State Output Leakage Current

VI = VCC or GND

-10

Input Capacitance [2]

IOS

Output Short Circuit Current [3]

VO = GND

-15

-120

VO = VCC

210

ICC

D.C. Supply Current [4]

VI, VIO = VCC or GND

2 (typ)

Notes:

[1]

-24 mA IOH and 24 mA IOL apply only to -1/-2 commercial grade devices. These speed grades are

also PCI-compliant. All other devices have -16 mA IOH and 16 mA IOL specifications.

[2]

Capacitance is sample tested only.

[3]

Only one output at a time. Duration should not exceed 30 seconds.

[4]

For -0/-1/-2 commercial grade devices only. Maximum ICC is 20 mA for -X commercial grade
devices and 15mA for all industrial grade devices. For AC conditions, contact QuickLogic customer

engineering.

QL2009

3-43

3.3 Volt

OPERATING RANGE

Symbol

Parameter

Industrial

Commercial

Unit

Min

Max

Min

Max

VCC

Supply Voltage

3.0

3.6

3.0

3.6

Ambient Temperature

-40

-0 Speed Grade

0.56

2.74

0.61

2.65

Delay Factor

-1 Speed Grade

0.56

2.21

0.61

2.14

-2 Speed Grade

0.56

1.85

0.61

1.79

DC CHARACTERISTICS over 3.3V operating range

Notes:

[5]

Capacitance is sample tested only.

[6]

Only one output at a time. Duration should not exceed 30 seconds.

[7]

For commercial grade devices only. Maximum ICC is 5 mA for all industrial grade devices. For AC
conditions, contact QuickLogic customer engineering.

Symbol

Parameter

Conditions

Min

Max

Unit

VIH

Input HIGH Voltage

2.0

VIL

Input LOW Voltage

0.8

VOH

Output HIGH Voltage

IOH = -2.4 mA

2.4

IOH = -10

VCC-0.1

VOL

Output LOW Voltage

IOL = 4 mA

0.4

IOL = 10

0.1

IIH

Input High Current Sink
(for tolerance to 5V devices)

5.5V > VI > VCC

Input Leakage Current

VI = VCC or GND

-10

IOZ

3-State Output Leakage Current

VI = VCC or GND

-10

Input Capacitance [5]

IOS

Output Short Circuit Current [6]

VO = GND

-10

-70

VO = VCC

130

ICC

D.C. Supply Current [7]

VI, VIO = VCC or GND

0.5 (typ)

pAS

I
C 2

QL2009

3-44

AC CHARACTERISTICS at VCC = 5V, TA = 25

°
°

C (K = 1.00)

Propagation delays depend on routing, fanout, load capacitance, supply voltage, junction temperature,
and process variation. The AC Characteristics are a design guide to provide initial timing estimates at
nominal conditions. Worst case estimates are obtained when nominal propagation delays are multiplied
by the appropriate Delay Factor, K, as specified in the Delay Factor table (Operating Range). The
QuickChip/QuickTools/QuickWorks software incorporates data sheet AC Characteristics into the
design database for precise path analysis or simulation results following place and route.

Logic Cells

Input-Only Cells

Symbol

Parameter

Propagation Delays (ns)

Fanout [8]

tIN

High Drive Input Delay

2.5

2.6

2.7

3.5

4.6

5.8

tINI

High Drive Input, Inverting Delay

2.6

2.7

2.8

3.6

4.7

5.9

tISU

Input Register Set-Up Time

4.8

tIH

Input Register Hold Time

0.0

tlCLK

Input Register Clock To Q

0.9

1.0

1.1

1.9

3.0

4.2

tlRST

Input Register Reset Delay

0.8

0.9

1.0

1.8

2.9

4.1

tlESU

Input Register clock Enable Set-Up Time

4.1

tlEH

Input Register Clock Enable Hold Time

0.0

Notes:

[8]

Stated timing for worst case Propagation Delay over process variation at VCC=5.0V and TA=25

Multiply by the appropriate Delay Factor, K, for speed grade, voltage and temperature settings as
specified in the Operating Range.

[9]

These limits are derived from a representative selection of the slowest paths through the pASIC 2 logic
cell including typical net delays. Worst case delay values for specific paths should be determined from
timing analysis of your particular design.

Symbol

Parameter

Propagation Delays (ns)

Fanout [8]

tPD

Combinatorial Delay [9]

1.4

1.7

2.0

2.3

3.5

tSU

Setup Time [9]

1.8

Hold Time

0.0

tCLK

Clock to Q Delay

0.8

1.1

1.4

1.7

2.9

tCWHI

Clock High Time

2.0

tCWLO

Clock Low Time

2.0

tSET

Set Delay

1.4

1.7

2.0

2.3

3.5

tRESET

Reset Delay

1.2

1.5

1.8

2.1

3.3

tSW

Set Width

1.9

tRW

Reset Width

1.8

QL2009

3-45

Clock Cells

Symbol

Parameter

Propagation Delays (ns)

Loads per Half Column [10]

tACK

Array Clock Delay

2.2

2.3

2.4

2.5

2.6

tGCKP

Global Clock Pin Delay

1.2

tGCKB

Global Clock Buffer Delay

1.5

1.6

1.7

1.8

1.9

2.0

I/O Cells

Symbol

Parameter

Propagation Delays (ns)

Output Load Capacitance (pF)

100

150

tOUTLH

Output Delay Low to High

2.6

3.0

3.6

4.1

5.2

tOUTHL

Output Delay High to Low

2.8

3.3

3.9

4.5

5.7

tPZH

Output Delay Tri-state to High

2.1

2.6

3.1

3.7

4.8

tPZL

Output Delay Tri-state to Low

2.6

3.3

4.1

4.9

6.5

tPHZ

Output Delay High to Tri-State [11]

2.9

tPLZ

Output Delay Low to Tri-State [11]

3.3

Notes:

[10]

The array distributed networks consist of 48 half columns and the global distributed networks consist of
52 half columns, each driven by an independent buffer. The number of half columns used does not affect
clock buffer delay. The array clock has up to 10 loads per half column. The global clock has up to 13
loads per half column.

[11]

The following loads are used for tPXZ:

5 pF

tPHZ

tPLZ

Symbol

Parameter

Propagation Delays (ns)

Fanout [8]

tI/O

Input Delay (bidirectional pad)

1.8

2.1

2.4

2.7

3.9

4.6

tISU

Input Register Set-Up Time

4.8

tIH

Input Register Hold Time

0.0

tlOCLK

Input Register Clock To Q

0.8

1.1

1.4

1.7

2.9

3.6

tlORST

Input Register Reset Delay

0.7

1.0

1.3

1.6

2.8

3.5

tlESU

Input Register clock Enable Set-Up Time

4.1

tlEH

Input Register Clock Enable Hold Time

0.0

pAS

I
C 2

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ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: QL2009-2PQ208I