8-7

Military 5.0V pASIC 1 Family - Very-High-Speed CMOS FPGA

Military 5.0V pASIC 1 Family

Rev B

Military 5.0V pASIC 1 Family

Device Highlights

Very High Speed

ViaLink" metal-to-metal programmable technol-
ogy, allows counter speeds over 150 MHz and
logic cell delays of under 2 ns at 5V, and over 80
MHz at 3.3V operation.

High Usable Density

Up to a 24-by-32 array of 768 logic cells provides
22,000 usable PLD gates in 208-pin PQFP and
208-pin CQFP packages.

PCI-Output Drive

Fully PCI 2.1 compliant input/output capability.
(including drive current)

Features

Total of 180 I/O pins

-172 Bidirectional Input/Output pins

-6 Dedicated Input/High-Drive pins

-2 Clock/Dedicated input pins with fanout-
independent, low-skew clock networks

-PCI 2.1 Compliant I/Os

Input + logic cell + output delays under 6 ns

Chip-to-chip operating frequencies up to 110 MHz

Internal state machine frequencies up to 150 MHz

Clock skew < 0.5 ns

Input hysteresis provides high noise immunity

Built-in scan path permits 100% factory testing of
logic and I/O cells and functional testing with Auto-
matic Test Vector Generation (ATVG) software
after programming

208 pin PQFP pin for pin compatible with the
208 CQFP

0.65µ CMOS process with ViaLink programming
technology

TABLE 1: Selector Table

EVICE

IGHLIGHTS

EATURES

Device

ASIC

Gates

PLD

Gates

Package

Max

I/O

Qualification

Level

SMD

5962-

QL8x12B

1,000

2,000

68CPGA

QL12x16B

2,000

4,000

84CPGA

M, /883

96836

144CPGA

122

M, /883

95599

QL16x24B

4,000

7,000

160 CQFP

122

M, /883

95599

208CQFP

180

M, /883

96837

QL24x32B

8,000

14,000

208PQFP

180

M = Military Temperature (-55 to +125 degrees C)
/883 = MIL-STD-883 qualified

Preliminary

8-8

Military 5.0V pASIC 1 Family

Product Summary

The pASIC 1 Family is a very-high-speed CMOS
user-programmable ASIC devices. The 768 logic cell
field-programmable gate array (FPGA) features
22,000 usable PLD gates of high-performance gen-
eral-purpose logic in a 208-pin PQFP and CQFP
package.

Low-impedance, metal-to-metal, ViaLink intercon-
nect technology provides nonvolatile custom logic
capable of operating above 150 MHz. Logic cell
delays under 2 ns, combined with input delays of
under 1.5 ns and output delays under 3 ns, permit

high-density programmable devices to be used with
today's fastest microprocessors and DSPs.

Designs can be entered using QuickLogic's Quick-
Works Toolkit or most popular third-party CAE tools.
QuickWorks combines Verilog/VHDL design entry
and simulation tools with device-specific place &
route and programming software. Ample on-chip
routing channels allow fast, fully automatic place and
route of designs using up to 100% of the logic and I/
O cells, while maintaining fixed pin-outs.

Pinout Diagram 68-Pin CPGA

TABLE 2: CPGA 68 Function/Connector Pin Table

RODUCT

UMMARY

INOUT

IAGRAM

68-P

CPGA

PIN

FUNC

PIN

FUNC

PIN

FUNC

PIN

FUNC

B10

K10

A10

K11

J10

J11

H10

H11

I/(SCLK)

I/(SI)

G10

I/CLK/(SM)

I/CLK

G11

VCC

GND

VCC

F10

GND

F11

I/(SO)

E10

E11

D10

D11

C10

C11

L10

B11

8-9

Military 5.0V pASIC 1 Family

Pinout Diagram 84-pin CPGA

TABLE 3: CPGA 84 Function/Connector Pin Table

INOUT

IAGRAM

84-P

CPGA

PIN

FUNC

PIN

FUNC

PIN

FUNC

PIN

FUNC

B10

K10

J10

A10

K11

J11

H10

H11

G11

GND

G10

I/(SCLK)

I/(SI)

F11

I/CLK/(SM)

I/CLK

F10

I(P)

I/(SO)

E11

VCC

E10

D11

D10

C11

L10

B11

C10

L11

A11

Preliminary

8-10

Military 5.0V pASIC 1 Family

Pinout Diagram 144-pin CPGA

TABLE 4: CPGA 144 Function/Connector Table

(Cont'd on next page)

INOUT

IAGRAM

144-P

CPGA

PIN

FUNC

PIN

FUNC

PIN

FUNC

PIN

FUNC

B15

R14

C14

P13

D13

N12

C15

R13

D14

P12

E13

VCC

R12

VCC

D15

N13

VCC

E14

P11

E15

R11

F13

N10

F14

P10

F15

R10

G15

C13

GND

G14

N11

GND

H15

I/(SCLK)

H14

I/(SI)

I/CLK/(SM)

G13

GND

I/CLK

GND

VCC

H13

VCC

I/(P)

J15

J14

I/(SO)

C11

VCC

J13

VCC

A10

K15

A11

L15

B10

K14

8-11

Military 5.0V pASIC 1 Family

CPGA 144 Function/Connector Table (Cont'd)

A12

M15

B11

L14

C10

K13

A13

N15

GND

L13

GND

B12

M14

A14

P15

B13

N14

C12

M13

A15

R15

B14

P14

INOUT

IAGRAM

160-P

CPGA

QL16x24B-1CF160M

8-13

Military 5.0V pASIC 1 Family

PQFP/CQFP 208 Function/Connector Table

PQFP/CQFP 208

UNCTION

CONNECTOR

ABLE

FUN

I/O

VCC

I/O

105

I/O

131

VCC

157

I/O

183

I/O

I/P

I/O

106

I/O

132

158

I/O

184

I/O

107

I/O

133

I/SO

159

I/O

185

I/O

VCC

I/O

108

I/O

134

VCC

160

I/O

186

I/O

VCC

109

I/O

135

I/O

161

I/O

187

VCC

I/O

110

I/O

136

I/O

162

I/O

188

I/O

GND

I/O

111

I/O

137

I/O

163

GND

189

I/O

112

I/O

138

I/O

164

I/O

190

I/O

VCC

I/O

113

I/O

139

I/O

165

VCC

191

I/O

VCC

I/O

114

VCC

140

I/O

166

I/O

192

I/O

115

I/O

141

I/O

167

I/O

193

I/O

GND

I/O

116

GND

142

I/O

168

I/O

194

I/O

117

I/O

143

I/O

169

I/O

195

I/O

118

I/O

144

I/O

170

I/O

196

I/O

VCC

I/O

119

I/O

145

VCC

171

I/O

197

I/O

120

I/O

146

I/O

172

I/O

198

I/O

GND

I/O

GND

121

I/O

147

GND

173

I/O

199

GND

I/O

122

I/O

148

I/O

174

I/O

200

I/O

VCC

123

I/O

149

I/O

175

I/O

201

VCC

I/O

124

I/O

150

I/O

176

I/O

202

I/O

GND

I/O

125

I/O

151

I/O

177

GND

203

I/O

100

I/O

126

I/O

152

I/O

178

I/O

204

I/O

GND

I/O

101

I/O

127

GND

153

I/O

179

I/O

205

I/O

102

I/O

128

I/O

154

I/O

180

I/O

206

I/O

I/Sck

I/O

103

I/O

129

I/SI

155

I/O

181

I/O

207

I/O

I/Clk

I/O

GND

104

I/O

130

I/Clk

156

I/O

182

GND

208

I/O

Preliminary

8-14

Military 5.0V pASIC 1 Family

ABSOLUTE MAXIMUM RATINGS

Supply Voltage ........................-0.5 to 7.0V
Input Voltage................ -0.5 to VCC +0.5V
ESD Pad Protection

.................... ±

2000V

DC Input Current

.......................±20 mA

Latch-up Immunity

.................. ±200 mA

Storage Temperature .......-65

C to +150

Lead Temperature ...........................300

5 Volt OPERATING RANGE

DC CHARACTERISTICS over 5V operating range

Notes:

[1] Capacitance is sample tested only. CI = 20 pF max on I/(SI).

[2] Only one output at a time. Duration should not exceed 30 seconds.

[3] Maximum Icc for military grade is 20 mA. For AC conditions use the formula described in the databook,

Section 9 - Power vs Operating Frequency.

[4] Stated timing for worst case Propagation Delay over process variation at VCC = 5.0V and TA = 25

°C. Mul-

tiply by the appropriate Delay Factor, K, for speed grade, voltage and temperature settings as specified in the
Operating Range.

[5] These limits are derived from a representative selection of the slowest paths through the pASIC logic cell

including net delays. Worst case delay values for specific paths should be determined from timing analysis
of your particular design.

Symbol

Parameter

Military

Unit

Min

Max

VCC

Supply Voltage

4.5

5.5

Ambient Temperature

-55

Case Temperature

125

Delay Factor

-0 Speed Grade

0.39

1.82

-1 Speed Grade

0.39

1.56

Symbol

Parameter

Conditions

Min

Max

Unit

VIH

Input HIGH Voltage

2.0

VIL

Input LOW Voltage

0.8

IOH = -4 mA

3.7

VOH

Output HIGH Voltage

IOH = 16 mA

2.4

IOH = -10

VCC-0.1

VOL

Output LOW Voltage

IOL = 8 mA

0.4

IOL = 10

0.1

Input Leakage Current

VI = VCC or GND

-10

IOZ

3-State Output Leakage Current

VI = VCC or GND

-10

Input Capacitance [1]

IOS

Output Short Circuit Current [2]

VO = GND

-10

-90

VO = VCC

160

ICC

D.C. Supply Current [3]

VI, VIO = VCC or GND

8-15

Military 5.0V pASIC 1 Family

QL8X12B

AC CHARACTERISTICS at VCC = 5V, TA = 25

°C (K = 1.00)

Logic Cell

Input Cells

Output Cell

Notes:

[6] See High Drive Buffer Table for more information.

[7] Clock buffer fanout refers to the maximum number of flip flops per half column. The number of half

columns used does not affect clock buffer delay.

[8] The following loads are used for tPXZ:

QL8

12B

Propagation Delays (ns)

Symbol

Parameter

Fanout

tPD

Combinatorial Delay [5]

1.7

2.1

2.6

3.0

4.8

tSU

Setup Time [5]

2.1

Hold Time

0.0

tCLK

Clock to Q Delay

1.0

1.5

1.9

2.3

4.2

tCWHI

Clock High Time

2.0

tCWLO

Clock Low Time

2.0

tSET

Set Delay

1.7

2.1

2.6

3.0

4.8

tRESET

Reset Delay

1.5

1.8

2.2

2.5

3.9

tSW

Set Width

1.9

tRW

Reset Width

1.8

Symbol

Parameter

Propagation Delays (ns) [4]

tIN

High Drive Input Delay [6]

2.1

2.2

2.3

2.4

2.6

2.9

tINI

High Drive Input, Inverting Delay [6]

2.1

2.2

2.3

2.5

2.8

3.1

tIO

Input Delay (bidirectional pad)

1.4

1.8

2.2

2.6

3.4

4.2

tGCK

Clock Buffer Delay [7]

2.7

2.8

2.9

3.0

tGCKHI

Clock Buffer Min High [7]

2.0

tGCKLO

Clock Buffer Min Low [7]

2.0

Propagation Delays (ns) [4]

Symbol

Parameter

Output Load Capacitance (pF)

100

150

tOUTLH

Output Delay Low to High

2.7

3.4

4.2

5.0

6.7

tOUTHL

Output Delay High to Low

2.8

3.7

4.7

5.6

7.6

tPZH

Output Delay Tri-state to High

4.0

4.9

6.1

7.3

9.7

tPZL

Output Delay Tri-state to Low

3.6

4.2

5.0

5.8

7.3

tPHZ

Output Delay High to Tri-state [8]

2.9

tPLZ

Output Delay Low to Tri-state [8]

3.3

Preliminary

8-16

Military 5.0V pASIC 1 Family

High Drive Buffer

[4] Stated timing for worst case Propagation Delay over process variation at VCC = 5.0V and TA = 25

°C.

Multiply by the appropriate Delay Factor, K, for speed grade, voltage and temperature settings as
specified in the Operating Range.

Clock Drivers

Propagation Delays (ns) [4]

Symbol

Parameter

Wired Together

Fanout

4.0

4.9

tIN

High Drive Input Delay

3.5

5.0

4.0

4.8

5.6

4.1

4.8

4.2

5.1

tINI

High Drive Input,

3.7

5.2

Inverting Delay

4.2

5.0

5.8

4.3

5.0

8-17

Military 5.0V pASIC 1 Family

QL12x16B

AC CHARACTERISTICS at VCC = 5V, TA = 25

°C (K = 1.00)

Logic Cell

Input Cells

Output Cell

Notes:

[6] See High Drive Buffer Table for more information.

[7] Clock buffer fanout refers to the maximum number of flip flops per half column. The number of half col-

umns used does not affect clock buffer delay.

[8] The following loads are used for tPXZ:

QL12

16B

Propagation Delays (ns)

Symbol

Parameter

Fanout

tPD

Combinatorial Delay [5]

1.7

2.2

2.6

3.2

5.2

tSU

Setup Time [5]

2.1

Hold Time

0.0

tCLK

Clock to Q Delay

1.0

1.5

1.9

2.5

4.6

tCWHI

Clock High Time

2.0

tCWLO

Clock Low Time

2.0

tSET

Set Delay

1.7

2.1

2.6

3.2

5.2

tRESET

Reset Delay

1.5

1.9

2.2

2.7

4.3

tSW

Set Width

1.9

tRW

Reset Width

1.8

Symbol

Parameter

Propagation Delays (ns) [4]

tIN

High Drive Input Delay [6]

2.4

2.5

2.6

2.7

3.0

3.3

tINI

High Drive Input, Inverting Delay [6]

2.5

2.6

2.7

2.8

3.1

3.4

tIO

Input Delay (bidirectional pad)

1.4

1.9

2.2

2.8

3.7

4.6

tGCK

Clock Buffer Delay [7]

2.7

2.8

2.9

3.0

tGCKHI

Clock Buffer Min High [7]

2.0

tGCKLO

Clock Buffer Min Low [7]

2.0

Propagation Delays (ns) [4]

Symbol

Parameter

Output Load Capacitance (pF)

100

150

tOUTLH

Output Delay Low to High

2.7

3.4

4.2

5.0

6.7

tOUTHL

Output Delay High to Low

2.8

3.7

4.7

5.6

7.6

tPZH

Output Delay Tri-state to High

4.0

4.9

6.1

7.3

9.7

tPZL

Output Delay Tri-state to Low

3.6

4.2

5.0

5.8

7.3

tPHZ

Output Delay High to Tri-state [8]

2.9

tPLZ

Output Delay Low to Tri-state [8]

3.3

Preliminary

8-18

Military 5.0V pASIC 1 Family

High Drive Buffer

[4] Stated timing for worst case Propagation Delay over process variation at VCC = 5.0V and TA = 25

°C.

Multiply by the appropriate Delay Factor, K, for speed grade, voltage and temperature settings as
specified in the Operating Range.

Clock Drivers

Propagation Delays (ns) [4]

Symbol

Parameter

Wired Together

Fanout

4.5

5.4

tIN

High Drive Input Delay

3.9

5.6

4.5

5.3

6.3

4.6

5.3

4.7

5.6

tINI

High Drive Input,

4.0

5.8

Inverting Delay

4.6

5.5

6.4

4.8

5.5

8-19

Military 5.0V pASIC 1 Family

QL16x24B

AC CHARACTERISTICS at VCC = 5V, TA = 25

°C (K = 1.00)

Logic Cell

Input Cells

Output Cell

Notes:

[6] See High Drive Buffer Table for more information.

[7] Clock buffer fanout refers to the maximum number of flip flops per half column. The number of half col-

umns used does not affect clock buffer delay.

[8] The following loads are used for tPXZ:

QL16

24B

Propagation Delays (ns)

Symbol

Parameter

Fanout

tPD

Combinatorial Delay [5]

1.7

2.2

2.6

3.2

5.3

tSU

Setup Time [5]

2.1

Hold Time

0.0

tCLK

Clock to Q Delay

1.0

1.5

1.9

2.6

4.7

tCWHI

Clock High Time

2.0

tCWLO

Clock Low Time

2.0

tSET

Set Delay

1.7

2.2

2.6

3.2

5.3

tRESET

Reset Delay

1.5

1.9

2.2

2.7

4.4

tSW

Set Width

1.9

tRW

Reset Width

1.8

Symbol

Parameter

Propagation Delays (ns) [4]

tIN

High Drive Input Delay [6]

2.8

2.9

3.0

3.1

4.0

5.3

tINI

High Drive Input, Inverting Delay [6]

3.0

3.1

3.2

3.3

4.1

5.7

tIO

Input Delay (bidirectional pad)

1.4

1.9

2.2

2.9

4.7

6.5

tGCK

Clock Buffer Delay [7]

2.7

2.8

2.9

3.0

3.1

3.3

tGCKHI

Clock Buffer Min High [7]

2.0

tGCKLO

Clock Buffer Min Low [7]

2.0

Propagation Delays (ns) [4]

Symbol

Parameter

Output Load Capacitance (pF)

100

150

tOUTLH

Output Delay Low to High

2.7

3.4

4.2

5.0

6.7

tOUTHL

Output Delay High to Low

2.8

3.7

4.7

5.6

7.6

tPZH

Output Delay Tri-state to High

4.0

4.9

6.1

7.3

9.7

tPZL

Output Delay Tri-state to Low

3.6

4.2

5.0

5.8

7.3

tPHZ

Output Delay High to Tri-state [8]

2.9

tPLZ

Output Delay Low to Tri-state [8]

3.3

Preliminary

8-20

Military 5.0V pASIC 1 Family

High Drive Buffer

[4] Stated timing for worst case Propagation Delay over process variation at VCC = 5.0V and TA = 25

°C.

Multiply by the appropriate Delay Factor, K, for speed grade, voltage and temperature settings as spec-
ified in the Operating Range.

Clock Drivers

Propagation Delays (ns) [4]

Symbol

Parameter

Wired Together

Fanout

5.3

6.7

tIN

High Drive Input Delay

4.5

6.6

5.3

6.2

7.2

5.4

6.2

5.7

7.2

tINI

High Drive Input,

4.6

6.8

Inverting Delay

5.5

6.4

7.4

5.6

6.4

8-21

Military 5.0V pASIC 1 Family

QL24x32B

AC CHARACTERISTICS at VCC = 5V, TA = 25

°C (K = 1.00)

Logic Cell

Input Cells

Output Cell

Notes:

[6] See High Drive Buffer Table for more information.

[7] Clock buffer fanout refers to the maximum number of flip flops per half column. The number of

half columns used does not affect clock buffer delay.

[8] The following loads are used for tPXZ:

QL24

32B

Propagation Delays (ns)

Symbol

Parameter

Fanout

tPD

Combinatorial Delay [5]

1.7

2.1

2.7

3.3

5.5

tSU

Setup Time [5]

2.1

Hold Time

0.0

tCLK

Clock to Q Delay

1.0

1.5

1.9

2.7

4.9

tCWHI

Clock High Time

2.0

tCWLO

Clock Low Time

2.0

tSET

Set Delay

1.7

2.2

2.7

3.3

5.5

tRESET

Reset Delay

1.5

1.9

2.3

2.8

4.6

tSW

Set Width

1.9

tRW

Reset Width

1.8

Symbol

Parameter

Propagation Delays (ns) [4]

tIN

High Drive Input Delay [6]

3.1

3.2

3.3

3.4

4.4

5.8

6.5

tINI

High Drive Input, Inverting Delay [6]

3.3

3.4

3.5

3.6

4.6

6.0

6.7

tIO

Input Delay (bidirectional pad)

1.4

1.9

2.3

3.0

4.8

6.7

8.5

tGCK

Clock Buffer Delay [7]

2.7

2.8

2.9

3.0

3.1

3.3

3.4

tGCKHI

Clock Buffer Min High [7]

2.0

tGCKLO

Clock Buffer Min Low [7]

2.0

Propagation Delays (ns) [4]

Symbol

Parameter

Output Load Capacitance (pF)

100

150

tOUTLH

Output Delay Low to High

2.7

3.3

3.8

4.3

5.4

tOUTHL

Output Delay High to Low

2.8

3.6

4.5

5.3

6.9

tPZH

Output Delay Tri-state to High

2.1

2.6

3.1

3.7

4.8

tPZL

Output Delay Tri-state to Low

2.6

3.3

4.1

4.9

6.5

tPHZ

Output Delay High to Tri-state [8]

2.9

tPLZ

Output Delay Low to Tri-state [8]

3.3

Preliminary

8-22

Military 5.0V pASIC 1 Family

High Drive Buffer

[4] Stated timing for worst case Propagation Delay over process variation at VCC = 5.0V and TA =

°C. Multiply by the appropriate Delay Factor, K, for speed grade, voltage and temperature set-

tings as specified in the Operating Range.

AC Performance

Propagation delays depend on routing, fanout, load
capacitance, supply voltage, junction temperature,
and process variation. The AC Characteristics are a
design guide to provide initial timing estimates at
nominal conditions. Worst case estimates are
obtained when nominal propagation delays are multi-
plied by the appropriate Delay Factor, K, as specified
in the Delay Factor table (Operating Range). The

effects of voltage and temperature variation are illus-
trated in the graphs on the following pages, K Factor
versus Voltage and Temperature. The pASIC Devel-
opment Tools incorporate data sheet AC Character-
istics into the QDIF database for pre-place-and-route
timing analysis. The SpDE Delay Modeler extracts
specific timing parameters for precise path analysis
or simulation results following place and route.

ORDERING INFORMATION

Clock Drivers

Propagation Delays (ns) [4]

Symbol

Parameter

Wired Together

Fanout

5.8

7.2

tIN

High Drive Input Delay

5.0

7.1

5.8

6.7

7.7

5.9

6.8

6.0

7.4

tINI

High Drive Input,

5.2

7.3

Inverting Delay

6.0

6.9

7.9

6.1

7.0

QL 24x32B - 1 CF208 M

QuickLogic

pASIC device

pASIC device part number

B = 0.65 micron CMOS

8x12B

12x16B
16x24B
24x32B

Operating Range

M = Military
M/883C = MIL STD 883

Package Code
CG68 = 68-pin CPGA

CG84 = 84-pin CPGA
CG144 = 144-pin CPGA
CF160 = 160-pin CQFD

PQ208 = 208-pin PQFP
CF208 = 208-pin CQFP

Speed Grade
0 = fast
1 = faster

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: QL24X32B-CG144M883C

Document Outline

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: QL24X32B-CG144M883C

Document Outline

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: QL24X32B-CG144M883C