90,000 Usable PLD Gate QuickRAM Combining Performance, Density and Embedded RAM

Military QuickRAM

Rev A

Military QuickRAM

Device Highlights

High Performance and High Density

Up to 90,000 Usable PLD Gates with 316 I/Os

300 MHz 16-bit Counters, 400 MHz Datapaths, 160+
MHz FIFOs

0.35um four-layer metal non-volatile CMOS process for
smallest die sizes

High Speed Embedded SRAM

Up to 22 dual-port RAM modules, organized in user-
configurable 1,152-bit blocks

5ns access times, each port independently accessible

Fast and efficient for FIFO, RAM, and ROM functions

Easy to Use / Fast Development Cycles

100% routable with 100% utilization and complete
pin-out stability

Variable-grain logic cells provide high performance and
100% utilization

Comprehensive design tools include high quality Verilog/
VHDL synthesis

Advanced I/O Capabilities

Interfaces with both 3.3 volt and 5.0 volt devices

PCI compliant with 3.3V and 5.0V buses for -1/-2
speed grades

Full JTAG boundary scan

Registered I/O cells with individually controlled clocks
and output enables

Features

Total of 316 I/O pins

308 bi-directional input/output pins, PCI-compliant for

5.0 volt and 3.3 volt buses for -1/-2/-3/-4 speed grades

8 high-drive input/distributed network pins

Eight Low-Skew Distributed Networks

Two array clock/control networks available to the logic
cell flip-flop clock, set and reset inputs - each driven by
an input-only pin

Six global clock/control networks available to the logic
cell F1, clock, set and reset inputs and the input and I/O
register clock, reset and enable inputs as well as the
output enable control - each driven by an input-only or
I/O pin, or any logic cell output or I/O cell feedback

High Performance

Input + logic cell + output total delays under 6 ns

Data path speeds exceeding 400 MHz

Counter speeds over 300 MHz

FIFO speeds over 160+ MHz

Military Reliability

Mil-STD-883 and Miil Temp Ceramic

Mil Temp Plastic - Guaranteed -55

C to 125

TABLE 1: Selector Table

EVICE

IGHLIGHTS

EATURES

Device

Usable

Gates

Package

Max

I/O

Qualification

Level

Supply

Voltage

QL4016
11,520 RAM Bits

8,000-

16,000

84CPGA

84PLCC

100CQFP

70
70
82

M, /883

3.3 V
3.3 V
3.3 V

QL4036
16,128 RAM bits

16,000-

25,000

144CPGA

208PQFP
208CQFP

118
174
174

M, /883

3.3 V
3.3 V
3.3 V

QL4090
25,344 RAM bits

36,000-

60,000

208PQFP
208CQFP
240PQFP

256CPGA
456PBGA

174
174
207
223
316

M, /883

3.3V
3.3V
3.3V
3.3V
3.3V

M = Military Temperature (-15 to +125 degrees C)
/888 = MIL STD 883

Preliminary

8-38

Military QuickRAM

Rev A

Product Summary

The QuickRAM family of ESPs (Embedded Standard
Products) offers FPGA logic in combination with
Dual-Port SRAM modules. QuickRAM is a 90,000
usable PLD gate ESPs. QuickRAM ESPs are fabri-
cated on a 0.35mm four-layer metal process using
QuickLogic's patented ViaLink technology to provide
a unique combination of high performance, high
density, low cost, and extreme ease-of-use.

QuickRAM contains up to 1,584 logic cells and 22
dual port RAM modules. Each RAM module has
1,152 RAM bits, for a total of up to 25,344 bits.
RAM Modules are Dual Port (one read port, one
write port) and can be configured into one of four
modes: 64 (deep) x18 (wide), 128x9, 256x4, or
512x2. With a maximum of 316 I/Os, and is avail-

able in plastic 84-PLCC, 208-PQFP, 240-PQFP and
456-PBGA packages and in ceramic 100, 208-
CQFP and 84, 144, 256-CPGA.

Software support for the complete QuickRAM family
is available through two basic packages. The turnkey
QuickWorks

package provides the most complete

ESP software solution from design entry to logic syn-
thesis, to place and route, to simulation. The Quick-
Tools

for Workstations package provides a solution

for designers who use Cadence, Exemplar, Mentor,
Synopsys, Synplicity, Viewlogic, Veribest, or other
third-party tools for design entry, synthesis, or simu-
lation.

Pinout Diagram 84-Pin PLCC

TABLE 2: 84-pin PLCC

RODUCT

UMMARY

INOUT

IAGRAM

84-P

PLCC

QuickRAM

QL4016-1PL84M

8-39

Military QuickRAM

Rev A

Pinout Diagram 100-Pin CQFP

100 CQFP Pinout Table

QuickRAM

QL4016-1CF100M

Pin #1

Pin #76

Pin #26

Pin #51

INOUT

IAGRAM

100-P

CQFP

100

TQFP

Function

100

TQFP

Function

100

TQFP

Function

100

TQFP

Function

I/O

TDI

I/O

TCK

I/O

STM

I/O

GND

I/O

GND

I/O

GND

I/O

GND

GCLK / I

I/O

GCLK / I

I/O

ACLK / I

I/O

ACLK / I

I/O

VCC

GND

VCC

GND

GCLK / I

I/O

GCLK / I

I/O

GCLK / I

I/O

GCLK / I

I/O

VCC

I/O

VCC

I/O

VCCIO

I/O

VCCIO

I/O

TRSTB

I/O

TMS

I/O

100

TDO

8-41

Military QuickRAM

Rev A

PQFP/CQFP 240/208 Pinout Table

INOUT

ABLE

INOUT

ABLE

240

208

Function

240

208

Function

240

208

Function

240

208

Function

240

208

Function

PQFP PQFP

208

I/O

GND

I/O

145

125

I/O

194

168

I/O

146

126

I/O

195

169

I/O

100

I/O

147

127

GND

196

I/O

101

I/O

148

128

I/O

197

170

I/O

102

I/O

149

I/O

198

171

I/O

103

I/O

150

129

GCLK / I

199

172

I/O

104

I/O

151

130

ACLK / I

200

173

I/O

105

I/O

152

131

VCC

201

174

I/O

106

I/O

153

132

GCLK / I

202

175

I/O

107

I/O

154

133

GCLK / I

203

I/O

108

I/O

155

134

VCC

204

176

I/O

VCC

I/O

109

I/O

156

135

I/O

205

177

GND

I/O

TDI

110

GND

157

136

I/O

206

178

I/O

GND

I/O

158

I/O

207

179

I/O

111

VCC

159

137

I/O

208

I/O

160

GND

209

180

I/O

161

138

I/O

210

181

I/O

112

100

I/O

162

139

I/O

211

182

GND

I/O

113

I/O

163

140

I/O

212

VCC

I/O

114

101

I/O

164

141

I/O

213

183

I/O

GND

115

I/O

165

142

I/O

214

184

I/O

116

102

I/O

166

I/O

215

185

I/O

VCC

117

I/O

167

143

I/O

216

186

I/O

118

I/O

168

144

I/O

217

187

VCCIO

I/O

119

103

TRSTB

169

145

VCC

218

188

I/O

120

104

TMS

170

I/O

219

I/O

GND

I/O

121

105

I/O

171

146

I/O

220

189

I/O

122

I/O

172

147

GND

221

190

I/O

GCLK / I

I/O

123

106

I/O

173

148

I/O

222

191

I/O

ACLK / I

I/O

124

107

I/O

174

149

I/O

223

192

I/O

VCC

I/O

125

108

I/O

175

150

I/O

224

193

I/O

GCLK / I

I/O

126

109

I/O

176

151

I/O

225

194

I/O

GCLK / I

I/O

127

I/O

177

152

I/O

226

I/O

VCC

I/O

128

110

I/O

178

153

I/O

227

195

I/O

129

111

I/O

179

154

I/O

228

196

I/O

130

112

I/O

180

155

I/O

229

197

I/O

GND

I/O

131

113

I/O

156

I/O

230

198

I/O

132

114

VCC

181

157

TCK

231

I/O

GND

133

115

I/O

182

158

STM

232

199

GND

I/O

134

116

GND

183

I/O

233

200

I/O

VCC

135

117

I/O

184

159

I/O

234

201

VCC

I/O

136

I/O

185

160

I/O

235

202

I/O

137

118

I/O

186

161

I/O

236

203

I/O

138

119

I/O

187

162

I/O

237

204

I/O

GND

139

120

I/O

188

163

GND

238

205

I/O

140

121

I/O

189

164

I/O

239

206

I/O

141

I/O

190

165

VCC

240

207

TDO

I/O

142

122

I/O

191

166

I/O

VCC

I/O

143

123

I/O

192

I/O

VCCIO

144

124

I/O

193

167

I/O

Preliminary

8-42

Military QuickRAM

Rev A

Pinout Diagram 84-Pin CPGA

84-Pin CPGA Pinout Table

INOUT

IAGRAM

84-P

CPGA

84 CPGA

Function

84 CPGA

Function

84 CPGA

Function

84 CPGA

Function

I/O

B11

I/O

VCC

F10

I/O

F11

I/O

VCC

I/O

GCLK / I

I/O

ACLK / I

I/O

GCLK / I

I/O

GND

VCCIO

GCLK / I

I/O

C10

I/O

GND

I/O

C11

I/O

G10

I/O

G11

I/O

K10

TCK

A10

I/O

K11

I/O

A11

TDO

D10

I/O

TMS

I/O

D11

I/O

H10

VCC

I/O

TDI

I/O

H11

I/O

GND

TRSTB

I/O

GCLK / I

VCCIO

GND

I/O

GCLK / I

E10

I/O

ACLK / I

I/O

GCLK / I

E11

I/O

VCC

I/O

J10

STM

I/O

J11

I/O

L10

I/O

B10

I/O

L11

I/O

QuickRAM

QL4016-1CG84M

Preliminary

8-44

Military QuickRAM

Rev A

Pinout Table 144-Pin CPGA

INOUT

ABLE

144-P

CPGA

144

CPGA

Function

144

CPGA

Function

144

CPGA

Function

144

CPGA

Function

I/O

H13

ACLK / I

N10

I/O

GND

H14

I/O

N11

GND

I/O

H15

GCLK / I

N12

I/O

C10

I/O

GCLK / I

N13

I/O

C11

I/O

VCC

N14

I/O

C12

TCK

VCC

N15

I/O

C13

I/O

J13

I/O

C14

I/O

J14

I/O

C15

I/O

J15

GND

TDI

A10

GND

I/O

GCLK / I

I/O

A11

I/O

A12

I/O

A13

VCC

D13

I/O

K13

I/O

A14

I/O

D14

I/O

K14

I/O

A15

I/O

D15

I/O

K15

I/O

VCCIO

I/O

P10

I/O

TDO

VCC

I/O

P11

I/O

GND

P12

I/O

E13

GND

L13

I/O

P13

I/O

E14

I/O

L14

VCC

P14

TRSTB

I/O

E15

I/O

L15

I/O

P15

I/O

VCCIO

I/O

VCC

B10

I/O

F13

I/O

M13

I/O

B11

I/O

F14

I/O

M14

I/O

B12

I/O

F15

GCLK / I

M15

I/O

GND

B13

STM

GND

I/O

B14

I/O

B15

I/O

G13

VCC

I/O

R10

I/O

G14

VCC

I/O

R11

I/O

G15

GCLK / I

I/O

R12

I/O

GCLK / I

I/O

R13

I/O

GND

I/O

GND

R14

I/O

ACLK / I

I/O

R15

TMS

8-45

Military QuickRAM

Rev A

Pinout Table 256-Pin CPGA

256

CPGA

Function

256

CPGA

Function

256

CPGA

Function

256

CPGA

Function

256

CPGA

Function

256

CPGA

Function

VCC

I/O

E19

I/O

GCLK / I

T17

I/O

V20

I/O

E20

VCC

GND

T18

I/O

VCC

I/O

T19

I/O

GND

L17

GCLK / I

T20

I/O

L18

I/O

L19

VCC

I/O

GND

I/O

C10

I/O

F17

I/O

L20

ACLK / I

I/O

C11

VCC

F18

GND

VCC

I/O

C12

I/O

F19

I/O

A10

GND

C13

I/O

F20

I/O

A11

I/O

C14

I/O

W10

I/O

A12

I/O

C15

I/O

M17

I/O

W11

GND

A13

I/O

C16

I/O

M18

I/O

W12

I/O

A14

I/O

C17

I/O

M19

I/O

U10

VCC

W13

VCCIO

A15

I/O

C18

I/O

G17

I/O

M20

I/O

U11

I/O

W14

I/O

A16

I/O

C19

I/O

G18

I/O

U12

I/O

W15

I/O

A17

I/O

C20

I/O

G19

I/O

U13

I/O

W16

I/O

A18

GND

VCC

G20

I/O

U14

I/O

W17

I/O

A19

I/O D2

I/O

U15

I/O

W18

I/O

A20

TCK

I/O

N17

I/O

U16

I/O

W19

TRSTB

I/O

N18

I/O

U17

I/O

W20

I/O

N19

I/O

U18

I/O

TDI

I/O

H17

I/O

N20

GND

U19

I/O

GND

I/O

H18

I/O

U20

I/O

H19

I/O

VCC

I/O

H20

I/O

VCC

I/O

D10

I/O

VCCIO

D11

I/O

P17

GND

I/O

D12

I/O

GND

P18

I/O

B10

VCC

D13

I/O

P19

I/O

B11

I/O

D14

I/O

J17

I/O

P20

I/O

Y10

I/O

B12

GND

D15

I/O

J18

VCC

I/O

Y11

I/O

B13

I/O

D16

I/O

J19

GND

I/O

VCC

Y12

I/O

B14

I/O

D17

STM

J20

VCC

GND

V10

GND

Y13

I/O

B15

I/O

D18

I/O

ACLK / I

I/O

V11

I/O

Y14

I/O

B16

VCC

D19

I/O

VCC

R17

I/O

V12

I/O

Y15

I/O

B17

I/O

D20

I/O

GND

R18

VCC

V13

I/O

Y16

I/O

B18

GND

I/O

GCLK / I

R19

I/O

V14

I/O

Y17

VCC

B19

I/O

K17

I/O

R20

I/O

V15

GND

Y18

I/O

B20

I/O

K18

I/O

V16

I/O

Y19

I/O

K19

GCLK / I

I/O

V17

GND

Y20

I/O

E17

I/O

K20

GCLK / I

I/O

V18

TMS

TDO

E18

I/O

GCLK / I

VCC

V19

I/O

INOUT

ABLE

256-P

CPGA

8-47

Military QuickRAM

Rev A

Pinout Table 456-Pin PBGA

(Cont'd on next page)

INOUT

ABLE

456-P

PBGA

456

Function

456

Function

456

Function

456

Function

456

Function

I/O

B26

STM

D25

I/O

M14

GND/THERM

I/O

D26

I/O

M15

GND/THERM

I/O

H22

M16

GND/THERM

I/O

H23

I/O

M22

I/O

TDO

I/O

H24

I/O

M23

I/O

H25

I/O

M24

I/O

GND

H26

I/O

M25

I/O

VCC

I/O

M26

I/O

GND

I/O

GCLK/I

A10

I/O

A11

I/O

C10

I/O

GND

I/O

A12

VCCIO

C11

I/O

E10

I/O

GND

GCLK/I

A13

I/O

C12

I/O

E11

GND

J22

VCC

A14

I/O

C13

I/O

E12

GND

J23

N11

GND/THERM

A15

I/O

C14

I/O

E13

VCC

J24

I/O

N12

GND/THERM

A16

I/O

C15

I/O

E14

GND

J25

I/O

N13

GND/THERM

A17

I/O

C16

I/O

E15

GND

J26

I/O

N14

GND/THERM

A18

I/O

C17

I/O

E16

GND

I/O

N15

GND/THERM

A19

I/O

C18

I/O

E17

I/O

N16

GND/THERM

A20

I/O

C19

I/O

E18

GND

I/O

N22

GND

A21

I/O

C20

I/O

E19

I/O

N23

I/O

A22

I/O

C21

I/O

E20

GND

VCC

N24

I/O

A23

I/O

C22

I/O

E21

VCC

K22

GND

N25

I/O

A24

I/O

C23

I/O

E22

GND

K23

I/O

N26

I/O

A25

I/O

C24

I/O

E23

I/O

K24

I/O

A26

I/O

C25

TCK

E24

I/O

K25

I/O

C26

I/O

E25

I/O

K26

I/O

E26

I/O

P11

GND/THERM

I/O

GND

I/O

P12

GND/THERM

I/O

P13

GND/THERM

I/O

VCC

L11

GND/THERM

P14

GND/THERM

I/O

F22

VCC

L12

GND/THERM

P15

GND/THERM

I/O

F23

L13

GND/THERM

P16

GND/THERM

B10

I/O

GND

F24

I/O

L14

GND/THERM

P22

B11

I/O

D10

I/O

F25

I/O

L15

GND/THERM

P23

GCLK / I

B12

I/O

D11

I/O

F26

I/O

L16

GND/THERM

P24

GCLK / I

B13

I/O

D12

GND

I/O

L22

P25

I/O

B14

I/O

D13

I/O

L23

I/O

P26

ACLK / I

B15

I/O

D14

I/O

L24

I/O

B16

I/O

D15

GND

I/O

L25

I/O

B17

I/O

D16

I/O

L26

I/O

B18

I/O

D17

I/O

G22

GND

ACLK / I

B19

I/O

D18

GND

G23

I/O

GCLK/I

B20

I/O

D19

I/O

G24

I/O

R11

GND/THERM

B21

I/O

D20

I/O

G25

I/O

R12

GND/THERM

B22

I/O

D21

G26

I/O

GND

R13

GND/THERM

B23

I/O

D22

I/O

M11

GND/THERM

R14

GND/THERM

B24

I/O

D23

GND

I/O

M12

GND/THERM

R15

GND/THERM

B25

I/O

D24

I/O

M13

GND/THERM

R16

GND/THERM

Preliminary

8-48

Military QuickRAM

Rev A

PBGA 456 Pinout Table

(continued from previous page)

456

Function

456

Function

456

Function

456

Function

R22

VCC

I/O

AC6

AE5

I/O

R23

I/O

AC7

I/O

AE6

I/O

R24

I/O

AC8

I/O

AE7

I/O

R25

I/O

AC9

AE8

I/O

R26

GCLK / I

I/O

AC10

I/O

AE9

I/O

Y22

GND

AC11

I/O

AE10

I/O

Y23

I/O

AC12

AE11

I/O

Y24

I/O

AC13

I/O

AE12

I/O

Y25

I/O

AC14

VCCIO

AE13

I/O

VCC

Y26

I/O

AC15

AE14

I/O

T11

GND/THERMAL

AA1

I/O

AC16

I/O

AE15

I/O

T12

GND/THERMAL

AA2

I/O

AC17

I/O

AE16

I/O

T13

GND/THERMAL

AA3

AC18

AE17

I/O

T14

GND/THERMAL

AA4

AC19

I/O

AE18

I/O

T15

GND/THERMAL

AA5

VCC

AC20

I/O

AE19

I/O

T16

GND/THERMAL

AA22

VCC

AC21

I/O

AE20

I/O

T22

GND

AA23

AC22

AE21

I/O

T23

I/O

AA24

I/O

AC23

GND

AE22

I/O

T24

I/O

AA25

I/O

AC24

I/O

AE23

T25

I/O

AA26

I/O

AC25

I/O

AE24

TMS

T26

I/O

AB1

I/O

AC26

I/O

AE25

I/O

AB2

I/O

AD1

I/O

AE26

I/O

AB3

I/O

AD2

AF1

I/O

AB4

I/O

AD3

I/O

AF2

I/O

AB5

GND

AD4

I/O

AF3

I/O

GND

AB6

VCC

AD5

I/O

AF4

I/O

U22

AB7

AD6

I/O

AF5

I/O

U23

I/O

AB8

AD7

I/O

AF6

I/O

U24

I/O

AB9

AD8

I/O

AF7

I/O

U25

I/O

AB10

VCC

AD9

I/O

AF8

I/O

U26

I/O

AB11

GND

AD10

I/O

AF9

I/O

AB12

AD11

I/O

AF10

I/O

AB13

I/O

AD12

I/O

AF11

I/O

AB14

GND

AD13

I/O

AF12

I/O

AB15

VCC

AD14

I/O

AF13

I/O

AB16

I/O

AD15

I/O

AF14

I/O

V22

GND

AB17

AD16

I/O

AF15

I/O

V23

AB18

VCC

AD17

I/O

AF16

I/O

V24

I/O

AB19

GND

AD18

I/O

AF17

I/O

V25

I/O

AB20

AD19

I/O

AF18

I/O

V26

I/O

AB21

VCC

AD20

I/O

AF19

I/O

AB22

GND

AD21

I/O

AF20

I/O

AB23

I/O

AD22

I/O

AF21

I/O

AB24

I/O

AD23

TRSTB

AF22

I/O

AB25

I/O

AD24

I/O

AF23

I/O

AB26

I/O

AD25

I/O

AF24

I/O

W22

AC1

I/O

AD26

I/O

AF25

I/O

W23

I/O

AC2

I/O

AE1

TDI

AF26

I/O

W24

I/O

AC3

AE2

I/O

W25

I/O

AC4

GND

AE3

I/O

W26

I/O

AC5

I/O

AE4

I/O

8-49

Military QuickRAM

Rev A

Pin Descriptions

Ordering Information

ESCRIPTIONS

Pin

Function

Description

TDI/RSI

Test Data In for JTAG /
RAM init. Serial Data In

Hold HIGH during normal operation. Connects to serial
PROM data in for RAM initialization. Connect to VCC if
unused.

TRSTB/RRO

Active low Reset for JTAG /
RAM init. reset out

Hold LOW during normal operation. Connects to serial
PROM reset for RAM initialization. Connect to GND if
unused.

TMS

Test Mode Select for JTAG

Hold HIGH during normal operation. Connect to VCC if
not used for JTAG.

TCK

Test Clock for JTAG

Hold HIGH or LOW during normal operation. Connect to
VCC or ground if not used for JTAG.

TDO/RCO

Test data out for JTAG /
RAM init. clock out

Connect to serial PROM clock for RAM initialization. Must
be left unconnected if not used for JTAG or RAM
initialization.

STM

Special Test Mode

Must be grounded during normal operation.

I/ACLK

High-drive input and/or
array network driver

Can be configured as either or both.

I/GCLK

High-drive input and/or
global network driver

Can be configured as either or both.

High-drive input

Use for input signals with high fanout.

I/O

Input/Output pin

Can be configured as an input and/or output.

VCC

Power supply pin

Connect to 3.3V supply.

VCCIO

Input voltage tolerance pin

Connect to 5.0 volt supply if 5 volt input tolerance is
required, otherwise connect to 3.3V supply.

GND

Ground pin

Connect to ground.

GND/THERM

Ground/Thermal pin

Available on 456-PBGA only. Connect to ground plane on
PCB if heat sinking desired. Otherwise may be left
unconnected.

QL 4090 - 1 PQ208 M

Operating Range

M = Military
M/883 = MIL STD 883

Package Code
PL84 = 84-pin PLCC

CG84=84-pin CPGA

CF100 = 100-pin CQFP
CG144=144-pin CPGA

PQ208 = 208-pin PQFP
CF208 = 208-pin CQFP
PQ240 = 240-pin PQFP
CG256=256-pin CPGA
CG456=456-pin PBGA

QuickLogic

device

QuickRAM device

part number

4016
4036
4090

Speed Grade
0 = quick
1 = fast
2 = faster

Preliminary

8-50

Military QuickRAM

Rev A

ABSOLUTE MAXIMUM RATINGS

VCC Voltage ...........................-0.5 to 4.6V
VCCIO Voltage .......................-0.5 to 7.0V
Input Voltage.............. -0.5 to VCCIO+0.5V

Latch-up Immunity

...................±200 mA

DC Input Current

...................... ±20 mA

ESD Pad Protection

.................... ±

2000V

Storage Temperature .......-65

C to +150

Lead Temperature ...........................300

OPERATING RANGE

DC CHARACTERISTICS

Notes:

[1] Military devices have 8 mA IOL specifications.

[2] Capacitance is sample tested only. Clock pins are 12 pF maximum.

[3] Only one output at a time. Duration should not exceed 30 seconds.

[4] Maximum ICC is 5 mA for all military grade devices. For AC conditions, contact QuickLogic

customer engineering.

Symbol

Parameter

Military

Unit

Min

Max

VCC

Supply Voltage

3.0

3.6

VCCIO

I/O Input Tolerance Voltage

3.0

5.5

Ambient Temperature

-55

Case Temperature

125

-0 Speed Grade

0.42

2.03

Delay Factor

-1 Speed Grade

0.42

1.64

-2 Speed Grade

0.42

1.37

Symbol

Parameter

Conditions

Min

Max

Unit

VIH

Input HIGH Voltage

0.5VCC VCCIO+0.5 V

VIL

Input LOW Voltage

-0.5

0.3VCC

VOH

Output HIGH Voltage

IOH = -12 mA

2.4

IOH = -500

0.9VCC

VOL

Output LOW Voltage

IOL = 8 mA [1]

0.45

IOL = 1.5 mA

0.1VCC

I or I/O Input Leakage Current

VI = VCCIO or GND

-10

IOZ

3-State Output Leakage Current

VI = VCCIO or GND

-10

Input Capacitance [2]

IOS

Output Short Circuit Current [3]

VO = GND

-15

-180

VO = VCC

210

ICC

D.C. Supply Current [4]

VI, VIO = VCCIO or GND 0.50 (typ)

ICCIO

D.C. Supply Current on VCCIO

100

8-51

Military QuickRAM

Rev A

QL4016

AC CHARACTERISTICS at VCC = 3.3V, TA = 25

C (K = 1.00)

(To calculate delays, multiply the appropriate K factor in the "Operating Range" section by the following numbers.)

Logic Cells

Input-Only/Clock Cells

Notes:

[6] Stated timing for worst case Propagation Delay over process variation at VCC=3.3V and TA=25

°C.

Multiply by the appropriate Delay Factor, K, for speed grade, voltage and temperature settings as speci-
fied in the Operating Range.

[7] These limits are derived from a representative selection of the slowest paths through the QuickRAM

logic cell including typical net delays. Worst case delay values for specific paths should be determined
from timing analysis of your particular design.

QL4016

Symbol

Parameter

Propagation Delays (ns)

Fanout [6]

tPD

Combinatorial Delay [7]

1.4

1.7

1.9

2.2

3.2

tSU

Setup Time [7]

1.7

Hold Time

0.0

tCLK

Clock to Q Delay

0.7

1.0

1.2

1.5

2.5

tCWHI

Clock High Time

1.2

tCWLO

Clock Low Time

1.2

tSET

Set Delay

1.0

1.3

1.5

1.8

2.8

tRESET

Reset Delay

0.8

1.1

1.3

1.6

2.6

tSW

Set Width

1.9

tRW

Reset Width

1.8

Symbol

Parameter

Propagation Delays (ns)

Fanout [6]

TIN

High Drive Input Delay

1.5

1.6

1.8

1.9

2.4

2.9

4.4

TINI

High Drive Input, Inverting Delay

1.6

1.7

1.9

2.0

2.5

3.0

4.5

TISU

Input Register Set-Up Time

3.1

TIH

Input Register Hold Time

0.0

TlCLK

Input Register Clock To Q

0.7

0.8

1.0

1.1

1.6

2.1

3.6

TlRST

Input Register Reset Delay

0.6

0.7

0.9

1.0

1.5

2.0

3.5

TlESU

Input Register Clock Enable Setup Time

2.3

TlEH

Input Register Clock Enable Hold Time

0.0

Preliminary

8-52

Military QuickRAM

Rev A

QL4016 Clock Cells

I/O Cell Input Delays

I/O Cell Output Delays

Notes:

[6] Stated timing for worst case Propagation Delay over process variation at VCC=3.3V and TA=25

°C.

Multiply by the appropriate Delay Factor, K, for speed grade, voltage and temperature settings as
specified in the Operating Range.

[8] The array distributed networks consist of 40 half columns and the global distributed networks consist of

44 half columns, each driven by an independent buffer. The number of half columns used does not
affect clock buffer delay. The array clock has up to 8 loads per half column. The global clock has up to
11 loads per half column.

[9] The following loads are used for tPXZ:

Symbol

Parameter

Propagation Delays (ns)

Loads per Half Column [8]

tACK

Array Clock Delay

1.2

1.3

1.5

1.6

1.7

tGCKP

Global Clock Pin Delay

0.7

tGCKB

Global Clock Buffer Delay

0.8

0.9

1.1

1.2

1.3

Symbol

Parameter

Propagation Delays (ns)

Fanout [6]

tI/O

Input Delay (bidirectional pad)

1.3

1.6

1.8

2.1

3.1

3.6

TISU

Input Register Set-Up Time

3.1

TIH

Input Register Hold Time

0.0

TlOCLK

Input Register Clock To Q

0.7

1.0

1.2

1.5

2.5

3.0

TlORST

Input Register Reset Delay

0.6

0.9

1.1

1.4

2.4

2.9

TlESU

Input Register clock Enable Set-Up Time

2.3

TlEH

Input Register Clock Enable Hold Time

0.0

Symbol

Parameter

Propagation Delays (ns)

Output Load Capacitance (pF)

100

150

TOUTLH

Output Delay Low to High

2.1

2.5

3.1

3.6

4.7

TOUTHL

Output Delay High to Low

2.2

2.6

3.2

3.7

4.8

TPZH

Output Delay Tri-state to High

1.2

1.7

2.2

2.8

3.9

TPZL

Output Delay Tri-state to Low

1.6

2.0

2.6

3.1

4.2

TPHZ

Output Delay High to Tri-State [9]

2.0

TPLZ

Output Delay Low to Tri-State [9]

1.2

5 pF

tPHZ

tPLZ

8-53

Military QuickRAM

Rev A

QL4036

AC CHARACTERISTICS at VCC = 3.3V, TA = 25

C (K = 1.00)

(To calculate delays, multiply the appropriate K factor in the "Operating Range" section by the following numbers.)

Logic Cells

Input-Only/Clock Cells

Notes:

[5] Stated timing for worst case Propagation Delay over process variation at VCC=3.3V and TA=25

°C. Multi-

ply by the appropriate Delay Factor, K, for speed grade, voltage and temperature settings as specified in the
Operating Range.

[6] These limits are derived from a representative selection of the slowest paths through the pASIC 3 logic cell

including typical net delays. Worst case delay values for specific paths should be determined fromtiming
analysis of your particular design.

QL4036

Symbol

Parameter

Propagation Delays (ns)

Fanout [5]

tPD

Combinatorial Delay [6]

1.4

1.7

1.9

2.2

3.2

tSU

Setup Time [6]

1.7

Hold Time

0.0

tCLK

Clock to Q Delay

0.7

1.0

1.2

1.5

2.5

tCWHI

Clock High Time

1.2

tCWLO

Clock Low Time

1.2

tSET

Set Delay

1.0

1.3

1.5

1.8

2.8

tRESET

Reset Delay

0.8

1.1

1.3

1.6

2.6

tSW

Set Width

1.9

tRW

Reset Width

1.8

Symbol

Parameter

Propagation Delays (ns)

Fanout [5]

TIN

High Drive Input Delay

1.5

1.6

1.8

1.9

2.4

2.9

4.4

TINI

High Drive Input, Inverting Delay

1.6

1.7

1.9

2.0

2.5

3.0

4.5

TISU

Input Register Set-Up Time

3.1

TIH

Input Register Hold Time

0.0

TlCLK

Input Register Clock To Q

0.7

0.8

1.0

1.1

1.6

2.1

3.6

TlRST

Input Register Reset Delay

0.6

0.7

0.9

1.0

1.5

2.0

3.5

TlESU

Input Register Clock Enable Setup Time

2.3

TlEH

Input Register Clock Enable Hold Time

0.0

Preliminary

8-54

Military QuickRAM

Rev A

QL4036 Clock Cells

I/O Cell Input Delays

I/O Cell Output Delays

Notes:

[5] Stated timing for worst case Propagation Delay over process variation at VCC=3.3V and TA=25

°C.

Multiply by the appropriate Delay Factor, K, for speed grade, voltage and temperature settings as
specified in the Operating Range.

[7] The array distributed networks consist of 56 half columns and the global distributed networks consist of

60 half columns, each driven by an independent buffer. The number of half columns used does not
affect clock buffer delay. The array clock has up to 12 loads per half column. The global clock has up
to 15 loads per half column.

[8] The following loads are used for tPXZ:

Symbol

Parameter

Propagation Delays (ns)

Loads per Half Column [7]

tACK

Array Clock Delay

1.2

1.3

1.5

1.6

1.7

1.8

tGCKP

Global Clock Pin Delay

0.7

tGCKB

Global Clock Buffer Delay

0.8

0.9

1.1

1.2

1.3

1.4

Symbol

Parameter

Propagation Delays (ns)

Fanout [5]

tI/O

Input Delay (bidirectional pad)

1.3

1.6

1.8

2.1

3.1

3.6

TISU

Input Register Set-Up Time

3.1

TIH

Input Register Hold Time

0.0

TlOCLK

Input Register Clock To Q

0.7

1.0

1.2

1.5

2.5

3.0

TlORST

Input Register Reset Delay

0.6

0.9

1.1

1.4

2.4

2.9

TlESU

Input Register clock Enable Set-Up Time

2.3

TlEH

Input Register Clock Enable Hold Time

0.0

Symbol

Parameter

Propagation Delays (ns)

Output Load Capacitance (pF)

100

150

TOUTLH

Output Delay Low to High

2.1

2.5

3.1

3.6

4.7

TOUTHL

Output Delay High to Low

2.2

2.6

3.2

3.7

4.8

TPZH

Output Delay Tri-state to High

1.2

1.7

2.2

2.8

3.9

TPZL

Output Delay Tri-state to Low

1.6

2.0

2.6

3.1

4.2

TPHZ

Output Delay High to Tri-State [8]

2.0

TPLZ

Output Delay Low to Tri-State [8]

1.2

5 pF

tPHZ

tPLZ

8-55

Military QuickRAM

Rev A

QL4090

AC CHARACTERISTICS at VCC = 3.3V, TA = 25

C (K = 1.00)

(To calculate delays, multiply the appropriate K factor in the "Operating Range" section by the following numbers.)

Logic Cells

Input-Only/Clock Cells

Notes:

[5] Stated timing for worst case Propagation Delay over process variation at VCC=3.3V and TA=25

°C.

Multiply by the appropriate Delay Factor, K, for speed grade, voltage and temperature settings as
specified in the Operating Range.

[6] These limits are derived from a representative selection of the slowest paths through the pASIC 3 logic

cell including typical net delays. Worst case delay values for specific paths should be determined from
timing analysis of your particular design.

QL4090

Symbol

Parameter

Propagation Delays (ns)

Fanout [5]

tPD

Combinatorial Delay [6]

1.4

1.7

1.9

2.2

3.2

tSU

Setup Time [6]

1.7

Hold Time

0.0

tCLK

Clock to Q Delay

0.7

1.0

1.2

1.5

2.5

tCWHI

Clock High Time

1.2

tCWLO

Clock Low Time

1.2

tSET

Set Delay

1.0

1.3

1.5

1.8

2.8

tRESET

Reset Delay

0.8

1.1

1.3

1.6

2.6

tSW

Set Width

1.9

tRW

Reset Width

1.8

Symbol

Parameter

Propagation Delays (ns)

Fanout [5]

TIN

High Drive Input Delay

1.5

1.6

1.8

1.9

2.4

2.9

4.4

TINI

High Drive Input, Inverting Delay

1.6

1.7

1.9

2.0

2.5

3.0

4.5

TISU

Input Register Set-Up Time

3.1

TIH

Input Register Hold Time

0.0

TlCLK

Input Register Clock To Q

0.7

0.8

1.0

1.1

1.6

2.1

3.6

TlRST

Input Register Reset Delay

0.6

0.7

0.9

1.0

1.5

2.0

3.5

TlESU

Input Register Clock Enable Setup Time

2.3

TlEH

Input Register Clock Enable Hold Time

0.0

Preliminary

8-56

Military QuickRAM

Rev A

QL4090 Clock Cells

I/O Cell Input Delays

I/O Cell Output Delays

Notes:

[5] Stated timing for worst case Propagation Delay over process variation at VCC=3.3V and TA=25

°C.

Multiply by the appropriate Delay Factor, K, for speed grade, voltage and temperature settings as spec-
ified in the Operating Range.

[7] The array distributed networks consist of 88 half columns and the global distributed networks consist of

92 half columns, each driven by an independent buffer. The number of half columns used does not
affect clock buffer delay. The array clock has up to 18 loads per half column. The global clock has up
to 20 loads per half column.

[8] The following loads are used for tPXZ:

Symbol

Parameter

Propagation Delays (ns)

Loads per Half Column [7]

TACK

Array Clock Delay

1.2

1.3

1.5

1.6

1.7

1.8

1.9

2.1

TGCKP

Global Clock Pin Delay

0.7

TGCKB

Global Clock Buffer Delay

0.8

0.9

1.1

1.2

1.3

1.4

1.5

1.6

1.7

Symbol

Parameter

Propagation Delays (ns)

Fanout [5]

tI/O

Input Delay (bidirectional pad)

1.3

1.6

1.8

2.1

3.1

3.6

TISU

Input Register Set-Up Time

3.1

TIH

Input Register Hold Time

0.0

TlOCLK

Input Register Clock To Q

0.7

1.0

1.2

1.5

2.5

3.0

TlORST

Input Register Reset Delay

0.6

0.9

1.1

1.4

2.4

2.9

TlESU

Input Register clock Enable Set-Up Time

2.3

TlEH

Input Register Clock Enable Hold Time

0.0

Symbol

Parameter

Propagation Delays (ns)

Output Load Capacitance (pF)

100

150

TOUTLH

Output Delay Low to High

2.1

2.5

3.1

3.6

4.7

TOUTHL

Output Delay High to Low

2.2

2.6

3.2

3.7

4.8

TPZH

Output Delay Tri-state to High

1.2

1.7

2.2

2.8

3.9

TPZL

Output Delay Tri-state to Low

1.6

2.0

2.6

3.1

4.2

TPHZ

Output Delay High to Tri-State [8]

2.0

TPLZ

Output Delay Low to Tri-State [8]

1.2

5 pF

tPHZ

tPLZ

8-57

Military QuickRAM

Rev A

RAM Cell Synchronous Write Timing

RAM Cell Synchronous Read Timing

RAM Cell Asynchronous Read Timing

Notes:

[5] Stated timing for worst case Propagation Delay over process variation at VCC=3.3V and TA=25

°C.

Multiply by the appropriate Delay Factor, K, for speed grade, voltage and temperature settings as
specified in the Operating Range.

Symbol

Parameter

Propagation Delays (ns)

Fanout

TSWA

WA Setup Time to WCLK

1.0

THWA

WA Hold Time to WCLK

0.0

TSWD

WD Setup Time to WCLK

1.0

THWD

WD Hold Time to WCLK

0.0

TSWE

WE Setup Time to WCLK

1.0

THWE

WE Hold Time to WCLK

0.0

TWCRD

WCLK to RD (WA=RA) [5]

5.0

5.3

5.6

5.9

7.1

Symbol

Parameter

Propagation Delays (ns)

Fanout

TSRA

RA Setup Time to RCLK

1.0

THRA

RA Hold Time to RCLK

0.0

TSRE

RE Setup Time to RCLK

1.0

THRE

RE Hold Time to RCLK

0.0

TRCRD

RCLK to RD [5]

4.0

4.3

4.6

4.9

6.1

Symbol

Parameter

Propagation Delays (ns)

Fanout

RPDRD

RA to RD [5]

3.0

3.3

3.6

3.9

5.1

Document Outline

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: QL4036-0PL84M

Document Outline

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: QL4036-0PL84M