SINGLE-CHIP 9-PORT 10/100MBPS SWITCH CONTROLLER
DATASHEET
Rev. 1.4
09 July 2004
Track ID: JATR-1076-21
RTL8309SB
RTL8309SB
Datasheet
Single-Chip 9-Port 10/100Mbps Switch Controller ii Track ID: JATR-1076-21 Rev. 1.4
COPYRIGHT
2004 Realtek Semiconductor Corp. All rights reserved. No part of this document may be reproduced, transmitted,
transcribed, stored in a retrieval system, or translated into any language in any form or by any means without the written
permission of Realtek Semiconductor Corp.
DISCLAIMER
Realtek provides this document "as is", without warranty of any kind, neither expressed nor implied, including, but not limited
to, the particular purpose. Realtek may make improvements and/or changes in this document or in the product described in this
document at any time. This document could include technical inaccuracies or typographical errors.
TRADEMARKS
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trademarks/registered trademarks of their respective owners.
USING THIS DOCUMENT
This document provides detailed user guidelines to achieve the best performance when implementing a 2-layer board PC
design with the RTL8309SB Single-Chip 9-port 10/100Mbps Switch Controller.
Though every effort has been made to assure that this document is current and accurate, more information may have become
available subsequent to the production of this guide. In that event, please contact your Realtek representative for additional
information that may help in the development process.
RTL8309SB
Datasheet
Single-Chip 9-Port 10/100Mbps Switch Controller iii Track ID: JATR-1076-21 Rev. 1.4
REVISION HISTORY
Revision
Release Date
Summary
1.0 2003/04/12
First
release.
1.1 2003/05/15
Revised
pin
descriptions.
Revised description for Bi-color LED.
New Bi-color LED Reference Schematic figure.
Add 3.3V items to electrical characteristics.
Add thermal operating range temperatures.
1.2
2003/12/01
Revised pin description of Dis_VLAN.
Revised pin description of Max_Pause_Count.
Revised default VLAN membership configuration for Disable VLAN
function in PHY register 16.11.
Update default value of Differential Service Code Point [B] in EEPROM
and PHY registers.
Update default value of VLAN ID [A] membership in EERPOM.
Update default value of ISP MAC Address in EEPROM.
Update default value of Port 8 VLAN Index in EEPROM.
Revised the definition for WAN port specification in EEPROM and PHY
registers.
Revised the definition for CPU port specification in EEPROM and PHY
registers.
Removed the Bypass CRC function in EEPROM.
Removed the Good Link Quality Threshold function in EEPROM and
PHY registers.
Add explanation of Indirect Access Data in PHY 7 Register 17~20.
1.3
2004/06/10
Removed PHY0~PHY7 REG2 and REG3 info.
Update pin number ordering on Pin Description Table.
Change the term "Auto MDIX" to "Crossover Detection and auto
correction".
1.4
2004/07/09
Removed QoS feature for IPv6.
RTL8309SB
Datasheet
Single-Chip 9-Port 10/100Mbps Switch Controller iv Track ID: JATR-1076-21 Rev. 1.4
Table of Contents
1.
GENERAL DESCRIPTION................................................................................................................................................1
2.
FEATURES...........................................................................................................................................................................3
3.
BLOCK DIAGRAM.............................................................................................................................................................4
4.
PIN ASSIGNMENTS ...........................................................................................................................................................5
5.
PIN DESCRIPTIONS ..........................................................................................................................................................7
5.1.
M
EDIA
C
ONNECTION
P
INS
..........................................................................................................................................7
5.2.
MII P
ORT
MAC I
NTERFACE
P
INS
...............................................................................................................................7
5.3.
M
ISCELLANEOUS
P
INS
................................................................................................................................................9
5.4.
P
ORT
LED P
INS
..........................................................................................................................................................9
5.5.
S
ERIAL
EEPROM
AND
SMI P
INS
.............................................................................................................................11
5.6.
S
TRAPPING
P
INS
........................................................................................................................................................12
5.7.
P
OWER
P
INS
..............................................................................................................................................................16
6.
EEPROM REGISTER DESCRIPTION ..........................................................................................................................17
6.1.
G
LOBAL
C
ONTROL
R
EGISTERS
..................................................................................................................................17
6.1.1.
Global Control Register0 ...................................................................................................................................17
6.1.2.
Global Control Register1 ...................................................................................................................................17
6.1.3.
Global Control Register2 ...................................................................................................................................18
6.1.4.
Global Control Register3 ...................................................................................................................................18
6.1.5.
Global Control Register4 ...................................................................................................................................19
6.1.6.
Global Control Register5 ...................................................................................................................................19
6.1.7.
Global Control Register6 ...................................................................................................................................19
6.1.8.
Global Control Register7 ...................................................................................................................................19
6.2.
P
ORT
0~7 C
ONTROL
P
INS
..........................................................................................................................................20
6.2.1.
Port 0 Control 0..................................................................................................................................................20
6.2.2.
Port 0 Control 1..................................................................................................................................................20
6.2.3.
Port 0 Control 2..................................................................................................................................................21
6.2.4.
Port 0 Control 3..................................................................................................................................................21
6.2.5.
Port 0 Control 4..................................................................................................................................................21
6.2.6.
IP Address...........................................................................................................................................................22
6.2.7.
Port 1 Control 0..................................................................................................................................................23
6.2.8.
Port 1 Control 1..................................................................................................................................................23
RTL8309SB
Datasheet
Single-Chip 9-Port 10/100Mbps Switch Controller v Track ID: JATR-1076-21 Rev. 1.4
6.2.9.
Port 1 Control 2..................................................................................................................................................24
6.2.10.
Port 1 Control 3..................................................................................................................................................24
6.2.11.
Port 1 Control 4..................................................................................................................................................24
6.2.12.
IP Mask ..............................................................................................................................................................25
6.2.13.
Port 2 Control 0..................................................................................................................................................25
6.2.14.
Port 2 Control 1..................................................................................................................................................26
6.2.15.
Port 2 Control 2..................................................................................................................................................26
6.2.16.
Port 2 Control 3..................................................................................................................................................26
6.2.17.
Port 2 Control 4..................................................................................................................................................27
6.2.18.
Switch MAC Address ..........................................................................................................................................27
6.2.19.
Port 3 Control 0..................................................................................................................................................28
6.2.20.
Port 3 Control 1..................................................................................................................................................28
6.2.21.
Port 3 Control 2..................................................................................................................................................29
6.2.22.
Port 3 Control 3..................................................................................................................................................29
6.2.23.
Port 3 Control 4..................................................................................................................................................29
6.2.24.
ISP MAC Address ...............................................................................................................................................30
6.2.25.
Port 4 Control 0..................................................................................................................................................30
6.2.26.
Port 4 Control 1..................................................................................................................................................30
6.2.27.
Port 4 Control 2..................................................................................................................................................31
6.2.28.
Port 4 Control 3..................................................................................................................................................31
6.2.29.
Port 4 Control 4..................................................................................................................................................31
6.3.
MII P
ORT
C
ONTROL
P
INS
..........................................................................................................................................32
6.3.1.
MII Port Control 0..............................................................................................................................................32
6.3.2.
MII Port Control 1..............................................................................................................................................32
6.3.3.
MII Port Control 2..............................................................................................................................................33
6.3.4.
CPU Port and WAN Port....................................................................................................................................33
6.4.
P
ORT
5~7 C
ONTROL
P
INS
..........................................................................................................................................34
6.4.1.
Port 5 Control 0..................................................................................................................................................34
6.4.2.
Port 5 Control 1..................................................................................................................................................34
6.4.3.
Port 5 Control 2..................................................................................................................................................35
6.4.4.
Port 5 Control 3..................................................................................................................................................35
6.4.5.
Port 5 Control 4..................................................................................................................................................35
6.4.6.
Port 6 Control 0..................................................................................................................................................36
6.4.7.
Port 6 Control 1..................................................................................................................................................36
6.4.8.
Port 6 Control 2..................................................................................................................................................36
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