S29C51001T/S29C51001B V1.0 February 2003

Features

128Kx8-bit Organization

Address Access Time:

70, 90, 120 ns

Single 5V

10% Power Supply

Sector Erase Mode Operation

8KB Boot Block (lockable)

512 bytes per Sector, 256 Sectors
Sector-Erase Cycle Time: 10ms (Max)
Byte-Program Cycle Time: 20

s (Max)

Minimum 10,000 Erase-Program Cycles

Low power dissipation
Active Read Current: 20mA (Typ)
Active Program Current: 30mA (Typ)
Standby Current: 100

A (Max)

Hardware Data Protection

Low V

Program Inhibit Below 3.2V

Self-timed program/erase operations with end-
of-cycle detection
DATA Polling
Toggle Bit

CMOS and TTL Interface

Available in two versions

S29C51001T (Top Boot Block)

S29C51001B (Bottom Boot Block)

Packages:
32-pin Plastic DIP
32-pin TSOP-I
32-pin PLCC

Description

The

S29C51001T/S29C51001B is a high speed

131,072 x 8 bit CMOS flash memory. Programming
or erasing the device is done with a single 5 Volt
power supply. The device has separate chip enable
CE, program enable WE, and output enable OE
controls to eliminate bus contention.

The

S29C51001T/S29C51001B offers a combi-

nation of features: Boot Block with Sector Erase
Mode. The end of program/erase cycle is detected
by DATA Polling of I/O

or by the Toggle Bit I/O

The

S29C51001T/S29C51001B features a

sector erase operation which allows each sector to
be erased and reprogrammed without affecting
data stored in other sectors. The device also
supports full chip erase.

Boot block architecture enables the device to

boot from a protected sector loaded either at the
top (

S29C51001T) or the bottom (S29C51001B)

sector. All inputs and outputs are CMOS and TTL
compatible.

The

S29C51001T/S29C51001B is ideal for

applications that require updatable code and data
storage.

SyncMOS Technologies Inc.

S29C51001T/S29C51001B

1 MEGABIT (131,072 x 8 BIT)

5 VOLT CMOS FLASH MEMORY

Pin Configurations

N/C

A16

A15

A12

I/O0

I/O1
I/O2

GND

13
14

15
16

32-Pin PDIP

Top View

A14

A13

A11

A10

I/O3

I/O4

I/O5

I/O6

I/O7

51001-02

Pin Names

Address Inputs

I/O

Data Input/Output

Chip Enable

Output Enable

Program Enable

10% Power Supply

GND Ground

No Connect

A11

A9
A8

A13
A14

VCC

N/C

A16
A15
A12

A7
A6
A5
A4

1
2
3
4
5
6

8
9
10
11
12
13
14
15
16

29
28
27
26
25

24
23
22
21
20

32-Pin TSOP I

Standard Pinout

Top View

OE
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3
GND
I/O2
I/O1

I/O0

19
18
17

51001-04

I/O

51001-03

I/O

GND

I/O

32 Pin PLCC

Top View

15 16 17 18 19 20

3 2 1

32 31 30

SyncMOS Technologies Inc.

S29C51001T/S29C51001B

1 MEGABIT (131,072 x 8 BIT)

5 VOLT CMOS FLASH MEMORY

OPERATING VOLTAGE

51: 5V

DEVICE SPEED

S 29 C 00

BOOT BLOCK LOCATION

T: TOP

70: 70ns
90: 90ns

12: 120ns

P = PDIP

T = TSOP-I

J = PLCC

PKG.

S29C51001T/S29C51001B V1.0 February 2003

Functional Block Diagram

Capacitance

(1,2)

NOTE:
1. Capacitance is sampled and not 100% tested.
2. T

= 25

C, V

= 5V

10%, f = 1 MHz.

Latch Up Characteristics

(1)

NOTE:
1. Includes all pins except V

. Test conditions: V

= 5V, one pin at a time.

AC Test Load

Symbol Parameter Test mSetup Typ. Max. Units

Input Capacitance V

= 0 6 8 pF

OUT

Output Capacitance V

OUT

= 0 8 12 pF

IN2

Control Pin Capacitance V

= 0 8 10 pF

Parameter

Min. Max. Unit

Input Voltage with Respect to GND on A

, OE

-1 +13 V

Input Voltage with Respect to GND on I/O, address or control pins -1 V

+ 1 V

Current -100 +100 mA

Address buffer & latches

51001-05

I/O Buffer & Data Latches

I/O

Y-Decoder

1,048,576 Bit

Memory Cell Array

X-Decoder

Control Logic

51001-06

IN3064 or Equivalent

IN3064

or Equivalent

2.7 k

6.2 k

+5.0 V

IN3064 or Equivalent

= 100 pF

Device Under

Test

SyncMOS Technologies Inc.

S29C51001T/S29C51001B

1 MEGABIT (131,072 x 8 BIT)

5 VOLT CMOS FLASH MEMORY

S29C51001T/S29C51001B V1.0 February 2003

Absolute Maximum Ratings

(1)

NOTE:

1. Stress greater than those listed unders "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress

rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections
of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

2. No more than one output maybe shorted at a time and not exceeding one second long.

DC Electrical Characteristics

(over the commercial operating range)

Symbol Parameter Commercial Extended Unit

Input Voltage (input or I/O pins) -2 to +7 -2 to +7 V

Input Voltage (A

pin, OE) -2 to +13 -2 to +13 V

Power Supply Voltage -0.5 to +5.5 -0.5 to +5.5 V

STG

Storage Temerpature (Plastic) -65 to +125 -65 to +150

OPR

Operating Temperature 0 to +70 -40 to + 125

OUT

Short Circuit Current

(2)

200 (Max.) 200 (Max.) mA

Parameter
Name Parameter Test Conditions Min. Max. Unit

Input LOW Voltage V

= V

Min. -- 0.8 V

Input HIGH Voltage V

= V

Max. 2 -- V

Input Leakage Current V

= GND to V

, V

= V

Max. --

Output Leakage Current V

OUT

= GND to V

, V

= V

Max. --

Output LOW Voltage V

= V

Min., I

= 2.1mA -- 0.4 V

Output HIGH Voltage V

= V

Min, I

= -400

A 2.4 -- V

CC1

Read Current CE = OE = V

, WE = V

, all I/Os open,

Address input = V

, at f = 1/t

Min.,

= V

Max.

-- 40 mA

CC2

Program Current CE = WE = VIL, OE = V

, V

= V

Max. -- 50 mA

TTL Standby Current CE = OE = WE = V

, V

= V

Max. -- 2 mA

SB1

CMOS Standby Current CE = OE = WE = V

0.3V, V

= V

Max. -- 100

Device ID Voltage for A

CE = OE = V

, WE = V

11.5 12.5 V

Device ID Current for A

CE = OE = V

, WE = V

, A9 = V

Max. -- 50

SyncMOS Technologies Inc.

S29C51001T/S29C51001B

1 MEGABIT (131,072 x 8 BIT)

5 VOLT CMOS FLASH MEMORY

S29C51001T/S29C51001B V1.0 February 2003

AC Electrical Characteristics

(over all temperature ranges)

Read Cycle

Program (Erase/Program) Cycle

Parameter

Name Parameter

70 -90 -120

Unit

Min. Max. Min. Max. Min. Max.

Read Cycle Time

70 -- 90 -- -- ns

Address Access Time --

70 -- 90 -- ns

ACS

Chip Enable Access Time --

70 -- 90 -- ns

Output Enable Access Time --

35 -- 45 -- ns

CLZ

CE Low to Output Active 0 -- 0 --

-- ns

OLZ

OE Low to Output Active 0 -- 0 --

-- ns

Output Enable or Chip Disable to Output
in High Z

20 0 30 ns

Output Hold from Address Change 0 -- 0 --

-- ns

Parameter

Name Parameter

70 -90 -120

Unit

Min. Typ. Max. Min. Typ. Max. Min. Typ. Max.

Program Cycle Time

70 -- -- 90 -- -- -- -- ns

Address Setup Time 0 -- -- 0 -- -- -- -- ns

Address Hold Time

45 -- -- 45 -- -- -- -- ns

CE Setup Time 0 -- -- 0 -- -- -- -- ns

CE Hold Time 0 -- -- 0 -- -- -- -- ns

OES

OE Setup Time 0 -- -- 0 -- -- -- -- ns

OEH

OE High Hold Time 0 -- -- 0 -- -- -- -- ns

WE Pulse Width

35 -- -- 45 -- -- -- -- ns

WPH

WE Pulse Width High

35 -- -- 38 -- -- -- -- ns

Data Setup Time 2

5 -- -- 30 -- -- -- -- ns

Data Hold Time 0 -- -- 0 -- -- -- -- ns

WHWH1

Programming Cycle -- -- 20 -- -- 20 --

WHWH2

Sector Erase Cycle -- -- 10 -- -- 10 --

-- ms

WHWH3

Chip Erase Cycle --

3 -- -- 3 -- -- -- s

SyncMOS Technologies Inc.

S29C51001T/S29C51001B

1 MEGABIT (131,072 x 8 BIT)

5 VOLT CMOS FLASH MEMORY

S29C51001T/S29C51001B V1.0 February 2003

Waveforms of Read Cycle

Waveforms of WE Controlled-Program Cycle

NOTES:
1. I/O

: The output is the complement of the data written to the device.

2. PA: The address of the memory location to be programmed.
3. PD: The data at the byte address to be programmed.

CLZ

OLZ

ADDRESS

I/O VALID DATA OUT VALID DATA OUT

HIGH-Z

51001-07

HIGH-Z

5555H

WHWH1

WPH

OES

OUT

I/O

(1)

(3)

A0H

51001-08

ADDRESS

I/O

3rd bus cycle

(2)

SyncMOS Technologies Inc.

S29C51001T/S29C51001B

1 MEGABIT (131,072 x 8 BIT)

5 VOLT CMOS FLASH MEMORY

S29C51001T/S29C51001B V1.0 February 2003

Waveforms of CE Controlled-Program Cycle

Waveforms of Erase Cycle

(1)

NOTES:
1. PA: The address of the memory location to be programmed.
2. PD: The data at the byte address to be programmed.
3. SA: The sector address for Sector Erase. Address = don't care for Chip Erase.

WHWH1

WPH

OES

OUT

I/O7

(2)

A0H

51001-09

ADDRESS 5555H PA PA

(1)

I/O

WPH

ADDRESS

I/O

5555H 5555H 5555H

2AAAH 2AAAH SA

AAH 55H 80H AAH 55H 30H

10H for

Chip Erase

51001-10

SyncMOS Technologies Inc.

S29C51001T/S29C51001B

1 MEGABIT (131,072 x 8 BIT)

5 VOLT CMOS FLASH MEMORY

S29C51001T/S29C51001B V1.0 February 2003

Functional Description

The

S29C51001T/S29C51001B consists of 256

equally-sized sectors of 512 bytes each. The 8 KB
lockable Boot Block is intended for storage of the
system BIOS boot code. The boot code is the first
piece of code executed each time the system is
powered on or rebooted.

The

S29C51001 is available in two versions: the

S29C51001T with the Boot Block address starting
from 1E000H to 1FFFFH, and the

S29C51001B

with the Boot Block address starting from 00000H
to 1FFFFH.

Read Cycle

A read cycle is performed by holding both CE

and OE signals LOW. Data Out becomes valid only
when these conditions are met. During a read cycle
WE must be HIGH prior to CE and OE going LOW.
WE must remain HIGH during the read operation
for the read to complete (see Table 1).

Output Disable

Returning OE or CE HIGH, whichever occurs first

will terminate the read operation and place the l/O
pins in the HIGH-Z state.

Standby

The device will enter standby mode when the CE

signal is HIGH. The l/O pins are placed in the
HIGH-Z, independent of the OE signal.

Byte Program Cycle

The

S29C51001T/S29C51001B is programmed

on a byte-by-byte basis. The byte program
operation is initiated by using a specific four-bus-
cycle sequence: two unlock program cycles, a
program setup command and program data
program cycles (see Table 2).

During the byte program cycle, addresses are

latched on the falling edge of either CE or WE,
whichever is last. Data is latched on the rising edge
of CE or WE, whichever is first. The byte program
cycle can be CE controlled or WE controlled.

Sector Erase Cycle

The

S29C51001T/S29C51001B features a

sector erase operation which allows each sector to
be erased and reprogrammed without affecting
data stored in other sectors. Sector erase operation
is initiated by using a specific six-bus-cycle
sequence: Two unlock program cycles, a setup
command, two additional unlock program cycles,
and the sector erase command (see Table 2). A
sector must be first erased before it can be
reprogrammed. While in the internal erase mode,
the device ignores any program attempt into the
device. The internal erase completion can be
determined via DATA polling or toggle bit.

The

S29C51001T/S29C51001B is shipped with

pre-erased sectors (all bits = 1).

8KB Boot Block

512

8KB Boot Block

S29C51001T S29C51001B

1FFFFH

1E000H

00000H

01FFFH

51001-13

00000H

8KB Boot Block = 16 Sectors

Table 1. Operation Modes Decoding

Decoding Mode CE

I/O

Read V

READ

Byte Write V

Standby V

X X X X X HIGH-Z

Autoselect Device ID V

CODE

Autoselect Manufacture ID V

CODE

Enabling Boot Block Protection Lock V

X X V

SyncMOS Technologies Inc.

S29C51001T/S29C51001B

1 MEGABIT (131,072 x 8 BIT)

5 VOLT CMOS FLASH MEMORY

S29C51001T/S29C51001B V1.0 February 2003

NOTES:
1. X = Don't Care, V

= HIGH, V

= LOW. V

= 12.5V Max.

2. PD: The data at the byte address to be programmed.

Table 2. Command Codes

NOTES:
1. Top Boot Sector
2. Bottom Boot Sector
3. PA: The address of the memory location to be programmed.
4. PD: The data at the byte address to be programmed.

Disabling Boot Block Protection Lock V

X X V

Output Disable V

X X X HIGH-Z

Command
Sequence

First Bus
Program Cycle

Second Bus
Program Cycle

Third Bus
Program Cycle

Fourth Bus
Program Cycle

Fifth Bus
Program Cycle

Six Bus
Program Cycle

Address Data Address Data Address Data Address Data Address Data Address Data

Read XXXXH F0H

Read 5555H AAH 2AAAH 55H 5555H F0H RA RD

Autoselect 5555H AAH 2AAAH 55H 5555H 90H 00H 40H

01H 01H

(1)

A1H

(2)

Byte
Program

5555H AAH 2AAAH 55H 5555H A0H PA PD(4)

Chip Erase 5555H AAH 2AAAH 55H 5555H 80H 5555H AAH 2AAAH 55H 5555H 10H

Sector Erase

5555H AAH 2AAAH 55H 5555H 80H 5555H AAH 2AAAH 55H PA(3) 30H

Decoding Mode CE OE WE A

I/O

Chip Erase Cycle

The

S29C51001T/S29C51001B features a chip-

erase operation. The chip erase operation is
i n i t i a t e d b y u s i n g a s p e c i f i c s i x - b u s - c y c l e
sequence: two unlock program cycles, a setup
command, two additional unlock program cycles,
and the chip erase command (see Table 2).

T h e c h i p e r a s e o p e r a t i o n i s p e r f o r m e d

sequentially, one sector at a time. When the
automated on chip erase algorithm is requested
with the chip erase command sequence, the device
automatically programs and verifies the entire
memory array for an all zero pattern prior to erasure

The automatic erase begins on the rising edge of

the last WE or CE pulse in the command sequence
and terminates when the data on DQ7 is "1".

Program Cycle Status Detection

There are two methods for determining the state

o f t h e

S29C51001T/S29C51001B during a

program (erase/program) cycle: DATA Polling
(I/O

) and Toggle Bit (I/O

DATA Polling (I/O

)

The

S29C51001T/S29C51001B features DATA

polling to indicate the end of a program cycle.
When the device is in the program cycle, any
attempt to read the device will received the
complement of the loaded data on I/O

. Once the

program cycle is completed, I/O

will show true

data, and the device is then ready for the next
cycle.

Toggle Bit (I/O

)

The

S29C51001T/S29C51001B also features

another method for determining the end of a
program cycle. When the device is in the program
cycle, any attempt to read the device will result in
l/O

toggling between 1 and 0. Once the program is

completed, the toggling will stop. The device is then
ready for the next operation. Examining the toggle
bit may begin at any time during a program cycle.

SyncMOS Technologies Inc.

S29C51001T/S29C51001B

1 MEGABIT (131,072 x 8 BIT)

5 VOLT CMOS FLASH MEMORY

S29C51001T/S29C51001B V1.0 February 2003

Boot Block Protection

T h e

S29C51001T/S29C51001B features

hardware Boot Block Protection. The boot block
sector protection is enabled when high voltage
(12.5V) is applied to OE and A9 pins with CE pin
LOW and WE pin lOW. The sector protection is
desabled when high voltage is applied to OE, CE
and A9 pins with WE pin LOW. Other pins can be
HIGH or LOW. This is shown in table 1.

Autoselect

The

S29C51001T/S29C51001B features an

Autoselect mode to identify

the Boot Block

(protected/unprotected), the Device (Top/Bottom),
and the manufacturer ID.

To get to the Autoselect mode, a high voltage

) must be applied to the A

pin. Once the A

signal is returned to LOW or HIGH, the device will
return to the previous mode.

Boot Block Protection Status

In Autoselect mode, performing a read at

address 3CXX2H or address 0CXX2H will indicate
if the Top Boot Block sector or the Bottom Boot
Block sector is locked out. If the data is 01H, the
Top/Bottom Boot Block is protected. If the data is
00H, the Top/Bottom Boot Block is unprotected.
(see Table 3.)

Device ID

In Autoselect mode, performing a read at

address XXXXH will determine whether the device
is a Top Boot Block device or a Bottom Boot Block
device. If the data is 01H, the device is a Top Boot
Block. If the data is A1H, the device is a Bottom
Boot Block device (see Table 3).

In addition, the device ID can also be read via the

command register when the device is erased or
programmed in a system without applying high
voltage to the A

pin. When A

is HIGH, the device

ID is presented at the outputs.

Manufacturer ID

In Autoselect mode, performing a read at

address. XXXX0H will determine the manufacturer
ID. 40H is the manufacturer code for SyncMOS
Flash.

In addition the manufacturer ID can also be read

via the command register when the device is
erased or programmed in a system without
applying high voltage to the A

pin. when A

LOW, the manufacturer ID is presented at the
outputs.

Hardware Data Protection

Sense Protection: the program operation is

inhibited when VCC is less than 2.5V.

Noise Protection: a CE or WE pulse of less than

5ns will not initiate a program cycle.

Program Inhibit Protection: holding any one of

OE LOW, CE HIGH or WE HIGH inhibits a program
cycle.

Table 3. Autoselect Decoding

NOTE:
1. X = Don't Care, V

= HIGH, V

= LOW.

Decoding Mode Boot Block

Address

Data I/O

I/O

Boot Block Protection Top V

X V

01H: protected

Bottom V

X V

00H: unprotected

Device ID Top V

X X 01H

Bottom A1H

Manufacture ID V

X X 40H

SyncMOS Technologies Inc.

S29C51001T/S29C51001B

1 MEGABIT (131,072 x 8 BIT)

5 VOLT CMOS FLASH MEMORY

S29C51001T/S29C51001B V1.0 February 2003

Byte Program Algorithm

Chip/Sector Erase Algorithm

Write Program

Command Sequence

Add/Data

5555H/AAH

2AAAH/55H

5555H/A0H

Four Bus
Cycle
Sequence

PA/PD

DATA

Polling (I/O7)

or Toggle Bit (I/O6)

Programming

Completed

Verify Byte?

Yes

Write Erase

Command Sequence

Add/Data

5555H/AAH

2AAAH/55H

5555H/80H

Six Bus
Cycle
Sequence

5555H/AAH

2AAAH/55H

5555H/10H (Chip Erase)

PA/30H (Sector Erase

DATA Polling or Toggle Bit

Successfully Completed

Erase Complete

51001-14

SyncMOS Technologies Inc.

S29C51001T/S29C51001B

1 MEGABIT (131,072 x 8 BIT)

5 VOLT CMOS FLASH MEMORY

S29C51001T/S29C51001B V1.0 February 2003

Package Diagrams

32-pin Plastic DIP

32-pin PLCC

MAX

0.545/0.555

INDEX-1

.047

+.012
0

0.210 MAX

0.120 MIN

0.010 MIN

.600 TYP

1.660 MAX.

.050 MAX

.100

TYP

.032 +.012

.018

+.006

.002

.010

+.004

.0004

INDEX-2

EJECTOR MARK

.420

.003

- 6

.017

.136

.003

.110

.046

.003

.025

.050 TYP

.450

.003

.490

.005

.045X45

.590

.005

.550

.003

19 18 17 16 15

31 32 1 2 3 4

SyncMOS Technologies Inc.

S29C51001T/S29C51001B

1 MEGABIT (131,072 x 8 BIT)

5 VOLT CMOS FLASH MEMORY

S29C51001T/S29C51001B V1.0 February 2003

Document Outline

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: S29C51001

Document Outline

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: S29C51001