SOLOMON SYSTECH
SEMICONDUCTOR TECHNICAL DATA
This document contains information on a new product. Specifications and information herein are subject to
change without notice.
http://www.solomon-systech.com
SSD1303
Rev 1.7
P 1/56
May 2005
Copyright
2005
Solomon Systech Limited
Advance Information
132 x 64 Dot Matrix
OLED/PLED Segment/Common Driver with Controller
SSD1303
Solomon Systech
May 2005
P 2/56
Rev 1.7
SSD1303
TABLE OF CONTENTS
1
GENERAL INFORMATION ............................................................................................................................5
2
FEATURES .........................................................................................................................................................5
3
ORDERING INFORMATION ..........................................................................................................................6
4
BLOCK DIAGRAM ...........................................................................................................................................7
5
DIE PAD FLOOR PLAN....................................................................................................................................8
6
PIN DESCRIPTION .........................................................................................................................................12
7
FUNCTIONAL BLOCK DESCRIPTIONS....................................................................................................15
7.1
O
SCILLATOR
C
IRCUIT AND
D
ISPLAY
T
IME
G
ENERATOR
..................................................................................15
7.2
R
ESET
C
IRCUIT
................................................................................................................................................15
7.3
C
OMMAND
D
ECODER AND
C
OMMAND
I
NTERFACE
..........................................................................................15
7.4
MPU P
ARALLEL
6800-
SERIES
I
NTERFACE
.......................................................................................................16
7.5
MPU P
ARALLEL
8080-
SERIES
I
NTERFACE
.......................................................................................................16
7.6
MPU S
ERIAL
I
NTERFACE
.................................................................................................................................17
7.7
G
RAPHIC
D
ISPLAY
D
ATA
RAM (GDDRAM) ..................................................................................................17
7.8
C
URRENT
C
ONTROL AND
V
OLTAGE
C
ONTROL
.................................................................................................17
7.9
S
EGMENT
D
RIVERS
/ C
OMMON
D
RIVERS
.........................................................................................................18
7.10
A
REA
C
OLOUR
D
ECODER
.................................................................................................................................18
7.11
DC-DC V
OLTAGE
C
ONVERTER
.......................................................................................................................19
8
COMMAND TABLE ........................................................................................................................................21
8.1
D
ATA
R
EAD
/ W
RITE
........................................................................................................................................24
9
COMMAND DESCRIPTIONS........................................................................................................................25
10
MAXIMUM RATINGS ....................................................................................................................................32
11
DC CHARACTERISTICS ...............................................................................................................................33
12
AC CHARACTERISTICS ...............................................................................................................................34
13
APPLICATION EXAMPLE ............................................................................................................................38
14
SSD1303T3R1 PACKAGE DETAILS.............................................................................................................39
SSD1303T3R1 P
IN
A
SSIGNMENT
................................................................................................................................39
15
SSD1303T6R1 PACKAGE DETAILS.............................................................................................................43
SSD1303T6R1 P
IN
A
SSIGNMENT
................................................................................................................................43
SSD1303T6R1 TAB P
ACKAGE
D
IMENSIONS
..............................................................................................................45
16
SSD1303T8R1 PACKAGE DETAILS.............................................................................................................47
SSD1303T8R1 P
IN
A
SSIGNMENT
................................................................................................................................47
SSD1303T8R1 TAB P
ACKAGE
D
IMENSIONS
..............................................................................................................49
17
SSD1303T9R1 PACKAGE DETAILS.............................................................................................................51
SSD1303T9R1 P
IN
A
SSIGNMENT
................................................................................................................................51
SSD1303T9R1 TAB P
ACKAGE
D
IMENSIONS
..............................................................................................................53
SSD1303
Rev 1.7
P 3/56
May 2005
Solomon Systech
18
SSD1303Z PACKAGE DETAILS ...................................................................................................................55
Solomon Systech
May 2005
P 4/56
Rev 1.7
SSD1303
TABLE OF FIGURES
Figure 1 - Block Diagram.................................................................................................................................. 7
Figure 2 - SSD1303Z Pin Assignment ............................................................................................................. 8
Figure 3 - SSD1303Z Alignment mark dimensions ........................................................................................ 11
Figure 4 - Oscillator Circuit............................................................................................................................. 15
Figure 5 - Display data read back procedure - insertion of dummy read ....................................................... 16
Figure 6 Display data write procedure in SPI mode.................................................................................... 17
Figure 7 - DC-DC voltage converter circuit .................................................................................................... 19
Figure 8 - Horizontal scroll direction............................................................................................................... 25
Figure 9 - Segment current vs Contrast setting ............................................................................................. 26
Figure 10 - 6800-series MPU parallel interface characteristics ..................................................................... 35
Figure 11 - 8080-series MPU parallel interface characteristics ..................................................................... 36
Figure 12 - Serial interface characteristics..................................................................................................... 37
Figure 13 - Application Example (Block Diagram of SSD1303T3)................................................................. 38
Figure 14 - SSD1303T3R1 pin assignment (Copper view, Normal TAB design) .......................................... 39
Figure 15 - SSD1303T6R1 pin assignment (Copper view) ............................................................................ 43
Figure 16 - SSD1303T9R1 pin assignment (Copper view) ............................................................................ 51
LIST OF TABLES
Table 1 - Ordering Information ......................................................................................................................... 6
Table 2 - SSD1303Z Die Pad Coordinates ...................................................................................................... 9
Table 3 - Passive component selection: ........................................................................................................ 20
Table 4 - Command table............................................................................................................................... 21
Table 5 - Read command table ...................................................................................................................... 23
Table 6 - Address increment table (Automatic).............................................................................................. 24
Table 7 - Maximum Ratings ........................................................................................................................... 32
Table 8 - DC Characteristics .......................................................................................................................... 33
Table 9 - AC Characteristics .......................................................................................................................... 34
Table 10 - 6800-Series MPU Parallel Interface Timing Characteristics......................................................... 35
Table 11 - 8080-Series MPU Parallel Interface Timing Characteristics......................................................... 36
Table 12 - Serial Interface Timing Characteristics ......................................................................................... 37
Table 13 - SSD1303T3R1 pin assignment..................................................................................................... 40
Table 14 - SSD1303T6R1 pin assignment..................................................................................................... 44
Table 15 - SSD1303T8R1 pin assignment..................................................................................................... 48
Table 16 - SSD1303T9R1 pin assignment..................................................................................................... 52
SSD1303
Rev 1.7
P 5/56
May 2005
Solomon Systech
1 GENERAL
INFORMATION
The SSD1303 is a single-chip CMOS OLED/PLED driver with controller for organic/polymer light
emitting diode dot-matrix graphic display system. It consists of 132 segments, 64 commons that can
support a maximum display resolution of 132x64. Besides, there are 4-colour selections to support
monochrome or area colour OLED/PLED. This IC is designed for Common Cathode type OLED panel.
The SSD1303 embeds with contrast control, display RAM and oscillator, which reduces the number
of external components and power consumption. It is suitable for many compact portable applications, such
as mobile phone sub-display, calculator and MP3 player, etc.
2 FEATURES
-
Support maximum 132 x 64 dot matrix panel
-
Area colour support with 4 Colour Selection and 64 steps per colour
-
Logic voltage supply: V
DD
= 2.4V - 3.5V
-
High voltage supply: V
CC
= 7.0V - 16.0V
-
Maximum segment output current: 320uA
-
Maximum common sink current: 45mA
-
Embedded 132 x 64 bit SRAM display buffer
-
256-step Contrast Control on monochrome passive OLED panel
- On-Chip
Oscillator
-
Programmable Frame Frequency and Multiplexing Ratio
-
8-bit 6800-series Parallel Interface, 8-bit 8080-series Parallel Interface, Serial Peripheral Interface
-
Row Re-mapping and Column Re-mapping
- Vertical
Scrolling
-
Automatic horizontal scrolling function
-
Low power consumption
-
Wide range of operating temperatures: -40 to 90
C
Solomon Systech
May 2005
P 6/56
Rev 1.7
SSD1303
3 ORDERING
INFORMATION
Table 1 - Ordering Information
Ordering Part Number
SEG
COM
Package Form
Reference
Remark
SSD1303Z
132
64
Gold Bump Die
Page 8
Die size: 9.22mm x 1.55mm
Pad pitch: COM 51.8m SEG 52.2m
SSD1303T3R1 96
64 TAB
Page
39
35mm film
4 sprocket hole
Folding TAB
80 / 68 / SPI interface
Output lead pitch 0.12974mm
SSD1303T6R1 132
64
TAB
Page
43
35mm film
4 sprocket hole
Folding TAB
80 / 68 / SPI interface
Output lead pitch 0.11976
SSD1303T8R1 96
64 TAB
Page
47
35mm film
4 sprocket hole
Folding TAB
80 / 68 / SPI interface
Output lead pitch 0.12974mm
SSD1303T9R1 96
64 TAB
Page
51
35mm film
4 sprocket hole
Folding TAB
80 / 68 / SPI interface
Output lead pitch 0.12974mm
SSD1303
Rev 1.7
P 7/56
May 2005
Solomon Systech
Common Dr
iv
er
s
(
e
v
en)
Segment Dr
iv
er
s
Common Dr
iv
er
s
(
odd)
A
r
ea Col
our Dec
o
rder
D
i
sp
l
a
y
Ti
m
i
ng
Generat
or
Os
c
illa
to
r
GDDRA
M
MC
U
I
n
t
e
rf
ac
e
Com
m
and
Dec
oder
4 BLOCK
DIAGRAM
Figure 1 - Block Diagram
RES#
CS#
D/C
E (RD#)
R/W (WR#)
BS2
BS1
BS0
D7
D6
D5
D4
D3
D2
D1
D0
V
o
l
t
age Cont
rol
Current
Cont
rol
VDD
VSS
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
COM63
COM61
.
.
.
COM3
COM1
SEG131
SEG130
.
.
.
SEG1
SEG0
COM0
COM2
.
.
.
COM60
COM62
.
.
.
.
.
.
.
.
.
.
.
CL
CLS
VD
D
B
VSSB
GD
R
RE
S
E
FB
VBR
E
F
VC
C
VC
O
M
H
VR
EF
IR
EF
VC
L
VSL
Solomon Systech
May 2005
P 8/56
Rev 1.7
SSD1303
5 DIE PAD FLOOR PLAN
Figure 2 - SSD1303Z Pin Assignment
DUMMY (x2)
COM32
COM34
.
.
COM60
COM62
VSS (x3)
VCL (x3)
VSS (x2)
VSL (x3)
VDD
VCC (x2)
VREF
VCOMH (x2)
IREF
ICAS
VDD
CLS
M/S
VSS
D7
D6
D5
D4
D3
D2
D1
D0
VDD
E/RD
R/W
VSS
D/C
RES#
CS#
VSS
DOF#
CL
M
VSS
BS2
VDD
BS1
VSS
BS0
VDD
GPIO1
GPIO0
VCC
VSS
BGGND
SENSE
VBREF
RESE
FB
VDD (x2)
VDDB (x2)
GDR (x2)
VSSB (x2)
VSS
TR0
TR1
TR2
TR3
TR4
TR5
TR6
TR7
TR8
VCOMH (x2)
VCC (x2)
VDD
VSL (x3)
VSSB (x2)
VSS (x2)
VCL (x3)
VSS (x3)
COM63
COM61
.
.
COM35
COM33
DUMMY (x2)
DUMMY
DUMMY
COM30
COM28
COM26
COM24
.
.
.
COM6
COM4
COM2
COM0
SEG0
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
SEG8
SEG9
SEG10
SEG11
SEG12
SEG13
.
.
.
SEG117
SEG118
SEG119
SEG120
SEG121
SEG122
SEG123
SEG124
SEG125
SEG126
SEG127
SEG128
SEG129
SEG130
SEG131
COM1
COM3
COM5
COM7
.
.
.
COM25
COM27
COM29
COM31
DUMMY
DUMMY
PAD 1
Die size
Die height
Bump height
Bump size
Pad 1-18, 113-298
Pad 19-112
T shape
(-3132.9, 79.5)
75um x 75um
+ shape
(3148.9, 79.5)
75um x 75um
Circle
(3433.9, -274.6)
R37.5um, inner 18um
Circle
(-3433.9, -274.6)
R37.5um, inner 18um
34um x 84um
54um x 84um
Alignment mark
9.22mm x 1.55mm
475 +/- 25um
Nominal 18um
Pad 1,2,3,? >130
Gold Bumps face up
SSD1303
X
Y
SSD1303
Rev 1.7
P 9/56
May 2005
Solomon Systech
Table 2 - SSD1303Z Die Pad Coordinates
Pad no. Pad Name
X-pos
Y-pos
Pad no. Pad Name
X-pos
Y-pos
Pad no. Pad Name
X-pos
Y-pos
1
NC
-4535.4
-679.6
61
VCC
-342.9
-679.6
121
COM46
4068.4
-679.6
2
NC
-4483.2
-679.6
62
GPIO0
-267.2
-679.6
122
COM44
4120.2
-679.6
3
COM33
-4431.0
-679.6
63
GPIO1
-190.5
-679.6
123
COM42
4172.0
-679.6
4
COM35
-4379.2
-679.6
64
VDD
-114.3
-679.6
124
COM40
4223.8
-679.6
5
COM37
-4327.4
-679.6
65
BS0
-38.1
-679.6
125
COM38
4275.6
-679.6
6
COM39
-4275.6
-679.6
66
VSS
38.1
-679.6
126
COM36
4327.4
-679.6
7
COM41
-4223.8
-679.6
67
BS1
114.3
-679.6
127
COM34
4379.2
-679.6
8
COM43
-4172.0
-679.6
68
VDD
190.5
-679.6
128
COM32
4431.0
-679.6
9
COM45
-4120.2
-679.6
69
BS2
266.7
-679.6
129
NC
4483.2
-679.6
10
COM47
-4068.4
-679.6
70
VSS
342.9
-679.6
130
NC
4535.4
-679.6
11
COM49
-4016.6
-679.6
71
M
419.1
-679.6
131
NC
4535.4
679.6
12
COM51
-3964.8
-679.6
72
CL
495.3
-679.6
132
NC
4483.2
679.6
13
COM53
-3913.0
-679.6
73
DOF#
571.5
-679.6
133
COM30
4431.0
679.6
14
COM55
-3861.2
-679.6
74
VSS
647.7
-679.6
134
COM28
4379.2
679.6
15
COM57
-3809.4
-679.6
75
CS#
723.9
-679.6
135
COM26
4327.4
679.6
16
COM59
-3757.6
-679.6
76
RES#
800.1
-679.6
136
COM24
4275.6
679.6
17
COM61
-3705.8
-679.6
77
D/C
876.3
-679.6
137
COM22
4223.8
679.6
18
COM63
-3654.0
-679.6
78
VSS
952.5
-679.6
138
COM20
4172.0
679.6
19
VSS
-3543.3
-679.6
79
R/W
1028.7
-679.6
139
COM18
4120.2
679.6
20
VSS
-3467.1
-679.6
80
E/RD
1104.9
-679.6
140
COM16
4068.4
679.6
21
VSS
-3390.9
-679.6
81
VDD
1181.1
-679.6
141
COM14
4016.6
679.6
22
VCL
-3314.7
-679.6
82
D0
1257.3
-679.6
142
COM12
3964.8
679.6
23
VCL
-3238.5
-679.6
83
D1
1333.5
-679.6
143
COM10
3913.0
679.6
24
VCL
-3162.3
-679.6
84
D2
1409.7
-679.6
144
COM8
3861.2
679.6
25
VSS
-3086.1
-679.6
85
D3
1485.9
-679.6
145
COM6
3809.4
679.6
26
VSS
-3009.9
-679.6
86
D4
1562.1
-679.6
146
COM4
3757.6
679.6
27
VSSB
-2933.7
-679.6
87
D5
1638.3
-679.6
147
COM2
3705.8
679.6
28
VSSB
-2857.5
-679.6
88
D6
1714.5
-679.6
148
COM0
3654.0
679.6
29
VSL
-2781.3
-679.6
89
D7
1790.7
-679.6
149
SEG0
3445.2
679.6
30
VSL
-2705.1
-679.6
90
VSS
1866.9
-679.6
150
SEG1
3393.0
679.6
31
VSL
-2628.9
-679.6
91
M/S
1943.1
-679.6
151
SEG2
3340.8
679.6
32
VDD
-2552.7
-679.6
92
CLS
2019.3
-679.6
152
SEG3
3288.6
679.6
33
VCC
-2476.5
-679.6
93
VDD
2095.5
-679.6
153
SEG4
3236.4
679.6
34
VCC
-2400.3
-679.6
94
ICAS
2171.7
-679.6
154
SEG5
3184.2
679.6
35
VCOMH
-2324.1
-679.6
95
IREF
2247.9
-679.6
155
SEG6
3132.0
679.6
36
VCOMH
-2247.9
-679.6
96
VCOMH
2324.1
-679.6
156
SEG7
3079.8
679.6
37
TR8
-2171.7
-679.6
97
VCOMH
2400.3
-679.6
157
SEG8
3027.6
679.6
38
TR7
-2095.5
-679.6
98
VREF
2476.5
-679.6
158
SEG9
2975.4
679.6
39
TR6
-2019.3
-679.6
99
VCC
2552.7
-679.6
159
SEG10
2923.2
679.6
40
TR5
-1943.1
-679.6
100
VCC
2628.9
-679.6
160
SEG11
2871.0
679.6
41
TR4
-1866.9
-679.6
101
VDD
2705.1
-679.6
161
SEG12
2818.8
679.6
42
TR3
-1790.7
-679.6
102
VSL
2781.3
-679.6
162
SEG13
2766.6
679.6
43
TR2
-1714.5
-679.6
103
VSL
2857.5
-679.6
163
SEG14
2714.4
679.6
44
TR1
-1638.3
-679.6
104
VSL
2933.7
-679.6
164
SEG15
2662.2
679.6
45
TR0
-1562.1
-679.6
105
VSS
3009.9
-679.6
165
SEG16
2610.0
679.6
46
VSS
-1485.9
-679.6
106
VSS
3086.1
-679.6
166
SEG17
2557.8
679.6
47
VSSB
-1409.7
-679.6
107
VCL
3162.3
-679.6
167
SEG18
2505.6
679.6
48
VSSB
-1333.5
-679.6
108
VCL
3238.5
-679.6
168
SEG19
2453.4
679.6
49
GDR
-1257.3
-679.6
109
VCL
3314.7
-679.6
169
SEG20
2401.2
679.6
50
GDR
-1181.1
-679.6
110
VSS
3390.9
-679.6
170
SEG21
2349.0
679.6
51
VDDB
-1104.9
-679.6
111
VSS
3467.1
-679.6
171
SEG22
2296.8
679.6
52
VDDB
-1028.7
-679.6
112
VSS
3543.3
-679.6
172
SEG23
2244.6
679.6
53
VDD
-952.5
-679.6
113
COM62
3654.0
-679.6
173
SEG24
2192.4
679.6
54
VDD
-876.3
-679.6
114
COM60
3705.8
-679.6
174
SEG25
2140.2
679.6
55
FB
-800.1
-679.6
115
COM58
3757.6
-679.6
175
SEG26
2088.0
679.6
56
RESE
-723.9
-679.6
116
COM56
3809.4
-679.6
176
SEG27
2035.8
679.6
57
VBREF
-647.7
-679.6
117
COM54
3861.2
-679.6
177
SEG28
1983.6
679.6
58
SENSE
-571.5
-679.6
118
COM52
3913.0
-679.6
178
SEG29
1931.4
679.6
59
BGGND
-495.3
-679.6
119
COM50
3964.8
-679.6
179
SEG30
1879.2
679.6
60
VSS
-419.1
-679.6
120
COM48
4016.6
-679.6
180
SEG31
1827.0
679.6
Solomon Systech
May 2005
P 10/56 Rev 1.7
SSD1303
Pad no. Pad Name
X-pos
Y-pos
Pad no. Pad Name
X-pos
Y-pos
181
SEG32
1774.8
679.6
241
SEG92
-1409.4
679.6
182
SEG33
1722.6
679.6
242
SEG93
-1461.6
679.6
183
SEG34
1670.4
679.6
243
SEG94
-1513.8
679.6
184
SEG35
1618.2
679.6
244
SEG95
-1566.0
679.6
185
SEG36
1566.0
679.6
245
SEG96
-1618.2
679.6
186
SEG37
1513.8
679.6
246
SEG97
-1670.4
679.6
187
SEG38
1461.6
679.6
247
SEG98
-1722.6
679.6
188
SEG39
1409.4
679.6
248
SEG99
-1774.8
679.6
189
SEG40
1357.2
679.6
249
SEG100
-1827.0
679.6
190
SEG41
1305.0
679.6
250
SEG101
-1879.2
679.6
191
SEG42
1252.8
679.6
251
SEG102
-1931.4
679.6
192
SEG43
1200.6
679.6
252
SEG103
-1983.6
679.6
193
SEG44
1148.4
679.6
253
SEG104
-2035.8
679.6
194
SEG45
1096.2
679.6
254
SEG105
-2088.0
679.6
195
SEG46
1044.0
679.6
255
SEG106
-2140.2
679.6
196
SEG47
991.8
679.6
256
SEG107
-2192.4
679.6
197
SEG48
939.6
679.6
257
SEG108
-2244.6
679.6
198
SEG49
887.4
679.6
258
SEG109
-2296.8
679.6
199
SEG50
835.2
679.6
259
SEG110
-2349.0
679.6
200
SEG51
783.0
679.6
260
SEG111
-2401.2
679.6
201
SEG52
730.8
679.6
261
SEG112
-2453.4
679.6
202
SEG53
678.6
679.6
262
SEG113
-2505.6
679.6
203
SEG54
626.4
679.6
263
SEG114
-2557.8
679.6
204
SEG55
574.2
679.6
264
SEG115
-2610.0
679.6
205
SEG56
522.0
679.6
265
SEG116
-2662.2
679.6
206
SEG57
469.8
679.6
266
SEG117
-2714.4
679.6
207
SEG58
417.6
679.6
267
SEG118
-2766.6
679.6
208
SEG59
365.4
679.6
268
SEG119
-2818.8
679.6
209
SEG60
313.2
679.6
269
SEG120
-2871.0
679.6
210
SEG61
261.0
679.6
270
SEG121
-2923.2
679.6
211
SEG62
208.8
679.6
271
SEG122
-2975.4
679.6
212
SEG63
156.6
679.6
272
SEG123
-3027.6
679.6
213
SEG64
104.4
679.6
273
SEG124
-3079.8
679.6
214
SEG65
52.2
679.6
274
SEG125
-3132.0
679.6
215
SEG66
0.0
679.6
275
SEG126
-3184.2
679.6
216
SEG67
-52.2
679.6
276
SEG127
-3236.4
679.6
217
SEG68
-104.4
679.6
277
SEG128
-3288.6
679.6
218
SEG69
-156.6
679.6
278
SEG129
-3340.8
679.6
219
SEG70
-208.8
679.6
279
SEG130
-3393.0
679.6
220
SEG71
-261.0
679.6
280
SEG131
-3445.2
679.6
221
SEG72
-365.4
679.6
281
COM1
-3654.0
679.6
222
SEG73
-417.6
679.6
282
COM3
-3705.8
679.6
223
SEG74
-469.8
679.6
283
COM5
-3757.6
679.6
224
SEG75
-522.0
679.6
284
COM7
-3809.4
679.6
225
SEG76
-574.2
679.6
285
COM9
-3861.2
679.6
226
SEG77
-626.4
679.6
286
COM11
-3913.0
679.6
227
SEG78
-678.6
679.6
287
COM13
-3964.8
679.6
228
SEG79
-730.8
679.6
288
COM15
-4016.6
679.6
229
SEG80
-783.0
679.6
289
COM17
-4068.4
679.6
230
SEG81
-835.2
679.6
290
COM19
-4120.2
679.6
231
SEG82
-887.4
679.6
291
COM21
-4172.0
679.6
232
SEG83
-939.6
679.6
292
COM23
-4223.8
679.6
233
SEG84
-991.8
679.6
293
COM25
-4275.6
679.6
234
SEG85
-1044.0
679.6
294
COM27
-4327.4
679.6
235
SEG86
-1096.2
679.6
295
COM29
-4379.2
679.6
236
SEG87
-1148.4
679.6
296
COM31
-4431.0
679.6
237
SEG88
-1200.6
679.6
297
NC
-4483.2
679.6
238
SEG89
-1252.8
679.6
298
NC
-4535.4
679.6
239
SEG90
-1305.0
679.6
240
SEG91
-1357.2
679.6
SSD1303
Rev 1.7
P 11/56 May 2005
Solomon Systech
Figure 3 - SSD1303Z Alignment mark dimensions
T shape
+ shape
Circle
Unit in um
Solomon Systech
May 2005
P 12/56 Rev 1.7
SSD1303
6 PIN DESCRIPTION
CL
This pin is the system clock input. When internal clock is enabled, this pin should be left open. The internal
clock is output from this pin. When internal oscillator is disabled, this pin receives display clock signal from
external clock source.
CLS
This is the internal clock enable pin. When it is pulled HIGH, internal clock is enabled. When it is pulled
LOW, the internal clock is disabled, an external clock source must be connected to the CL pin for normal
operation
.
BS0, BS1, BS2
These are MCU interface input selection pins. See the following table for selecting different interfaces:
6800-parallel
interface
8080-parallel
interface
Serial
interface
BS0 0
0
0
BS1 0
1
0
BS2 1
1
0
CS#
This pin is the chip select input. The chip is enabled for MCU communication only when CS# had been
pulled low.
RES#
This is a reset signal input pin. When it is pulled LOW, initialization of the chip is executed.
D/C
This is the Data/Command control pin. When it is pulled HIGH, the input at D
7
-D
0
is treated as display data.
When it is pulled LOW, the input at D
7
-D
0
is transferred to the command registers. For detail relationship to
MCU interface signals, please refer to the Timing Characteristics Diagrams.
R/W (WR#)
This is a MCU interface input pin. When 6800-series Parallel Interface mode is selected, this pin is used as
Read/Write (R/W) selection input. Pull this pin to HIGH for read mode and pull it to LOW for write mode.
When 8080-series Parallel Interface mode is selected, this pin is used as Write (WR#) selection input. Pull
this pin to LOW for write mode. Data write operation is initiated when this pin is pulled LOW and the CS# is
pulled LOW.
E (RD#)
This is a MCU interface input pin. When 6800-series Parallel Interface is selected, this pin is used as
Enable (E) signal. Read/Write operation is initiated when this pin is pulled HIGH and the CS# pin is pulled
LOW. When 8080-series Parallel Interface is selected, this pin is used to receive the Read Data (RD#)
signal. Data read operation is initiated when this pin is pulled LOW and CS# pin is pulled LOW.
D
7
-D
0
These are 8-bit bi-directional data bus to be connected to the microprocessor's data bus. When serial
interface mode is selected, D
1
will be the serial data input, SDIN, D
0
will be the serial clock input, SCLK, and
D
2
should be left opened.
SSD1303
Rev 1.7
P 13/56 May 2005
Solomon Systech
VDD
This is a voltage supply pin. It must be connected to external source.
VSS
This is a ground pin. It also acts as a reference for the logic pins and the OLED driving voltages. It must be
connected to external ground.
BGGND
This is a ground pin for analog circuits. It must be connected to external ground
VCC
This is the most positive voltage supply pin of the chip. It should be supplied externally.
VREF
This is a voltage reference pin for pre-charge voltage in driving OLED device. Voltage should be set to
match with the OLED driving voltage in current drive phase. It can either be supplied externally or by
connecting to VCC.
IREF
This is a segment current reference pin. A resistor should be connected between this pin and V
SS
. Set the
current at 10uA.
VCOMH
This is an input pin for the voltage output high level for COM signals. A capacitor should be connected
between this pin and VSS.
VDDB This is a power supply pin for the internal buffer of the DC-DC voltage converter. It must be
connected to V
DD
when the converter is used.
VSSB
This is a ground pin for the internal buffer of the DC-DC voltage converter. It must be connected to V
SS
when the converter is used.
GDR
This is an output pin drives the gate of the external NMOS of the booster circuit.
RESE
This is a source current pin of the external NMOS of the booster circuit.
VB
REF
This is an internal voltage reference pin for booster circuit. A stabilization capacitor, typ. 1uF, should be
connected to Vss.
FB
This is a feedback resistor input pin for the booster circuit. It is used to adjust the booster output voltage
level, Vcc.
COM0-COM63
These are pins provided the Common switch signals to the OLED panel. They are in high impedance state
when display is OFF.
Solomon Systech
May 2005
P 14/56 Rev 1.7
SSD1303
SEG0-SEG131
These are pins provided the Segment switch signals to the OLED panal. They are in high impedance stage
when display is OFF.
TR0-TR8, GPIO0, GPIO1, ICAS, M and DOF#
These are reserved pins. No connection necessary and should be left open individually.
VSL
This is a segment voltage reference pin. This pin should be connected to VSS
externally.
VCL
This is a common voltage reference pin. This pin should be connected to VSS externally.
M/S
This pin must be connected to VDD to enable the chip.
NC
Dummy pad. Do not group or short NC pins together.
SSD1303
Rev 1.7
P 15/56 May 2005
Solomon Systech
7 FUNCTIONAL BLOCK DESCRIPTIONS
7.1 Oscillator Circuit and Display Time Generator
Figure 4 - Oscillator Circuit
This module is an On-Chip low power RC oscillator circuitry (Figure 4). The oscillator generates the clock
for the Display Timing Generator.
7.2 Reset Circuit
When RES# pin is pulled LOW, the chip is initialized with the following status:
1. Display is OFF
2. 132 x 64 Display Mode
3. Normal segment and display data column address and row address mapping (SEG0 is mapped to
column address 00H and COM0 is mapped to row address 00H)
4. Shift register data clear in serial interface
5. Display start line is set at display RAM address 0
6. Column address counter is set at 0
7. Normal scan direction of the COM outputs
8. Contrast control register is set at 80H
9. DC/DC
enable
7.3 Command Decoder and Command Interface
This module determines whether the input data is interpreted as data or command. When the D/C# pin is
pulled HIGH, the inputs at D
7
-D
0
are interpreted as data and be written to Graphic Display Data RAM
(GDDRAM). When it is pulled LOW, the inputs at D
7
-D
0
are interpreted as command, they will be decoded
and be written to the corresponding command registers.
Divider
Internal
Oscillator
M
U
X
CL
CLK
DCLK
Internal
Display
Clock
Solomon Systech
May 2005
P 16/56 Rev 1.7
SSD1303
7.4 MPU Parallel 6800-series Interface
The parallel interface consists of 8 bi-directional data pins (D
7
-D
0
), R/W (WR#), E (RD#), D/C, CS#. When
the R/W (WR#) pin is pulled HIGH, Read operation from the Graphic Display Data RAM (GDDRAM) or the
status register occurs. When the R/W (WR#) pin is pulled LOW, Write operation to Display Data RAM or
Internal Command Registers occurs, depending on the status of D/C input. The E (RD#) input serves as
data latch signal (clock) when HIGH provided that CS# is LOW. Refer to Parallel Interface Timing Diagram
of 6800-series microprocessors.
In order to match the operating frequency of display RAM with that of the microprocessor, some pipeline
processing is internally performed, which requires the insertion of a dummy read before the first actual
display data read. This is shown in Figure 5 below.
Figure 5 - Display data read back procedure - insertion of dummy read
7.5 MPU Parallel 8080-series Interface
The parallel interface consists of 8 bi-directional data pins (D
7
-D
0
), R/W (WR#), E (RD#), D/C, CS#. The E
(RD#) input serves as data read latch signal (clock) when it is LOW provided that CS# is LOW. Display data
or status register read is controlled by D/C signal.
R/W (WR#) input serves as data write latch signal (clock) when it is HIGH and provided that CS# is LOW.
Display data or command register write is controlled by D/C. Refer to Parallel Interface Timing Diagram of
8080-series microprocessor. Similar to 6800-series interface, a dummy read is also required before the first
actual display data read.
n+2
n+1
Write column
address
Dummy read
Data read1
R/W#
(W/R#)
Data bus
N
n
E (RD#)
Data read2
Data read3
SSD1303
Rev 1.7
P 17/56 May 2005
Solomon Systech
7.6 MPU Serial Interface
The serial interface consists of serial clock SCLK, serial data SDIN, D/C#, CS#. In SPI mode, D0 acts as
SCLK, D1 acts as SDIN. For the unused data pins, D2 should be left open. D3 to D7, E and R/W pins can
be connected to external ground.
SDIN is shifted into an 8-bit shift register on every rising edge of SCLK in the order of D
7
, D
6
, ... D
0
. D/C# is
sampled on every eighth clock and the data byte in the shift register is written to the Display Data RAM or
command register in the same clock.
During data writing, an additional NOP command should be inserted before the CS# goes high (Refer to
Figure 6.
Figure 6 Display data write procedure in SPI mode
D7
D6
D5
D4
D3
D2
D1
D0
SCLK(D0)
SDIN(D1)
DB1
DB2
DBn
NOP COMMAND
CS#
D/C
SDIN/
SCLK
7.7 Graphic Display Data RAM (GDDRAM)
The GDDRAM is a bit mapped static RAM holding the bit pattern to be displayed. The size of the RAM is
132 x 64 bits. For mechanical flexibility, re-mapping on both Segment and Common outputs can be
selected by software.
For vertical scrolling of the display, an internal register storing display start line can be set to control the
portion of the RAM data to be mapped to the display.
7.8 Current Control and Voltage Control
This block is used to derive the incoming power sources into different levels of internal use voltage and
current. VCC and VDD are external power supplies. VREF is reference voltage, which is used to derive the
driving voltage for segments and commons. IREF is a reference current source for segment current drivers.
Solomon Systech
May 2005
P 18/56 Rev 1.7
SSD1303
7.9 Segment Drivers / Common Drivers
Segment drivers deliver 132 current sources to drive OLED panel. The driving current can be adjusted from
0 to 300uA with 256 steps. Common drivers generate voltage scanning pulses.
7.10 Area Colour Decoder
Page 0 and Page 1 of the display are divided into 32 banks. Bank16 and Bank32 comprise of a display area
of 12 x 8 pixels. Other banks (0~15 & 17~31) have matrices of 8 x 8 pixels. Each bank can be programmed
to any one of the four colours (colour A, B, C, D). Detailed operation can be referred to the Command
Table.
Page 0, bank
1
Page 0, bank 16
Page 1, bank
17
Page 1, bank 32
Bank 0 (background)
Page 2 Page 7
SSD1303
Rev 1.7
P 19/56 May 2005
Solomon Systech
7.11 DC-DC Voltage Converter
It is a switching voltage generator circuit, designed for handheld applications. In SSD1303, internal DC-DC
voltage converter accompanying with an external application circuit (shown in below figure) can generate a
high voltage supply V
CC
from a low voltage supply input V
DD
. V
CC
is the voltage supply to the OLED driver
block. Below application circuit is an example for the input voltage of 3V VDD to generate V
CC
of 12V
@0mA ~ 20mA application.
Figure 7 - DC-DC voltage converter circuit
VDDB
VBREF
VSSB
GDR
RESE
FB
+
VDD
AGND
+
DGND
AGND
+
AGND
+
VCC
L1
D1
Q1
R1
R2
+
C4
C3
C2
C1
C5
+
C6
+
C7
R3
Remark:
1.
VSSB is tied to VSS on SSD1303T3 package.
2.
L1, D1, Q1, C5 should be grouped closed together on PCB layout.
3.
R1, R2, C1, C4 should be grouped closed together on PCB layout.
4.
The VCC output voltage level can be adjusted by R1and R2, the reference formula is:
VCC = 1.2 x (R1+R2) / R2
The value of (R1+R2) should be between 500k to 1M Ohm.
Solomon Systech
May 2005
P 20/56 Rev 1.7
SSD1303
Table 3 - Passive component selection:
Components Typical
Value
Remark
L1 Inductor,
10H
1A
D1
Schottky diode
1A, 25V e.g. 1N5822, BAT54 [Philips
Semiconductors]
Q1
MOSFET
N-FET with low R
DS
(on) and low Vth voltage.
e.g. MGSF1N02LT1 [ON SEMI]
R1, R2
Resistor
1%,1/10W
R3
Resistor, 1.2
1%, 1/2W
C1 Capacitor,
1F
16V
C2
Capacitor, 6.8F
Low ESR, 25V
C3 Capacitor,
1F
16V
C4 Capacitor,
10nF
16V
C5
Capacitor, 1 ~ 10 F
16V
C6
Capacitor, 0.1 ~ 1F
16V
C7 Capacitor,
15nF
16V
SSD1303
Rev 1.7
P 21/56 May 2005
Solomon Systech
8 COMMAND
TABLE
Table 4 - Command table
(D/C =0, R/W (WR#)=0, E (RD#)=1)
Note: commands marked with "**" are compatible to SSD1301
D/C Hex D7 D6 D5 D4 D3 D2 D1 D0
Command
Description
0
0 0 0 0 X
3
X
2
X
1
X
0
00~0F
Set Lower Column
Address **
Set the lower nibble of the column address register
using X
3
X
2
X
1
X
0
as data bits. The initial display line
register is reset to 0000b after POR.
0 10~1F 0 0 0 1 X
3
X
2
X
1
X
0
Set Higher Column
Address **
Set the higher nibble of the column address register
using X
3
X
2
X
1
X
0
as data bits. The initial display line
register is reset to 0000b after POR.
0
26
0
0
1
0
0
1
1
0 Horizontal scroll setup
A[2:0] Set the number of column scroll per step
0 A[2:0] * * * * * A
2
A
1
A
0
Valid value: 001b, 010b, 011b, 100b
0 B[2:0] * * * * * B
2
B
1
B
0
B[2:0] Define start page address
0 C[1:0] * * * * * * C
1
C
0
C[1:0] Set time interval between each scroll step in
terms of frame frequency
0 D[2:0] * * * * * D
2
D
1
D
0
00b 12 frame
01b 64 frames
10b 128 frames
11b 256 frames
D[2:0] Define end page address
Set the value of D[2:0] larger or equal to B[2:0]
0
0 0 1 0 1 1 1 1
2F
Activate horizontal scroll Start horizontal scrolling
0
0 0 1 0 1 1 1 0
2E
Deactivate horizontal
scroll
Stop horizontal scrolling
0 40-7F
0 1
X
5
X
4
X
3
X
2
X
1
X
0
Set Display Start Line
Set display TAM display start line register from 0-63
using X
5
X
3
X
2
X
1
X
0
.
Display start line register is reset to 000000 during
POR
0 81 1 0 0 0 0 0 0 1
0 A[7:0] A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
Set Contrast Control
Register **
Double byte command to select 1 out of 256 contrast
steps. Contrast increases as the value increases.
(POR = 80h)
0 82 1 0 0 0 0 0 1 0
0 A[7:0] A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
Brightness for color
banks
Double byte command to select 1 out of 256
brightness steps. Brightness increases as the value
increases. (POR = 80h)
0
91
1
0
0
1
0
0
0
1
Set current drive pulse width of Bank 0, Colour A, B
and C.
0 X[5:0] * * X
5
X
4
X
3
X
2
X
1
X
0
Bank 0: X[5:0] = 0... 63; for pulse width set to 1 ~
64 clocks (POR = 110001b)
0 A[5:0] * * A
5
A
4
A
3
A
2
A
1
A
0
Colour A: A[5:0] same as above (POR = 111111b)
0 B[5:0] * * B
5
B
4
B
3
B
2
B
1
B
0
Colour B: B[5:0] same as above (POR = 111111b)
0 C[5:0] * * C
5
C
4
C
3
C
2
C
1
C
0
Colour C: C[5:0] same as above (POR = 111111b)
Set Look Up Table
(LUT) for area colour
Note: colour D pulse width is fixed at 64 clocks
pulse .
Solomon Systech
May 2005
P 22/56 Rev 1.7
SSD1303
D/C Hex D7 D6 D5 D4 D3 D2 D1 D0
Command
Description
0
92
1
0
0
1
0
0
1
0
A[1:0] : 00, 01, 10, or 11 for Colour = A, B, C or D of
bank 1
0 A[7:0] A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
A[3:2] : 00, 01, 10, or 11 for Colour = A, B, C or D
of bank 2
0 B[7:0] B
7
B
6
B
5
B
4
B
3
B
2
B
1
B
0
:
0 C[7:0] C
7
C
6
C
5
C
4
C
3
C
2
C
1
C
0
:
0 D[7:0] D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
D[7:6]: 00, 01, 10, or 11 for Colour = A, B, C or D of
bank 16
Set bank colour of for
bank 1-16 (Page 0)
0
93
1
0
0
1
0
0
1
1
A[1:0] : 00, 01, 10, or 11 for Colour = A, B, C or D of
bank 17
0 A[7:0] A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
A[3:2] : 00, 01, 10, or 11 for Colour = A, B, C or D
of bank 18
0 B[7:0] B
7
B
6
B
5
B
4
B
3
B
2
B
1
B
0
:
0 C[7:0] C
7
C
6
C
5
C
4
C
3
C
2
C
1
C
0
:
0 D[7:0] D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
D[7:6]: 00, 01, 10, or 11 for Colour = A, B, C or D of
bank 32
Set bank colour of for
bank 17-32 (Page 1)
X
0
=0: column address 0 is mapped to SEG0 (POR)
0 A0~
A1 1 0 1 0 0 0 0
X
0
Set Segment Re-map **
X
0
=1: column address 131 is mapped to SEG0
X
0
=0: normal display (POR)
X
0
=1: entire display ON
0 A4~A5 1 0 1 0 0 1 0 X
0
Set Entire Display
ON/OFF **
X
0
=0: normal display (POR)
0 A6~A7 1 0 1 0 0 1 1 X
0
Set
Normal/Inverse
Display **
X
0
=1: inverse display
0 A8 1 0 1 0 1 0 0 0
0 A[5:0] * * A
5
A
4
A
3
A
2
A
1
A
0
Set Multiplex Ratio **
The next command, A[5:0] determines multiplex ratio
N from 16MUX-64MUX, POR= 64MUX
0 AA
1 0 1 0 1 0 1 0 NOP
Reserved,
do
not
use
0
AB
1
0 1
0
1
0
1 1
NOP
Reserved, do not use
0
0
AD
1
1
0
0
1
0
0
0
1
1
1
0
0
1
1
X
0
Set DC-DC on/off
X
0
: 1
DC-DC will be turned on when display on
(POR)
0
DC-DC is disable
X
0
=0: turns OFF OLED panel (POR)
0 AE~AF 1 0 1 0 1 1 1 X
0
Set Display ON/OFF **
X
0
=1: turns ON OLED panel
0 B0~BF 1 0 1 1 X
3
X
2
X
1
X
0
Set Page Address **
Set GDDRAM Page Address (0~7) for read/write
using X
3
X
2
X
1
X
0
0 C0/C8 1 1 0 0 X
3
*
*
* Set COM Output Scan
Direction **
X
3
=0: normal mode (POR) Scan from COM 0 to COM
[N 1]
X
3
=1: remapped mode. Scan from COM [N-1] to
COM0
Where N is the Multiplex ratio.
0 D0-D1 1 1 0 1 0 0 0 X
0
Reserved
Reserved, do not use
SSD1303
Rev 1.7
P 23/56 May 2005
Solomon Systech
D/C Hex D7 D6 D5 D4 D3 D2 D1 D0
Command
Description
0 D3 1 1 0 1 0 0 1 1
Set
vertical
scroll
by
COM
from
0-63.
0 A[5:0] * * A
5
A
4
A
3
A
2
A
1
A
0
Set Display Offset **
The value is reset to 00H after POR.
0 D5 1 1 0 1 0 1 0 1 Set
Display
Clock
Divide Ratio/Oscillator
Frequency
A[3:0] Define the divide ratio of the display clocks
(DCLK):
0 A[7:0] A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
Divide ratio= A[3:0] + 1, POR is 0000b (divide ratio =
1)
A[7:4] Set the Oscillator Frequency. Oscillator
Frequency increases with the value of A[7:4] and vice
versa. POR is 0111b
0 D8 1 1 0 1 1 0 0 0
X
5
X
4
= 00 (POR) : mono mode
0 0
0
X
5
X
4
0 X
2
0 X
0
Set area colour mode
on/off & low power
display mode
X
5
X
4
= 11 Area Colour enable
X
2
=0 and X
0
=0: Normal (POR) power mode
X
2
=1 and X
0
=1: Set low power save mode
0
D9
1
1
0
1
1
0
0
1 Set Pre-charge period** A[3:0] Phase 1 period of up to 15 dclk clocks
[POR=2h]; 0 is invalid entry
0 A[7:0] A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
A[7:4] Phase 2 period of up to 15 dclk clocks
[POR=2h]; 0 is invalid entry
0 DA 1 1 0 1 1 0 1 0
X
4
=0, Sequential COM pin configuration
0
0
0
0
X
4
0
0
1
0
(i.e. COM31, 30, 29....0 ; SEG0-132;
COM31,32....62,63)
X
4
=1(POR), Alternative COM pin configuration
Set COM pins hardware
configuration
(i.e. COM62,60,58,...2,0; SEG0-132;
COM1,3,5...61,63)
0 DB 1 1 0 1 1 0 1 1 Set
VCOM
Deselect
Level
A[6:0] 0000000 low VCOM deselect level (~ 0.43
Vref)
0 A[6:0] * A
6
A
5
A
4
A
3
A
2
A
1
A
0
0110101 normal VCOM deselect level (~ 0.77*Vref
(POR))
1111111 high VCOM deselect level (equal Vref)
0 E2 1 1 1 0 0 0 1 0 Reserved
Reserved
0 E3 1 1 1 0 0 0 1 1 NOP
**
Command
for
No
Operation
0 F* 1 1 1 1 * * * *
Reserved
Reserved, do not use
Note: Remark "*" stands for "Don't Care"
Table 5 - Read command table
Solomon Systech
May 2005
P 24/56 Rev 1.7
SSD1303
(D/C=0, R/W (WR#)=1, E (RD#)=1 for 6800 or E (RD#)=0 for 8080)
Bit Pattern
Command
Description
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
Status Register Read *
D
7
: Reserve
D
6
: "1" for display OFF / "0" for display ON
D
5 :
Reserve
D
4 :
Reserve
D
3 :
Reserve
D
2 :
Reserve
D
1 :
Reserve
D
0 :
Reserve
Note: Patterns other than that given in Command Table are prohibited to enter to the chip as a command; otherwise, unexpected result
will occur.
8.1 Data Read / Write
To read data from the GDDRAM, input HIGH to R/W (WR#) pin and D/C pin for 6800-series parallel mode,
LOW to E (RD#) pin and HIGH to D/C# pin for 8080-series parallel mode. No data read is provided in serial
mode operation.
In normal data read mode, GDDRAM column address pointer will be increased by one automatically after
each data read.
Also, a dummy read is required before the first data read. See Figure 5 in Functional Block Description.
To write data to the GDDRAM, input LOW to R/W (WR#) pin and HIGH to D/C pin for 6800-series parallel
mode AND 8080-series parallel mode. For serial interface mode, it is always in write mode. GDDRAM
column address pointer will be increased by one automatically after each data write.
Table 6 - Address increment table (Automatic)
D/C
R/W (WR#)
Comment
Address Increment
0 0
Write
Command No
0 1 Read
Status No
1 0 Write
Data Yes
1 1 Read
Data Yes*1
*1. If read-data command is issued in read-modify-write mode, address increase is not applied.
SSD1303
Rev 1.7
P 25/56 May 2005
Solomon Systech
9 COMMAND
DESCRIPTIONS
Set Lower Column Address
This command specifies the lower nibble of the 8-bit column address of the display data RAM. The column
address will be incremented by each data access after it is pre-set by the MCU.
Set Higher Column Address
This command specifies the higher nibble of the 8-bit column address of the display data RAM. The column
address will be incremented by each data access after it is pre-set by the MCU.
Activate Horizontal Scroll
Start motion of horizontal scrolling. This command should only be issued after Horizontal scroll setup
parameters are defined.
The following actions are prohibited after the horizontal scroll is activated
1.
RAM access (Data write or read)
2.
Changing horizontal scroll setup parameters
The SSD1303 horizontal scroll is designed for 128 columns scrolling only. 4 remaining columns are
reserved for computation and should be left open.
With column address 0 mapped to SEG0 (Segment remap setting = A0h), the 4 unused columns will be
SEG128, SEG129, SEG130, SEG131.
With column address 0 mapped to SEG131 (Segment remap setting = A1h), the 4 unused columns will be
SEG0, SEG1, SEG2, SEG3.
Figure 8 - Horizontal scroll direction
REMAP
SETTING
SEG
0
SEG
1
SEG
2
SEG
3
SEG
4
SEG
5
...
...
...
SEG
126
SEG
127
SEG
128
SEG
129
SEG
130
SEG
131
A0
A
B
C
D
E
F
!
!
!
Y
Z
Invalid data
A1
Invalid data
Z
Y
"
"
"
F
E
D
C
B
A
Scroll direction
Solomon Systech
May 2005
P 26/56 Rev 1.7
SSD1303
Deactivate Horizontal Scroll
Stop motion of horizontal scrolling.
Horizontal Scroll Setup
This command consists of 5 consecutive bytes to set up the horizontal scroll parameters. It determined the
scrolling start page, end page and the scrolling speed.
Before issuing this command, the horizontal scroll must be deactivated (2Eh). Otherwise, ram content may
be corrupted.
Set Display Start Line
This command is to set Display Start Line register to determine starting address of display RAM to be
displayed by selecting a value from 0 to 63. With value equals to 0, D
0
of Page 0 is mapped to COM0. With
value equals to 1, D
1
of Page0 is mapped to COM0. The display start line values of 0 to 63 are assigned to
Page 0 to 7.
Set Contrast Control Register
This command is to set Contrast Setting of the display. The chip has 256 contrast steps from 00 to FF. The
segment output current increases as the contrast step value increases. See Figure 9.
Figure 9 - Segment current vs Contrast setting
Segm ent current vs Contrast setting
0
50
100
150
200
250
300
350
00
0F
1F
2F
3F
4F
5F
6F
7F 8F 9F AF BF CF DF EF FF
Contrast setting
Current (uA)
Set Brightness for Color Banks
This command is to set Brightness Setting of the display for area colors banks (except bank 0). The chip
has 256 brightness steps from 00 to FF. The segment output current increases as the brightness step value
increases
Segment output current setting:
Iseg = Cr/256 * Iref * scale factor
Where:
Cr is contrast step
Iref is reference current equals 10uA
Scale factor =32
SSD1303
Rev 1.7
P 27/56 May 2005
Solomon Systech
Set Look Up Table (LUT) for area colour
SSD1303 provides 4 colour (pulse width) settings - Colour A, B, C and D. The colour intensity (or grey
scale) is defined by the current drive pulse width. The pulse width of colour A, B, C can be programmable
from 1 to 64 DCLK* duration. The colour D is fixed at 64 DCLK pulse width. This colour setting has to be
stored in the Look Up Table (LUT).
For the background colour, the colour intensity is defined by a variable X[5:0].
Set LUT command:
10010001
X[5:0]
A[5:0]
B[5:0]
C[5:0]
Description
Number
of
DCLKs
Bank 0
Set background colour
X[5:0]
Colour A
Set Pulse Width A
A[5:0]
Colour B
Set Pulse Width B
B[5:0]
Colour C
Set Pulse Width C
C[5:0]
Colour D
Pulse width D is fixed to 64
DCLK
64 (fixed)
DCLK: Internal Display Clock
Set
bank colour of bank 1-16 (Page 0) and bank colour of bank 17-32 (Page 1)
Next step is to define the colour of each display area. The 132x64 display matrix is divided into 8 pages of 8
commons per pages. The first two pages, page 0 and page 1, are divided into 32 banks: Bank16 and
Bank32 comprise of a display area of 12x8 pixels. Other banks (0~15 & 17~31) have matrices of 8x8 pixels.
Each bank can be programmable to any 1 of the 4 colour (A, B, C, D). User can use 92h and 93h command
for the bank colour setting. Note: Only applicable in area colour mode.
Set Segment Re-map
This command changes the mapping between the display data column address and segment driver. It
allows flexibility in OLED module design. Refer to Command Table.
Set Entire Display ON/OFF
This command forces the entire display to be "ON" regardless of the contents of the display data RAM. This
command has priority over normal/reverse display. This command will be used with "Set Display ON/OFF"
command to form a compound command for entering power save mode.
Set Normal/Inverse Display
This command sets the display to be either normal/inverse. In normal display, a RAM data of 1 indicates an
"ON" pixel while in inverse display; a RAM data of 0 indicates an "ON" pixel.
Set Multiplex Ratio
This command switches default 63 multiplex mode to any multiplex ratio from 2 to 63. The output pads
COM0-COM63 will be switched to corresponding COM signal.
Set DC-DC on/off
This command is to control the DC-DC voltage converter. The converter will be turned on by issuing this
command then DISPLAY ON command. The panel display must be off while issuing this command.
POR the DC-DC will be turned on.
Solomon Systech
May 2005
P 28/56 Rev 1.7
SSD1303
Set Display ON/OFF
This command turns the display ON or OFF. When the display is OFF, the segment and common output
are in high impedance state.
Set Page Address
This command positions the page address from 0 to 7 in GDDRAM. Refer to Command Table.
Set COM Output Scan Direction
This command sets the scan direction of the COM output allowing layout flexibility in OLED module design.
In addition, the display will have immediate effect once this command is issued. That is, if this command is
sent during normal display, the graphic display will be vertically flipped.
Set Display Offset
This is a double byte command. The next command specifies the mapping of display start line to one of
COM0-63 (it is assumed that COM0 is the display start line, display start line register equals to 0).
For example, to move the COM16 towards the COM0 direction for 16 lines, the 6-bit data in the second byte
should be given by 010000. To move in the opposite direction by 16 lines, the 6-bit data should be given by
(64 16) and so the second byte should be 100000.
SSD1303
Rev 1.7
P 29/56 May 2005
Solomon Systech
Set MUX ratio(A8)
COM Normal / Remapped (C0 / C8)
Display offset (D3)
Display start line (40 - 7F)
COM0
Row0
RAM0
Row8
RAM8
Row0
RAM8
Row0
RAM0
Row8
RAM8
Row0
RAM8
COM1
Row1
RAM1
Row9
RAM9
Row1
RAM9
Row1
RAM1
Row9
RAM9
Row1
RAM9
COM2
Row2
RAM2
Row10
RAM10
Row2
RAM10
Row2
RAM2
Row10
RAM10
Row2
RAM10
COM3
Row3
RAM3
Row11
RAM11
Row3
RAM11
Row3
RAM3
Row11
RAM11
Row3
RAM11
COM4
Row4
RAM4
Row12
RAM12
Row4
RAM12
Row4
RAM4
Row12
RAM12
Row4
RAM12
COM5
Row5
RAM5
Row13
RAM13
Row5
RAM13
Row5
RAM5
Row13
RAM13
Row5
RAM13
COM6
Row6
RAM6
Row14
RAM14
Row6
RAM14
Row6
RAM6
Row14
RAM14
Row6
RAM14
COM7
Row7
RAM7
Row15
RAM15
Row7
RAM15
Row7
RAM7
Row15
RAM15
Row7
RAM15
COM8
Row8
RAM8
Row16
RAM16
Row8
RAM16
Row8
RAM8
Row16
RAM16
Row8
RAM16
COM9
Row9
RAM9
Row17
RAM17
Row9
RAM17
Row9
RAM9
Row17
RAM17
Row9
RAM17
COM10
Row10
RAM10
Row18
RAM18
Row10
RAM18
Row10
RAM10
Row18
RAM18
Row10
RAM18
COM11
Row11
RAM11
Row19
RAM19
Row11
RAM19
Row11
RAM11
Row19
RAM19
Row11
RAM19
COM12
Row12
RAM12
Row20
RAM20
Row12
RAM20
Row12
RAM12
Row20
RAM20
Row12
RAM20
COM13
Row13
RAM13
Row21
RAM21
Row13
RAM21
Row13
RAM13
Row21
RAM21
Row13
RAM21
COM14
Row14
RAM14
Row22
RAM22
Row14
RAM22
Row14
RAM14
Row22
RAM22
Row14
RAM22
COM15
Row15
RAM15
Row23
RAM23
Row15
RAM23
Row15
RAM15
Row23
RAM23
Row15
RAM23
COM16
Row16
RAM16
Row24
RAM24
Row16
RAM24
Row16
RAM16
Row24
RAM24
Row16
RAM24
COM17
Row17
RAM17
Row25
RAM25
Row17
RAM25
Row17
RAM17
Row25
RAM25
Row17
RAM25
COM18
Row18
RAM18
Row26
RAM26
Row18
RAM26
Row18
RAM18
Row26
RAM26
Row18
RAM26
COM19
Row19
RAM19
Row27
RAM27
Row19
RAM27
Row19
RAM19
Row27
RAM27
Row19
RAM27
COM20
Row20
RAM20
Row28
RAM28
Row20
RAM28
Row20
RAM20
Row28
RAM28
Row20
RAM28
COM21
Row21
RAM21
Row29
RAM29
Row21
RAM29
Row21
RAM21
Row29
RAM29
Row21
RAM29
COM22
Row22
RAM22
Row30
RAM30
Row22
RAM30
Row22
RAM22
Row30
RAM30
Row22
RAM30
COM23
Row23
RAM23
Row31
RAM31
Row23
RAM31
Row23
RAM23
Row31
RAM31
Row23
RAM31
COM24
Row24
RAM24
Row32
RAM32
Row24
RAM32
Row24
RAM24
Row32
RAM32
Row24
RAM32
COM25
Row25
RAM25
Row33
RAM33
Row25
RAM33
Row25
RAM25
Row33
RAM33
Row25
RAM33
COM26
Row26
RAM26
Row34
RAM34
Row26
RAM34
Row26
RAM26
Row34
RAM34
Row26
RAM34
COM27
Row27
RAM27
Row35
RAM35
Row27
RAM35
Row27
RAM27
Row35
RAM35
Row27
RAM35
COM28
Row28
RAM28
Row36
RAM36
Row28
RAM36
Row28
RAM28
Row36
RAM36
Row28
RAM36
COM29
Row29
RAM29
Row37
RAM37
Row29
RAM37
Row29
RAM29
Row37
RAM37
Row29
RAM37
COM30
Row30
RAM30
Row38
RAM38
Row30
RAM38
Row30
RAM30
Row38
RAM38
Row30
RAM38
COM31
Row31
RAM31
Row39
RAM39
Row31
RAM39
Row31
RAM31
Row39
RAM39
Row31
RAM39
COM32
Row32
RAM32
Row40
RAM40
Row32
RAM40
Row32
RAM32
Row40
RAM40
Row32
RAM40
COM33
Row33
RAM33
Row41
RAM41
Row33
RAM41
Row33
RAM33
Row41
RAM41
Row33
RAM41
COM34
Row34
RAM34
Row42
RAM42
Row34
RAM42
Row34
RAM34
Row42
RAM42
Row34
RAM42
COM35
Row35
RAM35
Row43
RAM43
Row35
RAM43
Row35
RAM35
Row43
RAM43
Row35
RAM43
COM36
Row36
RAM36
Row44
RAM44
Row36
RAM44
Row36
RAM36
Row44
RAM44
Row36
RAM44
COM37
Row37
RAM37
Row45
RAM45
Row37
RAM45
Row37
RAM37
Row45
RAM45
Row37
RAM45
COM38
Row38
RAM38
Row46
RAM46
Row38
RAM46
Row38
RAM38
Row46
RAM46
Row38
RAM46
COM39
Row39
RAM39
Row47
RAM47
Row39
RAM47
Row39
RAM39
Row47
RAM47
Row39
RAM47
COM40
Row40
RAM40
Row48
RAM48
Row40
RAM48
Row40
RAM40
Row48
RAM48
Row40
RAM48
COM41
Row41
RAM41
Row49
RAM49
Row41
RAM49
Row41
RAM41
Row49
RAM49
Row41
RAM49
COM42
Row42
RAM42
Row50
RAM50
Row42
RAM50
Row42
RAM42
Row50
RAM50
Row42
RAM50
COM43
Row43
RAM43
Row51
RAM51
Row43
RAM51
Row43
RAM43
Row51
RAM51
Row43
RAM51
COM44
Row44
RAM44
Row52
RAM52
Row44
RAM52
Row44
RAM44
Row52
RAM52
Row44
RAM52
COM45
Row45
RAM45
Row53
RAM53
Row45
RAM53
Row45
RAM45
Row53
RAM53
Row45
RAM53
COM46
Row46
RAM46
Row54
RAM54
Row46
RAM54
Row46
RAM46
Row54
RAM54
Row46
RAM54
COM47
Row47
RAM47
Row55
RAM55
Row47
RAM55
Row47
RAM47
Row55
RAM55
Row47
RAM55
COM48
Row48
RAM48
Row56
RAM56
Row48
RAM56
Row48
RAM48
-
-
Row48
RAM56
COM49
Row49
RAM49
Row57
RAM57
Row49
RAM57
Row49
RAM49
-
-
Row49
RAM57
COM50
Row50
RAM50
Row58
RAM58
Row50
RAM58
Row50
RAM50
-
-
Row50
RAM58
COM51
Row51
RAM51
Row59
RAM59
Row51
RAM59
Row51
RAM51
-
-
Row51
RAM59
COM52
Row52
RAM52
Row60
RAM60
Row52
RAM60
Row52
RAM52
-
-
Row52
RAM60
COM53
Row53
RAM53
Row61
RAM61
Row53
RAM61
Row53
RAM53
-
-
Row53
RAM61
COM54
Row54
RAM54
Row62
RAM62
Row54
RAM62
Row54
RAM54
-
-
Row54
RAM62
COM55
Row55
RAM55
Row63
RAM63
Row55
RAM63
Row55
RAM55
-
-
Row55
RAM63
COM56
Row56
RAM56
Row0
RAM0
Row56
RAM0
-
-
Row0
RAM0
-
-
COM57
Row57
RAM57
Row1
RAM1
Row57
RAM1
-
-
Row1
RAM1
-
-
COM58
Row58
RAM58
Row2
RAM2
Row58
RAM2
-
-
Row2
RAM2
-
-
COM59
Row59
RAM59
Row3
RAM3
Row59
RAM3
-
-
Row3
RAM3
-
-
COM60
Row60
RAM60
Row4
RAM4
Row60
RAM4
-
-
Row4
RAM4
-
-
COM61
Row61
RAM61
Row5
RAM5
Row61
RAM5
-
-
Row5
RAM5
-
-
COM62
Row62
RAM62
Row6
RAM6
Row62
RAM6
-
-
Row6
RAM6
-
-
COM63
Row63
RAM63
Row7
RAM7
Row63
RAM7
-
-
Row7
RAM7
-
-
0
8
0
0
0
8
56
56
56
Normal
Normal
Normal
64
Normal
0
8
Output
Hardware
pin name
0
0
Normal
64
64
Normal
8
0
Solomon Systech
May 2005
P 30/56 Rev 1.7
SSD1303
Set MUX ratio(A8)
COM Normal / Remapped (C0 / C8)
Display offset (D3)
Display start line (40 - 7F)
COM0
Row63
RAM63
Row7
RAM7
Row63
RAM7
Row47
RAM47
-
-
Row47
RAM41
-
-
COM1
Row62
RAM62
Row6
RAM6
Row62
RAM6
Row46
RAM46
-
-
Row46
RAM40
-
-
COM2
Row61
RAM61
Row5
RAM5
Row61
RAM5
Row45
RAM45
-
-
Row45
RAM41
-
-
COM3
Row60
RAM60
Row4
RAM4
Row60
RAM4
Row44
RAM44
-
-
Row44
RAM42
-
-
COM4
Row59
RAM59
Row3
RAM3
Row59
RAM3
Row43
RAM43
-
-
Row43
RAM43
-
-
COM5
Row58
RAM58
Row2
RAM2
Row58
RAM2
Row42
RAM42
-
-
Row42
RAM44
-
-
COM6
Row57
RAM57
Row1
RAM1
Row57
RAM1
Row41
RAM41
-
-
Row41
RAM45
-
-
COM7
Row56
RAM56
Row0
RAM0
Row56
RAM0
Row40
RAM40
-
-
Row40
RAM46
-
-
COM8
Row55
RAM55
Row63
RAM63
Row55
RAM63
Row39
RAM39
Row47
RAM47
Row39
RAM47
Row47
RAM63
COM9
Row54
RAM54
Row62
RAM62
Row54
RAM62
Row38
RAM38
Row46
RAM46
Row38
RAM46
Row46
RAM62
COM10
Row53
RAM53
Row61
RAM61
Row53
RAM61
Row37
RAM37
Row45
RAM45
Row37
RAM45
Row45
RAM61
COM11
Row52
RAM52
Row60
RAM60
Row52
RAM60
Row36
RAM36
Row44
RAM44
Row36
RAM44
Row44
RAM60
COM12
Row51
RAM51
Row59
RAM59
Row51
RAM59
Row35
RAM35
Row43
RAM43
Row35
RAM43
Row43
RAM59
COM13
Row50
RAM50
Row58
RAM58
Row50
RAM58
Row34
RAM34
Row42
RAM42
Row34
RAM42
Row42
RAM58
COM14
Row49
RAM49
Row57
RAM57
Row49
RAM57
Row33
RAM33
Row41
RAM41
Row33
RAM41
Row41
RAM57
COM15
Row48
RAM48
Row56
RAM56
Row48
RAM56
Row32
RAM32
Row40
RAM40
Row32
RAM40
Row40
RAM56
COM16
Row47
RAM47
Row55
RAM55
Row47
RAM55
Row31
RAM31
Row39
RAM39
Row31
RAM39
Row39
RAM55
COM17
Row46
RAM46
Row54
RAM54
Row46
RAM54
Row30
RAM30
Row38
RAM38
Row30
RAM38
Row38
RAM54
COM18
Row45
RAM45
Row53
RAM53
Row45
RAM53
Row29
RAM29
Row37
RAM37
Row29
RAM37
Row37
RAM53
COM19
Row44
RAM44
Row52
RAM52
Row44
RAM52
Row28
RAM28
Row36
RAM36
Row28
RAM36
Row36
RAM52
COM20
Row43
RAM43
Row51
RAM51
Row43
RAM51
Row27
RAM27
Row35
RAM35
Row27
RAM35
Row35
RAM51
COM21
Row42
RAM42
Row50
RAM50
Row42
RAM50
Row26
RAM26
Row34
RAM34
Row26
RAM34
Row34
RAM50
COM22
Row41
RAM41
Row49
RAM49
Row41
RAM49
Row25
RAM25
Row33
RAM33
Row25
RAM33
Row33
RAM49
COM23
Row40
RAM40
Row48
RAM48
Row40
RAM48
Row24
RAM24
Row32
RAM32
Row24
RAM32
Row32
RAM48
COM24
Row39
RAM39
Row47
RAM47
Row39
RAM47
Row23
RAM23
Row31
RAM31
Row23
RAM31
Row31
RAM47
COM25
Row38
RAM38
Row46
RAM46
Row38
RAM46
Row22
RAM22
Row30
RAM30
Row22
RAM30
Row30
RAM46
COM26
Row37
RAM37
Row45
RAM45
Row37
RAM45
Row21
RAM21
Row29
RAM29
Row21
RAM29
Row29
RAM45
COM27
Row36
RAM36
Row44
RAM44
Row36
RAM44
Row20
RAM20
Row28
RAM28
Row20
RAM28
Row28
RAM44
COM28
Row35
RAM35
Row43
RAM43
Row35
RAM43
Row19
RAM19
Row27
RAM27
Row19
RAM27
Row27
RAM43
COM29
Row34
RAM34
Row42
RAM42
Row34
RAM42
Row18
RAM18
Row26
RAM26
Row18
RAM26
Row26
RAM42
COM30
Row33
RAM33
Row41
RAM41
Row33
RAM41
Row17
RAM17
Row25
RAM25
Row17
RAM25
Row25
RAM41
COM31
Row32
RAM32
Row40
RAM40
Row32
RAM40
Row16
RAM16
Row24
RAM24
Row16
RAM24
Row24
RAM40
COM32
Row31
RAM31
Row39
RAM39
Row31
RAM39
Row15
RAM15
Row23
RAM23
Row15
RAM23
Row23
RAM39
COM33
Row30
RAM30
Row38
RAM38
Row30
RAM38
Row14
RAM14
Row22
RAM22
Row14
RAM22
Row22
RAM38
COM34
Row29
RAM29
Row37
RAM37
Row29
RAM37
Row13
RAM13
Row21
RAM21
Row13
RAM21
Row21
RAM37
COM35
Row28
RAM28
Row36
RAM36
Row28
RAM36
Row12
RAM12
Row20
RAM20
Row12
RAM20
Row20
RAM36
COM36
Row27
RAM27
Row35
RAM35
Row27
RAM35
Row11
RAM11
Row19
RAM19
Row11
RAM19
Row19
RAM35
COM37
Row26
RAM26
Row34
RAM34
Row26
RAM34
Row10
RAM10
Row18
RAM18
Row10
RAM18
Row18
RAM34
COM38
Row25
RAM25
Row33
RAM33
Row25
RAM33
Row9
RAM9
Row17
RAM17
Row9
RAM17
Row17
RAM33
COM39
Row24
RAM24
Row32
RAM32
Row24
RAM32
Row8
RAM8
Row16
RAM16
Row8
RAM16
Row16
RAM32
COM40
Row23
RAM23
Row31
RAM31
Row23
RAM31
Row7
RAM7
Row15
RAM15
Row7
RAM15
Row15
RAM31
COM41
Row22
RAM22
Row30
RAM30
Row22
RAM30
Row6
RAM6
Row14
RAM14
Row6
RAM14
Row14
RAM30
COM42
Row21
RAM21
Row29
RAM29
Row21
RAM29
Row5
RAM5
Row13
RAM13
Row5
RAM13
Row13
RAM29
COM43
Row20
RAM20
Row28
RAM28
Row20
RAM28
Row4
RAM4
Row12
RAM12
Row4
RAM12
Row12
RAM28
COM44
Row19
RAM19
Row27
RAM27
Row19
RAM27
Row3
RAM3
Row11
RAM11
Row3
RAM11
Row11
RAM27
COM45
Row18
RAM18
Row26
RAM26
Row18
RAM26
Row2
RAM2
Row10
RAM10
Row2
RAM10
Row10
RAM26
COM46
Row17
RAM17
Row25
RAM25
Row17
RAM25
Row1
RAM1
Row9
RAM9
Row1
RAM9
Row9
RAM25
COM47
Row16
RAM16
Row24
RAM24
Row16
RAM24
Row0
RAM0
Row8
RAM8
Row0
RAM8
Row8
RAM24
COM48
Row15
RAM15
Row23
RAM23
Row15
RAM23
-
-
Row7
RAM7
-
-
Row7
RAM23
COM49
Row14
RAM14
Row22
RAM22
Row14
RAM22
-
-
Row6
RAM6
-
-
Row6
RAM22
COM50
Row13
RAM13
Row21
RAM21
Row13
RAM21
-
-
Row5
RAM5
-
-
Row5
RAM21
COM51
Row12
RAM12
Row20
RAM20
Row12
RAM20
-
-
Row4
RAM4
-
-
Row4
RAM20
COM52
Row11
RAM11
Row19
RAM19
Row11
RAM19
-
-
Row3
RAM3
-
-
Row3
RAM19
COM53
Row10
RAM10
Row18
RAM18
Row10
RAM18
-
-
Row2
RAM2
-
-
Row2
RAM18
COM54
Row9
RAM9
Row17
RAM17
Row9
RAM17
-
-
Row1
RAM1
-
-
Row1
RAM17
COM55
Row8
RAM8
Row16
RAM16
Row8
RAM16
-
-
Row0
RAM0
-
-
Row0
RAM16
COM56
Row7
RAM7
Row15
RAM15
Row7
RAM15
-
-
-
-
-
-
-
-
COM57
Row6
RAM6
Row14
RAM14
Row6
RAM14
-
-
-
-
-
-
-
-
COM58
Row5
RAM5
Row13
RAM13
Row5
RAM13
-
-
-
-
-
-
-
-
COM59
Row4
RAM4
Row12
RAM12
Row4
RAM12
-
-
-
-
-
-
-
-
COM60
Row3
RAM3
Row11
RAM11
Row3
RAM11
-
-
-
-
-
-
-
-
COM61
Row2
RAM2
Row10
RAM10
Row2
RAM10
-
-
-
-
-
-
-
-
COM62
Row1
RAM1
Row9
RAM9
Row1
RAM9
-
-
-
-
-
-
-
-
COM63
Row0
RAM0
Row8
RAM8
Row0
RAM8
-
-
-
-
-
-
-
-
48
Remap
8
16
8
0
0
8
48
48
Remap
Remap
48
Remap
0
0
0
0
0
8
Hardware
pin name
Output
64
64
64
Remap
Remap
Remap
0
8
Set Display Clock Divide Ratio/ Oscillator Frequency
This command is used to set the frequency of the internal display clocks, DCLKs. It is defined as the divide
ratio (Value from 1 to 16) used to divide the oscillator frequency. POR is 1. Frame frequency is determined
by divide ratio, number of display clocks per row, MUX ratio and oscillator frequency.
Set Area Colour Mode ON/OFF
This command is used to enable area colour mode. POR is mono mode.
SSD1303
Rev 1.7
P 31/56 May 2005
Solomon Systech
Set Low Power Display Mode
This is a double byte command. This command is set to reduce power consumption during IC operation.
Set Pre-charge period
This command is used to set the duration of the pre-charge period. The interval is counted in number of
DCLK. POR is 2 DCLK.
Set COM pins hardware configuration
This command is to set the COM signals pin configuration (sequential or alternative) to match the OLED
panel hardware layout
Sequential COM pin configuration:
COM31, 30, 29...0
SEG0, 1, 2... 131
COM32, 33, 34...63
Alternative COM pin configuration (POR):
COM62, 60, 58...0
SEG0, 1, 2... 131
COM1, 3, 5...63
Set VCOM deselect level
This command is to set the COM pin output voltage level at deselect stage.
NOP
No Operation Command
Status register Read
This command is issued by setting D/C# LOW during a data read (refer to Figure 10 and Figure 11 for
parallel interface waveform). It allows the MCU to monitor the internal status of the chip. No status read is
provided for serial mode.
Solomon Systech
May 2005
P 32/56 Rev 1.7
SSD1303
10 MAXIMUM RATINGS
Table 7 - Maximum Ratings
(Voltage Reference to V
SS
)
Symbol Parameter
Value Unit
V
DD
-0.3 to +4.0
V
V
CC
0.0 to 18.0
V
V
REF
Supply Voltage
0.0 to 18.0
V
V
COMH
Supply Voltage/Output voltage
0.0 to 18.0
V
-
SEG/COM output voltage
0.0 to 18.0
V
V
in
Input voltage
Vss-0.3 to Vdd+0.3
V
T
A
Operating Temperature
-40 to +90
C
T
stg
Storage Temperature Range
-65 to +150
C
Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the
limits in the Electrical Characteristics tables or Pin Description.
SSD1303
Rev 1.7
P 33/56 May 2005
Solomon Systech
11 DC CHARACTERISTICS
Table 8 - DC Characteristics
(Unless otherwise specified, Voltage Referenced to V
SS
, V
DD
= 2.4 to 3.5V, T
A
= 25
C)
Symbol Parameter
Test
Condition
Min
Typ
Max
Unit
V
CC
Operating
Voltage
-
7
12
16
V
V
DD
Logic Supply Voltage
-
2.4
-
3.5
V
V
DD
Logic Supply Voltage (internal
DC/DC enable)
-
3.0 - 3.5
V
V
OH
High Logic Output Level
IOUT = 100uA, 3.3MHz
0.9*V
DD
- V
DD
V
V
OL
Low Logic Output Level
IOUT = 100uA, 3.3MHz
0
-
0.1*V
DD
V
V
IH
High Logic Input Level
IOUT = 100uA, 3.3MHz
0.8*V
DD
- V
DD
V
V
IL
Low Logic Input Level
IOUT = 100uA, 3.3MHz
0
-
0.2*V
DD
V
I
CC, SLEEP
Sleep mode Current
VDD=2.7V, display
OFF, No panel attached
-10 - +10
uA
I
DD, SLEEP
Sleep mode Current
VDD=2.7V, display
OFF, No panel attached
-10 - +10
uA
I
CC
V
CC
Supply Current
V
DD
= 2.7V, V
CC
= 12V, I
REF
= 10uA
No loading, Display ON, All ON
Contrast = FF
-
550
-
uA
I
DD
V
DD
Supply Current
V
DD
= 2.7V, V
CC
= 12V, I
REF
= 10uA
No loading, Display ON, All ON
Contrast = FF
-
190
-
uA
Contrast=FF 285
320
355
Contrast=AF -
220
-
Contrast=5F -
120
-
I
SEG
Segment Output Current
VDD=2.7V, VCC=12V,
IREF=10uA, Display ON, Segment
pin under test is connected with a
20K resistive load to VSS
Contrast=0F -
20
-
uA
Dev
Segment output current uniformity
Dev = (I
SEG
I
MID
)/I
MID
I
MID
= (I
MAX
+ I
MIN
)/2
I
SEG
[0:131] = Segment
current at contrast = FF
-
-
3
%
Adj. Dev
Adjacent pin output current
uniformity (contrast = FF)
Adj Dev = (I[n]-I[n+1]) /
(I[n]+I[n+1])
-
2.0
- %
VDD input=3V, L=22uH;
R1=450Kohm;
R2=50Kohm;
Icc = 20mA(loading)
11.0 12.0 13.0
Vcc
DC-DC converter output voltage
-
7 - 16
V
Pwr
DC-DC converter output power
VDD input=3V, L=22uH;
Vcc = 12V
-
-
400
mW
Solomon Systech
May 2005
P 34/56 Rev 1.7
SSD1303
12 AC CHARACTERISTICS
Table 9 - AC Characteristics
(Unless otherwise specified, Voltage Referenced to V
SS
, V
DD
= 2.4 to 3.5V, T
A
= 25C.)
Symbol
Parameter Test
Condition
Min
Typ
Max
Unit
F
OSC
Oscillation Frequency of
Display Timing
Generator
Vdd = 2.7V
315 360
420
kHz
F
FRM
Frame Frequency for 64
MUX Mode
132x64 Graphic Display Mode,
Display ON, Internal Oscillator
Enabled
-
F
OSC
X
1/(D*K*64)
-
Hz
Reset low pulse width
-
3
us
RES#
Reset complete time
-
2
us
D: divide ratio (default value = 1)
K: number of display clocks (default value = 54)
Refer to command table (set display clock divide ratio/oscillator freq) for detail description
SSD1303
Rev 1.7
P 35/56 May 2005
Solomon Systech
Table 10 - 6800-Series MPU Parallel Interface Timing Characteristics
(V
DD
- V
SS
= 2.4 to 3.5V, T
A
= 25C)
Symbol
Parameter
Min Typ Max Unit
t
cycle
Clock
Cycle
Time
300 - - ns
t
AS
Address
Setup
Time
0 - - ns
t
AH
Address
Hold
Time
0 - - ns
t
DSW
Write Data Setup Time
40
-
-
ns
t
DHW
Write Data Hold Time
7
-
-
ns
t
DHR
Read Data Hold Time
20
-
-
ns
t
OH
Output
Disable
Time
- - 70 ns
t
ACC
Access
Time
- - 140 ns
PW
CSL
Chip Select Low Pulse Width (read)
Chip Select Low Pulse Width (write)
120
60
- - ns
PW
CSH
Chip Select High Pulse Width (read)
Chip Select High Pulse Width (write)
60
60
- - ns
t
R
Rise
Time
- - 15 ns
t
F
Fall
Time
- - 15 ns
Figure 10 - 6800-series MPU parallel interface characteristics
D
0
~D
7
(WRITE)
D
0
~D
7
(READ)
E
CS#
R/W
PW
CSL
t
R
t
F
t
DHW
t
OH
t
ACC
t
DHR
Valid Data
t
DSW
Valid Data
t
cycle
PW
CSH
t
AH
t
AS
D/C
Solomon Systech
May 2005
P 36/56 Rev 1.7
SSD1303
Table 11 - 8080-Series MPU Parallel Interface Timing Characteristics
(V
DD
- V
SS
= 2.4 to 3.5V, T
A
= 25C)
Symbol
Parameter
Min Typ Max Unit
t
cycle
Clock
Cycle
Time
300
- - ns
t
AS
Address
Setup
Time
0
-
-
ns
t
AH
Address
Hold
Time
0
-
-
ns
t
DSW
Write Data Setup Time
40
-
-
ns
t
DHW
Write Data Hold Time
7
-
-
ns
t
DHR
Read Data Hold Time
20
-
-
ns
t
OH
Output
Disable
Time
-
-
70
ns
t
ACC
Access
Time
-
-
140
ns
PW
CSL
Chip Select Low Pulse Width (read)
Chip Select Low Pulse Width (write)
120
60
- - ns
PW
CSH
Chip Select High Pulse Width (read)
Chip Select High Pulse Width (write)
60
60
- - ns
t
R
Rise
Time
- - 15 ns
t
F
Fall
Time
- - 15 ns
Figure 11 - 8080-series MPU parallel interface characteristics
t
t
DHR
t
ACC
Valid Data
Valid Data
t
DSW
t
DHW
t
R
t
F
PW
CSL
PW
CSH
t
cycle
t
AH
t
AS
D
0
-D
7
(Read data from driver)
D
0
-D
7
(Write data to driver)
WR#
RD#
CS#
D/C
SSD1303
Rev 1.7
P 37/56 May 2005
Solomon Systech
Table 12 - Serial Interface Timing Characteristics
(V
DD
- V
SS
= 2.4 to 3.5V, T
A
= 25C)
Symbol
Parameter
Min Typ Max Unit
t
cycle
Clock Cycle Time
250
- - ns
t
AS
Address Setup Time
150 - - ns
t
AH
Address Hold Time
150 - - ns
t
CSS
Chip Select Setup Time
120 - - ns
t
CSH
Chip Select Hold Time
60 - - ns
t
DSW
Write Data Setup Time
100 - - ns
t
DHW
Write Data Hold Time
100 - - ns
t
CLKL
Clock Low Time
100 - - ns
t
CLKH
Clock High Time
100 - - ns
t
R
Rise Time
- - 15 ns
t
F
Fall Time
- - 15 ns
Figure 12 - Serial interface characteristics
t
AH
t
AS
D/C
Valid Data
t
DHW
t
CLKL
t
DSW
t
CLKH
t
cycle
t
CSS
t
CSH
t
F
t
R
SDIN(D
1
)
CS#
SCLK(D
0
)
D7
SDIN(D
1
)
CS#
SCLK(D
0
)
D6
D5
D4
D3
D2
D1
D0
Solomon Systech
May 2005
P 38/56 Rev 1.7
SSD1303
The configuration for 6800-parallel interface mode, externally V
CC
is shown in the following diagram:
(V
DD
=2.7V, V
CC
=V
REF
=12V, I
REF
=10uA)
Pin connected to MCU interface: D0~D7, E, R/W#, D/C#, CS#, RES#
Pin externally connected to VSS: BS0, VSSB
Pin internally connected to VCC: VREF
GDR, RESE, VB
REF
, FB should be left open individually;
C
1
~ C
3
: 4.7uF
R1: 910k
, R
1
=(Voltage at IREF pin-VSS)/I
REF
Voltage at IREF pin = VCC-3V
13 APPLICATION EXAMPLE
Figure 13 - Application Example (Block Diagram of SSD1303T3)
DISPLAY PANEL SIZE
96 x 64
COM
62
COM
60
.
.
COM
2
COM
0
SEG
0
.
.
.
.
.
.
.
.
.
.
.
.
SEG
9
5
COM
1
COM
3
.
.
COM
61
COM
63
SSD1303T3
V
CC
V
COMH
I
REF
D
7
~D
0
E (RD#) R/W# (W/R#) D/C# RES# CS# BS
1
BS
2
V
DD
VDDB GDR RESE FB VB
REF
V
SS
R
1
D
0
~D
7
E (RD#) R/W# (W/R#) D/C# RES# CS# BS
1
BS
2
V
DD
V
SS
C
1
C
2
V
SS
[GND]
C
3
Vcc
SSD1303
Rev 1.7
P 39/56 May 2005
Solomon Systech
14 SSD1303T3R1 PACKAGE DETAILS
SSD1303T3R1 Pin Assignment
Figure 14 - SSD1303T3R1 pin assignment (Copper view, Normal TAB design)
Remark:
Use internal clock
VREF is connected to VCC
Support MCU interface: 8-bit 6800/8080 parallel interface and SPI
VSSB, BGGND are connected to VSS
BS0 is connected to VSS
Solomon Systech
May 2005
P 40/56 Rev 1.7
SSD1303
Table 13 - SSD1303T3R1 pin assignment
Pin no.
Pin name
Pin no.
Pin name
Pin no.
Pin name
Pin no.
Pin name
1
NC
61
COM8
121
SEG47
181
COM7
2
VSS
62
COM6
122
SEG48
182
COM9
3
GDR
63
COM4
123
SEG49
183
COM11
4
VDDB
64
COM2
124
SEG50
184
COM13
5
FB
65
COM0
125
SEG51
185
COM15
6
RESE
66
NC
126
SEG52
186
COM17
7
VBREF
67
NC
127
SEG53
187
COM19
8
GP0
68
NC
128
SEG54
188
COM21
9
GP1
69
NC
129
SEG55
189
COM23
10
NC
70
NC
130
SEG56
190
COM25
11
VDD1
71
NC
131
SEG57
191
COM27
12
BS1
72
NC
132
SEG58
192
COM29
13
BS2
73
NC
133
SEG59
193
COM31
14
NC
74
SEG0
134
SEG60
194
COM33
15
CS#
75
SEG1
135
SEG61
195
COM35
16
RES#
76
SEG2
136
SEG62
196
COM37
17
D/C
77
SEG3
137
SEG63
197
COM39
18
R/W
78
SEG4
138
SEG64
198
COM41
19
E/RD
79
SEG5
139
SEG65
199
COM43
20
D0
80
SEG6
140
SEG66
200
COM45
21
D1
81
SEG7
141
SEG67
201
COM47
22
D2
82
SEG8
142
SEG68
202
COM49
23
D3
83
SEG9
143
SEG69
203
COM51
24
D4
84
SEG10
144
SEG70
204
COM53
25
D5
85
SEG11
145
SEG71
205
COM55
26
D6
86
SEG12
146
SEG72
206
COM57
27
D7
87
SEG13
147
SEG73
207
COM59
28
IREF
88
SEG14
148
SEG74
208
COM61
29
VCOMH
89
SEG15
149
SEG75
209
COM63
30
VCC
90
SEG16
150
SEG76
210
NC
31
NC
91
SEG17
151
SEG77
211
NC
32
NC
92
SEG18
152
SEG78
33
NC
93
SEG19
153
SEG79
34
COM62
94
SEG20
154
SEG80
35
COM60
95
SEG21
155
SEG81
36
COM58
96
SEG22
156
SEG82
37
COM56
97
SEG23
157
SEG83
38
COM54
98
SEG24
158
SEG84
39
COM52
99
SEG25
159
SEG85
40
COM50
100
SEG26
160
SEG86
41
COM48
101
SEG27
161
SEG87
42
COM46
102
SEG28
162
SEG88
43
COM44
103
SEG29
163
SEG89
44
COM42
104
SEG30
164
SEG90
45
COM40
105
SEG31
165
SEG91
46
COM38
106
SEG32
166
SEG92
47
COM36
107
SEG33
167
SEG93
48
COM34
108
SEG34
168
SEG94
49
COM32
109
SEG35
169
SEG95
50
COM30
110
SEG36
170
NC
51
COM28
111
SEG37
171
NC
52
COM26
112
SEG38
172
NC
53
COM24
113
SEG39
173
NC
54
COM22
114
SEG40
174
NC
55
COM20
115
SEG41
175
NC
56
COM18
116
SEG42
176
NC
57
COM16
117
SEG43
177
NC
58
COM14
118
SEG44
178
COM1
59
COM12
119
SEG45
179
COM3
60
COM10
120
SEG46
180
COM5
SSD1303
Rev 1.7
P 41/56 May 2005
Solomon Systech
SSD1303T3R1 TAB PACKAGE DIMENSIONS
SS
D1
303
T3
SO
LOM
O
N
Solomon Systech
May 2005
P 42/56 Rev 1.7
SSD1303
SSD1303
Rev 1.7
P 43/56 May 2005
Solomon Systech
15 SSD1303T6R1 PACKAGE DETAILS
SSD1303T6R1 Pin Assignment
Figure 15 - SSD1303T6R1 pin assignment (Copper view)
Remark:
Use internal clock
VREF is connected to VCC
Support MCU interface: 8-bit 6800/8080 parallel interface and SPI
VSSB, BGGND are connected to VSS
BS0 is connected to VSS
Solomon Systech
May 2005
P 44/56 Rev 1.7
SSD1303
Table 14 - SSD1303T6R1 pin assignment
Pin no.
Pin name
Pin no.
Pin name
Pin no.
Pin name
Pin no.
Pin name
Pin no.
Pin name
1
NC
61
COM9
121
SEG83
181
SEG23
241
COM50
2
VCC
62
COM7
122
SEG82
182
SEG22
242
COM52
3
VCOMH
63
COM5
123
SEG81
183
SEG21
243
COM54
4
IREF
64
COM3
124
SEG80
184
SEG20
244
COM56
5
D7
65
COM1
125
SEG79
185
SEG19
245
COM58
6
D6
66
NC
126
SEG78
186
SEG18
246
COM60
7
D5
67
NC
127
SEG77
187
SEG17
247
COM62
8
D4
68
NC
128
SEG76
188
SEG16
248
NC
9
D3
69
NC
129
SEG75
189
SEG15
249
NC
10
D2
70
NC
130
SEG74
190
SEG14
11
D1
71
NC
131
SEG73
191
SEG13
12
D0
72
NC
132
SEG72
192
SEG12
13
E/RD
73
SEG131
133
SEG71
193
SEG11
14
R/W
74
SEG130
134
SEG70
194
SEG10
15
D/C
75
SEG129
135
SEG69
195
SEG9
16
RES#
76
SEG128
136
SEG68
196
SEG8
17
CS#
77
SEG127
137
SEG67
197
SEG7
18
NC
78
SEG126
138
SEG66
198
SEG6
19
BS2
79
SEG125
139
SEG65
199
SEG5
20
BS1
80
SEG124
140
SEG64
200
SEG4
21
VDD
81
SEG123
141
SEG63
201
SEG3
22
NC
82
SEG122
142
SEG62
202
SEG2
23
NC
83
SEG121
143
SEG61
203
SEG1
24
NC
84
SEG120
144
SEG60
204
SEG0
25
VBREF
85
SEG119
145
SEG59
205
NC
26
RESE
86
SEG118
146
SEG58
206
NC
27
FB
87
SEG117
147
SEG57
207
NC
28
VDDB
88
SEG116
148
SEG56
208
NC
29
GDR
89
SEG115
149
SEG55
209
NC
30
VSS
90
SEG114
150
SEG54
210
NC
31
NC
91
SEG113
151
SEG53
211
NC
32
NC
92
SEG112
152
SEG52
212
NC
33
NC
93
SEG111
153
SEG51
213
NC
34
COM63
94
SEG110
154
SEG50
214
NC
35
COM61
95
SEG109
155
SEG49
215
NC
36
COM59
96
SEG108
156
SEG48
216
COM0
37
COM57
97
SEG107
157
SEG47
217
COM2
38
COM55
98
SEG106
158
SEG46
218
COM4
39
COM53
99
SEG105
159
SEG45
219
COM6
40
COM51
100
SEG104
160
SEG44
220
COM8
41
COM49
101
SEG103
161
SEG43
221
COM10
42
COM47
102
SEG102
162
SEG42
222
COM12
43
COM45
103
SEG101
163
SEG41
223
COM14
44
COM43
104
SEG100
164
SEG40
224
COM16
45
COM41
105
SEG99
165
SEG39
225
COM18
46
COM39
106
SEG98
166
SEG38
226
COM20
47
COM37
107
SEG97
167
SEG37
227
COM22
48
COM35
108
SEG96
168
SEG36
228
COM24
49
COM33
109
SEG95
169
SEG35
229
COM26
50
COM31
110
SEG94
170
SEG34
230
COM28
51
COM29
111
SEG93
171
SEG33
231
COM30
52
COM27
112
SEG92
172
SEG32
232
COM32
53
COM25
113
SEG91
173
SEG31
233
COM34
54
COM23
114
SEG90
174
SEG30
234
COM36
55
COM21
115
SEG89
175
SEG29
235
COM38
56
COM19
116
SEG88
176
SEG28
236
COM40
57
COM17
117
SEG87
177
SEG27
237
COM42
58
COM15
118
SEG86
178
SEG26
238
COM44
59
COM13
119
SEG85
179
SEG25
239
COM46
60
COM11
120
SEG84
180
SEG24
240
COM48
SSD1303
Rev 1.7
P 45/56 May 2005
Solomon Systech
SSD1303T6R1 TAB Package Dimensions
SS
D1
30
3T
6
Solomon Systech
May 2005
P 46/56 Rev 1.7
SSD1303
SSD1303
Rev 1.7
P 47/56 May 2005
Solomon Systech
16 SSD1303T8R1 PACKAGE DETAILS
SSD1303T8R1 Pin Assignment
Remark:
Use internal clock
VREF is connected to VCC
Support MCU interface: 8-bit 6800/8080 parallel interface and SPI
VSSB, BGGND are connected to VSS
BS0 is connected to VSS
Solomon Systech
May 2005
P 48/56 Rev 1.7
SSD1303
Table 15 - SSD1303T8R1 pin assignment
Pin no.
Pin name
Pin no.
Pin name
Pin no.
Pin name
Pin no.
Pin name
1
NC
61
COM8
121
SEG47
181
COM7
2
VSS
62
COM6
122
SEG48
182
COM9
3
GDR
63
COM4
123
SEG49
183
COM11
4
VDDB
64
COM2
124
SEG50
184
COM13
5
FB
65
COM0
125
SEG51
185
COM15
6
RESE
66
NC
126
SEG52
186
COM17
7
VBREF
67
NC
127
SEG53
187
COM19
8
GP0
68
NC
128
SEG54
188
COM21
9
GP1
69
NC
129
SEG55
189
COM23
10
NC
70
NC
130
SEG56
190
COM25
11
VDD1
71
NC
131
SEG57
191
COM27
12
BS1
72
NC
132
SEG58
192
COM29
13
BS2
73
NC
133
SEG59
193
COM31
14
NC
74
SEG0
134
SEG60
194
COM33
15
CS#
75
SEG1
135
SEG61
195
COM35
16
RES#
76
SEG2
136
SEG62
196
COM37
17
D/C
77
SEG3
137
SEG63
197
COM39
18
R/W
78
SEG4
138
SEG64
198
COM41
19
E/RD
79
SEG5
139
SEG65
199
COM43
20
D0
80
SEG6
140
SEG66
200
COM45
21
D1
81
SEG7
141
SEG67
201
COM47
22
D2
82
SEG8
142
SEG68
202
COM49
23
D3
83
SEG9
143
SEG69
203
COM51
24
D4
84
SEG10
144
SEG70
204
COM53
25
D5
85
SEG11
145
SEG71
205
COM55
26
D6
86
SEG12
146
SEG72
206
COM57
27
D7
87
SEG13
147
SEG73
207
COM59
28
IREF
88
SEG14
148
SEG74
208
COM61
29
VCOMH
89
SEG15
149
SEG75
209
COM63
30
VCC
90
SEG16
150
SEG76
210
NC
31
NC
91
SEG17
151
SEG77
211
NC
32
NC
92
SEG18
152
SEG78
33
NC
93
SEG19
153
SEG79
34
COM62
94
SEG20
154
SEG80
35
COM60
95
SEG21
155
SEG81
36
COM58
96
SEG22
156
SEG82
37
COM56
97
SEG23
157
SEG83
38
COM54
98
SEG24
158
SEG84
39
COM52
99
SEG25
159
SEG85
40
COM50
100
SEG26
160
SEG86
41
COM48
101
SEG27
161
SEG87
42
COM46
102
SEG28
162
SEG88
43
COM44
103
SEG29
163
SEG89
44
COM42
104
SEG30
164
SEG90
45
COM40
105
SEG31
165
SEG91
46
COM38
106
SEG32
166
SEG92
47
COM36
107
SEG33
167
SEG93
48
COM34
108
SEG34
168
SEG94
49
COM32
109
SEG35
169
SEG95
50
COM30
110
SEG36
170
NC
51
COM28
111
SEG37
171
NC
52
COM26
112
SEG38
172
NC
53
COM24
113
SEG39
173
NC
54
COM22
114
SEG40
174
NC
55
COM20
115
SEG41
175
NC
56
COM18
116
SEG42
176
NC
57
COM16
117
SEG43
177
NC
58
COM14
118
SEG44
178
COM1
59
COM12
119
SEG45
179
COM3
60
COM10
120
SEG46
180
COM5
SSD1303
Rev 1.7
P 49/56 May 2005
Solomon Systech
SSD1303T8R1 TAB Package Dimensions
Solomon Systech
May 2005
P 50/56 Rev 1.7
SSD1303
SSD1303
Rev 1.7
P 51/56 May 2005
Solomon Systech
17 SSD1303T9R1 PACKAGE DETAILS
SSD1303T9R1 Pin Assignment
Figure 16 - SSD1303T9R1 pin assignment (Copper view)
Remark:
Use internal clock
VREF is connected to VCC
Support MCU interface: 8-bit 6800/8080 parallel interface and SPI
VSSB, BGGND are connected to VSS
BS0 is connected to VSS
Solomon Systech
May 2005
P 52/56 Rev 1.7
SSD1303
Table 16 - SSD1303T9R1 pin assignment
Pin
No.
Pin
name
Pin
No.
Pin
name
Pin
No.
Pin
name
Pin
No.
Pin
name
1 NC
61
COM9
121
SEG80
181
COM6
2 VCC
62
COM7
122
SEG79
182
COM8
3 VCOMH
63 COM5
123 SEG78
183 COM10
4 IREF
64 COM3
124
SEG77
184
COM12
5 D7
65
COM1
125
SEG76
185
COM14
6 D6
66 NC
126
SEG75
186
COM16
7 D5
67 NC
127
SEG74
187
COM18
8 D4
68 NC
128
SEG73
188
COM20
9 D3
69 NC
129
SEG72
189
COM22
10 D2
70 NC
130
SEG71
190
COM24
11 D1
71 NC
131
SEG70
191
COM26
12 D0
72 NC
132
SEG69
192
COM28
13 E
73 NC
133
SEG68
193
COM30
14 R/W
74
SEG127
134
SEG67
194
COM32
15 D/C
75
SEG126
135
SEG66
195
COM34
16 RES
76
SEG125
136
SEG65
196
COM36
17 CS#
77
SEG124
137
SEG64
197
COM38
18 NC
78
SEG123
138
SEG63
198
COM40
19 BS2
79
SEG122
139
SEG62
199
COM42
20 BS1
80
SEG121
140
SEG61
200
COM44
21 VDD1
81 SEG120
141
SEG60
201
COM46
22 NC
82
SEG119
142
SEG59
202
COM48
23 GPIO1
83 SEG118
143 SEG58
203 COM50
24 GPIO0
84 SEG117
144 SEG57
204 COM52
25 VBREF
85 SEG116
145 SEG56
205 COM54
26 RESE
86 SEG115 146 SEG55 206 COM56
27 FB
87
SEG114
147
SEG54
207
COM58
28 VDDB 88 SEG113 148 SEG53 208 COM60
29 GDR 89 SEG112
149 SEG52 209 COM62
30 VSS
90
SEG111 150 SEG51 210
NC
31 NC
91
SEG110
151
SEG50
211 NC
32 NC
92
SEG109
152
SEG49
33 NC
93
SEG108
153
SEG48
34 COM63
94 SEG107
154 SEG47
35 COM61
95 SEG106
155 SEG46
36 COM59
96 SEG105
156 SEG45
37 COM57
97 SEG104
157 SEG44
38 COM55
98 SEG103
158 SEG43
39 COM53
99 SEG102
159 SEG42
40 COM51 100 SEG101 160 SEG41
41 COM49 101 SEG100 161 SEG40
42 COM47 102 SEG99 162 SEG39
43 COM45 103 SEG98 163 SEG38
44 COM43 104 SEG97 164 SEG37
45 COM41 105 SEG96 165 SEG36
46 COM39 106 SEG95 166 SEG35
47 COM37 107 SEG94 167 SEG34
48 COM35 108 SEG93 168 SEG33
49 COM33 109 SEG92 169 SEG32
50 COM31 110 SEG91 170 NC
51 COM29 111 SEG90 171 NC
52 COM27 112 SEG89 172 NC
53 COM25 113 SEG88 173 NC
54 COM23 114 SEG87 174 NC
55 COM21 115 SEG86 175 NC
56 COM19 116 SEG85 176 NC
57 COM17 117 SEG84 177 NC
58 COM15 118 SEG83 178 COM0
59 COM13 119 SEG82 179 COM2
60 COM11 120 SEG81 180 COM4
SSD1303
Rev 1.7
P 53/56 May 2005
Solomon Systech
SSD1303T9R1 TAB Package Dimensions
SS
D1
30
3T
9
Solomon Systech
May 2005
P 54/56 Rev 1.7
SSD1303
SSD1303
Rev 1.7
P 55/56 May 2005
Solomon Systech
18 SSD1303Z PACKAGE DETAILS
DIE TRAY DIMENSIONS
Solomon Systech
May 2005
P 56/56 Rev 1.7
SSD1303
http://www.solomon-systech.com
Solomon Systech reserves the right to make changes without further notice to any products herein. Solomon Systech makes no warranty,
representation or guarantee regarding the suitability of its products for any particular purpose, nor does Solomon Systech assume any liability arising
out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or
incidental damages. "Typical" parameters can and do vary in different applications. All operating parameters, including "Typicals" must be validated
for each customer application by customer's technical experts. Solomon Systech does not convey any license under its patent rights nor the rights of
others. Solomon Systech products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the
body, or other applications intended to support or sustain life, or for any other application in which the failure of the Solomon Systech product could
create a situation where personal injury or death may occur. Should Buyer purchase or use Solomon Systech products for any such unintended or
unauthorized application, Buyer shall indemnify and hold Solomon Systech and its offices, employees, subsidiaries, affiliates, and distributors
harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal
injury or death associated with such unintended or unauthorized use, even if such claim alleges that Solomon Systech was negligent regarding the
design or manufacture of the part.
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