The information provided herein is believed to be reliable at press time. Sirenza Microdevices assumes no responsibility for inaccuracies or ommisions.
Sirenza Microdevices assumes no responsibility for the use of this information, and all such information shall be entirely at the user's own risk. Prices and specifications are subject to change without
notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. Sirenza Microdevices does not authorize or warrant any Sirenza Microdevices product
for use in life-support devices and/or systems.
Copyright 2002 Sirenza Microdevices, Inc. All worldwide rights reserved.
303 South Technology Court Broomfield, CO 80021
Phone: (800) SMI-MMIC
http://www.sirenza.com
1
EDS-103585 Rev C
Preliminary
Sirenza Microdevices' SZA-5044 is a high efficiency class
AB Heterojunction Bipolar Transistor (HBT) amplifier
housed in a low-cost surface-mountable plastic package.
This HBT amplifier is made with InGaP on GaAs device
technology and fabricated with MOCVD for an ideal com-
bination of low cost and high reliability.
This product is specifically designed as a final stage for
802.11a equipment in the 4.9 - 5.9 GHz band for a 5V sup-
ply. Optimized on-chip impedance matching circuitry pro-
vides a 50
nominal RF input impedance. A single
external output matching circuit covers the entire 4.9-
5.9GHz band simultaneously. The external output match
allows for load line optimization for other applications or
optimized performance over narrower bands.
Key Specifications
Symbol
Parameters: Test Conditions, App circuit page 4
Z
0
= 50
, V
CC
= 5.0V, Icq = 220mA, T
BP
= 25C
Unit
Min.
Typ.
Max.
f
O
Frequency of Operation
MHz
4900
5900
P
1dB
Output Power at 1dB Compression 5.15 GHz
dBm
28.0
29.5
Output Power at 1dB Compression 5.875 GHz
26.5
28.0
S
21
Gain at 5.15 GHz
dB
27.2
29.2
31.2
Gain at 5.875 GHz
24.4
26.4
28.4
Pout
Output power at 3% EVM 802.11a 54Mb/s - 5.15GHz
dBm
22
Output Power at 3% EVM 802.11a 54Mb/s - 5.875GHz
21
NF
Noise Figure at 5.875 GHz
dB
6.3
IRL
Worst Case Input Return Loss 5.15-5.875GHz
dB
10
15
ORL
Worst Case Output Return Loss 5.15-5.875GHz
7
11
Vdet Range
Output Voltage Range for Pout=10dBm to 26dBm
V
0.8 to 1.9
Icq
Vcc Quiescent Current
mA
185
220
255
I
VPC
Power Up Control Current, Vpc=5V ( I
VPC1
+ I
VPC2
+ I
VPC3
)
mA
1.7
R
th, j-l
Thermal Resistance (junction - lead)
C/W
24
Functional Block Diagram
SZA-5044
4.9 5.9 GHz 5V Power Amplifier
Product Features
Applications
802.11a 54Mb/s Class AB Performance
Pout = 21.5dBm @ 3% EVM, 5V, 310mA
High Gain = 28dB
Output Return Loss < -11dB for Linear Tune
On-chip Output Power Detector
P1dB = 29dBm @ 5V
Simultaneous 4.9- 5.9GHz Performance
Robust - Survives RF Input Power = +15dBm
Power up/down control < 1
s, Vpc 2.9V to 5V
802.11a WLAN, OFDM
5.8GHz ISM Band
Fixed Wireless, UNII, 802.16 WiMAX
Product Description
4mm x 4mm QFN Package
RFIN
RFOUT
Vcc
Pow er Detector
Vout
Activ e
Bias
Activ e
Bias
Activ e
Bias
Pow er
Up/Dow n
Control
303 South Technology Court Broomfield, CO 80021
Phone: (800) SMI-MMIC
http://www.sirenza.com
2
EDS-103585 Rev C
Preliminary
SZA-5044 4.9-5.9 GHz Power Amp
Pin Out Description
Pin #
Function
Description
1,3,5,9,
11,15,17
N/C
Pins are not used. May be grounded, left open, or connected to adjacent pin.
6
VPC1
VPC1 is the bias control pin for the stage 1 active bias circuit and can be run from 2.9V to 5V control. An exter-
nal series resistor is required for proper setting of bias levels depending on control voltage. Refer to the evalu-
ation board schematic for resistor value. To prevent potential damage, do not apply voltage to this pin that is
+1V greater than voltage applied to pin 20 (Vbias) unless Vpc supply current capability is less than 10 mA.
7
VPC2
VPC2 is the bias control pin for the stage 2 active bias circuit and can be run from 2.9V to 5V control. An exter-
nal series resistor is required for proper setting of bias levels depending on control voltage. Refer to the evalu-
ation board schematic for resistor value. To prevent potential damage, do not apply voltage to this pin that is
+1V greater than voltage applied to pin 20 (Vbias) unless Vpc supply current capability is less than 10 mA.
8
VPC3
VPC3 is the bias control pin for the stage 3 active bias circuit and can be run from 2.9V to 5V control. An exter-
nal series resistor is required for proper setting of bias levels depending on control voltage. Refer to the evalu-
ation board schematic for resistor value. To prevent potential damage, do not apply voltage to this pin that is
+1V greater than voltage applied to pin 20 (Vbias) unless Vpc supply current capability is less than 10 mA.
10
Vdet
Ouput power detector voltage. Load with 10K-100K ohms to ground for best performance.
2,4
RFIN
RF input pins. This is DC grounded internal to the IC. Do not apply voltage to this pin. All three pins must be
used for proper operation.
12,13,14
RFOUT
RF output pin. This is also another connection to the 3rd stage collector
16
VC3
3rd stage collector bias pin. Apply 5V to this pin.
18
VC2
2nd stage collector bias pin. Apply 5V to this pin.
19
VC1
1st stage collector bias pin. Apply 5V to this pin.
20
Vbias
Active bias network VCC. Apply 5V to this pin.
EPAD
Gnd
Exposed area on the bottom side of the package needs to be soldered to the ground plane of the board for
optimum thermal and RF performance. Several vias should be located under the EPAD as shown in the rec-
ommended land pattern (page 5).
Caution: ESD Sensitive
Appropriate precaution in handling, packaging
and testing devices must be observed.
Absolute Maximum Ratings
Parameters
Value
Unit
VC3 Collector Bias Current (pin16)
500
mA
VC2 Collector Bias Current (pin18)
225
mA
VC1 Collector Bias Current (pin19)
75
mA
Device Voltage (V
D
)
7.0
V
Power Dissipation
3.4
W
Operating Lead Temperature (T
L
)
-40 to +85
C
RF Input Power for 50 ohm RF out load
15
dBm
RF Input Power for 10:1 VSWR RF out
load
2
dBm
Storage Temperature Range
-40 to +150
C
Operating Junction Temperature (T
J
)
+150
C
ESD Human Body Model
>1000
V
Operation of this device beyond any one of these limits may
cause permanent damage. For reliable continuous operation
the device voltage and current must not exceed the maximum
operating values specified in the table on page one.
Bias conditions should also satisfy the following expression:
I
D
V
D
< (T
J
- T
L
) / R
TH'
j-l
Simplified Device Schematic
Stage 1
Bias
Stage 2
Bias
Stage 3
Bias
Pin 2, 4
Pin 12,13,14
Pin
6
Pin
20
Pin
19
Pin
7
Pin
18
Pin
8
Pin
16
Pin
10
EPAD
EPAD
EPAD
303 South Technology Court Broomfield, CO 80021
Phone: (800) SMI-MMIC
http://www.sirenza.com
5
EDS-103585 Rev C
Preliminary
SZA-5044 4.9-5.9 GHz Power Amp
4.9 - 5.9 GHz Evaluation Board Data (V
BIAS
= 5.0V, I
q
= 220mA)
IM3 vs Pout (2 tone avg), T=25C
Tone Spacing=1MHz
-50
-48
-46
-44
-42
-40
-38
-36
-34
-32
-30
8
10
12
14
16
18
20
22
24
26
Pout(dBm)
IM
3(dB
c)
F=4.9
F=5.15
F=5.35
F=5.725
F=5.875
RF Detector Output (Vdet) vs Pout
F=4.9GHz
0.8
1.0
1.2
1.4
1.6
1.8
2.0
2.2
2.4
2.6
12
14
16
18
20
22
24
26
28
30
Pout(dBm)
V
d
et(V
)
T=-40C
T=25C
T=85C
RF Detector Output (Vdet) vs Pout
F=5.15GHz
0.8
1.0
1.2
1.4
1.6
1.8
2.0
2.2
2.4
2.6
12
14
16
18
20
22
24
26
28
30
Pout(dBm)
V
d
e
t(V
)
T=-40C
T=25C
T=85C
RF Detector Output (Vdet) vs Pout
F=5.35GHz
0.8
1.0
1.2
1.4
1.6
1.8
2.0
2.2
2.4
2.6
12
14
16
18
20
22
24
26
28
30
Pout(dBm)
V
d
et(V
)
T=-40C
T=25C
T=85C
RF Detector Output (Vdet) vs Pout
F=5.725GHz
0.8
1.0
1.2
1.4
1.6
1.8
2.0
2.2
2.4
2.6
12
14
16
18
20
22
24
26
28
30
Pout(dBm)
V
d
et(V
)
T=-40C
T=25C
T=85C
RF Detector Output (Vdet) vs Pout
F=5.875GHz
0.8
1.0
1.2
1.4
1.6
1.8
2.0
2.2
2.4
2.6
12
14
16
18
20
22
24
26
28
30
Pout(dBm)
Vdet(V)
T=-40C
T=25C
T=85C
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