Low Power CMOS SRAM
256K X 8 Bits

UC62LS2008

-20/-25

Features:

· Vcc operation voltage : 3.0V ~ 3.6V
· Low power consumption :

20mA (Max.) operating current
1uA (Typ.) CMOS standby current

· High Speed Access time :

25ns (Max.) at Vcc = 3.0V

· Automatic power down when chip is deselected
· Three state outputs and TTL compatible
· Data retention supply voltage as low as 1.2V
· Easy expansion with CE\ and OE\ options

Description

The UC62LS2008 is a high performance, very low power

CMOS Static Random Access Memory organized as 262,144
words by 8 bits and operates from 3.0V to 3.6V supply
voltage. Advanced CMOS technology and circuit techniques
provide both high speed and low power features with a
typical CMOS standby current of 1uA and maximum access
time of 25ns in 3.0V operation.

Easy memory expansion is provided enable (CE\), and

active LOW output enable (OE\) and three-state output
drivers.

The UC62LS2008 has an automatic power down feature,

reducing the power consumption significantly when chip is
deselected.
The UC62LS2008 is available in the JEDEC standard 32 pin
450mil Plastic SOP, 8mmx20.0mm TSOP (type I), and
8mmx13.4mm STSOP.

PRODUCT FAMILY

Power Consumption

Speed

(ns)

STANDBY Operating

Product Family

Operating

Tempature Vcc Range

Vcc=3.0V(Max.)

Vcc=3.3V(Typ.)

Vcc=3.6V(Max.)

Package

Type

UC62LS2008HC

TSOP-32

UC62LS2008FC

SOP-32

UC62LS2008GC

STSOP-32

UC62LS2008AC

~ 70

3.0V ~ 3.6V

20/25

1uA

20mA

DICE

UC62LS2008HI

TSOP-32

UC62LS2008FI

SOP-32

UC62LS2008GI

STSOP-32

UC62LS2008AI

-40

~ 85

3.0V ~ 3.6V

20/25

1uA

20mA

DICE

PIN CONFIGURATIONS

A14

A12

DQ0

DQ1

DQ2

GND

VCC

A13

A11

A10

DQ7

DQ6

DQ5

DQ4

DQ3

11
12
13
14

UC62LS2008HC

UC62LS2008FI

A15

A17

A16

1
2
3
4
5
6
7
8
9

DQ0

DQ1

DQ2

GND

A14
A12

A7
A6
A5
A4

A16

CE2

VCC

A13

A11

OE
A10

DQ7
DQ6
DQ5
DQ4
DQ3

A15

A17

CE2

UC62LS2008GI

29
28

UC62LS2008FC

UC62LS2008GC

UC62LS2008HI

BLOCK DIAGRAM

MEMORY ARRAY

256K X 8 Bits

RO
W

DECOD

COLUMN DECODER

SENSE AMPLIFIER

WRITE DRIVER

I/O BUFFER

AD
DRESS

I
N

PUT

BU
FFE

CO
N

RO
L

BLOC

CO
N

RO
L

PU
T

BU
FFE

COL

Address

ROW

Address

A0 -

A1
7

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

CE2

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PAGE

Low Power CMOS SRAM
256K X 8 Bits

UC62LS2008

-20/-25

PIN DESCRIPTION

Name Type

Function

A0 A17

Input

Address inputs for selecting one of the 262,144 x 8 bit words in the RAM

CE\,CE2 Input

CE\ is active LOW. CE2 is active HIGH.Chip enable must be active when data read from or write

to the device. If chip enable is not active, the device is deselected and not in a standby power

down mode. The DQ pins will be in high impedance state when the device is deselected.

WE\ Input

The Write enable input is active LOW and controls read and write operations. With the chip

selected, when WE\ is HIGH and OE\ is LOW, output data will be present on the DQ pins, when

WE\ is LOW, the data present on the DQ pins will be written into the selected memory location.

OE\ Input

The output enable input is active LOW. If the output enable is active while the chip is selected

and the write enable is inactive, data will be present on the DQ pins and they will be enabled.

The DQ pins will be in the high impedance state when OE\ is inactive.

DQ0 DQ7

I/O

These 8 bi-directional ports are used to read data from or write data into the RAM.

Vcc Power

Power Supply

Gnd Power

Ground

TRUTH TABLE

Mode

WE\

CE\

CE2

OE\

I/O state

Vcc Current

Not Selected

High Z

SB1

Not

Selected

X X L X

High

SB1

Output Disabled

High Z

Read H L H L

OUT

Write L

ABSOLUTE MAXIMUM RATINGS

(1)

SYMBOL PARAMETER

RATING

UNIT

TERM

Terminal Voltage with
Respect to GND

-0.5 to V

+0.5

BIAS

Temperature Under Bias

-40 to 125

STG

Storage Temperature

-50 to 150

PT Power

Dissipation

0.5

OUT

DC Output Current

1. Stresses greater than those listed under ABSOLUTE

MAXIMUM RATINGS may cause permanent damage to the
device. This is a stress rating only and functional operation of
the device at these or any other conditions above those
indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for
extended periods may affect reliability.

OPERATING RANGE

RANGE

AMBIENT

TEMPERATURE

Commercial

to 70

3.0V ~ 3.6V

CAPACITANCE

(1)

(TA=25

,f=1.0MHz)

SYMBOL

PARAMETER

CONDITIONS MAX. UNIT

CIN

Input

Capacitance

VIN=0V 6 pF

CDQ

Input/Output

Capacitance

VDQ 8

1. This parameter is guaranteed and not 100% tested.

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Low Power CMOS SRAM
256K X 8 Bits

UC62LS2008

-20/-25

DC ELECTRICAL CHARACTERISTICS (TA=0

to 70

)

Symbol Comment

Test Condition

MIN. TYP.

(1)

MAX. UNITS

Guaranteed Input Low
Voltage

(2)

=2.4V

-0.5 - 0.8 V

Guaranteed Input High
Voltage

(2)

=3.6V

2.0 -

Vcc-0.2

Input Leakage Current

=3.6V V

=0V to V

- - 1

Output Leakage Current

=3.6V CE\=V

or OE\=V

=0V t V

- - 1

Output Low Voltage

=3.6V, I

=2mA

- - 0.4

Output High Voltage

=3.0V, I

=-1mA

2.4 - - V

Operating Power Supply
Current

CE\=V

=0mA, F=Fmax

(3)

- - 20

SB1

TTL Standby Current

CE\=V

, V

to V

- - 1

SB2

CMOS Standby Current

CE\

-0.2V, V

-0.2V

to 0.2V

- 1 5

1. Typical characteristics are at TA = 25oC.

2. These are absolute values with respect to device ground and all overshoots due to system or tester notice are included.

3. Fmax = 1/tRC .

DATA RETENTION CHARACTERISTICS ( TA=0

to 70

)

Symbol Comment

Test

Condition

MIN. TYP.

(1)

MAX. UNITS

VCC to Data Retention

CE\

- 0.2V

-0.2V or V

0.2V

1.2 - - V

CCDR

Data Retention Current

CE\

- 0.2V

-0.2V or V

0.2V

- 0.05 0.5 uA

Chip Deselect to Data
Retention Time

0 - - ns

Operation Recovery Time

See Retention Waveform

(2)

- - ns

1. V

= 1.5V, TA = 25

2. t

= Read Cycle Time

LOW VCC DATA RETENTION WAVEFORM

(1)

(CE\ Controlled)

Data Retention Mode

>= 1.2V

CDR

VIH

CE >= V

- 0.2V

Vcc

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Low Power CMOS SRAM
256K X 8 Bits

UC62LS2008

-20/-25

AC TEST CONDITIONS

Input Pulse Levels
Input Rise and Fall Times
Input and Output Timing Reference Level

VCC/0V
1V/ns
0.5VCC

AC TEST LOADS AND WAVEFORMS

3.3V

OUTPUT

126

1404

INCLUDING
JIG AND
SCOPE

FIGURE 1A

3.3V

OUTPUT

1404

5pF

INCLUDING
JIG AND
SCOPE

FIGURE 1B

667

TERMINAL EQUIVALENT

OUTPUT

1.73V

GND

1V/ns

10%

90%

10%

ALL INPUT PULSES

FIGURE 2

KEY TO SWITCHING WAVEFORMS

WAVEFORMS INPUTS OUTPUTS

MUST BE
STEADY

MAY CHANGE
FROM H TO L

WILL BE
CHANGE
FROM H TO L

MAY CHANGE
FROM L TO H

WILL BE
CHANGE
FROM L TO H

DON'T CARE
ANY CHANGE
PERMITTED

CHANGE
STATE
UNKNOWN

DOES NOT
APPLY

CENTER LINE
IS HIGH
IMPEDANCE
OFF STATE

AC ELECTRICAL CHARACTERISTICS (TA=0

to 70

, V

=3.0V~3.6V)

READ CYCLE

UC62LS2008-20 UC62LS2008-25

JEDEC

PARAMETER

NAME

PARAMETER

NAME

DESCRIPTION

Min

Typ

Max Min Typ Max

UNIT

AVAX

Read

Cycle

Time

- - 25 - - Ns

AVQV

Address

Access

Time

- - 20 - - 25

ELQV

Chip

Select

Access

Time

- - 20 - - 25

GLQV

Output Enable to Output Valid

ELQX

CLZ

Chip Select to Output Low Z

GLQX

OLZ

Output Enable to Output Low Z

EHQZ

CHZ

Chip Deselect to Output in High Z

GHQZ

OHZ

Output Disable to Output in High Z

AXOX

Address Chang to Output Change

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Low Power CMOS SRAM
256K X 8 Bits

UC62LS2008

-20/-25

SWITCHING WAVEFORMS (READ CYCLE)

READ CYCLE1

(1,2,4)

ADDRESS

OUT

READ CYCLE2

(1,3,4)

CLZ

(5)

CHZ

(5)

OUT

READ CYCLE3

(1,4)

ADDRESS

CLZ

(5)

CHZ

(5)

OUT

OHZ

(1,5)

OLZ

NOTES:

1. WE\ is high in read cycle.

2. Device is continuously selected when CE\ = VIL

3. Address valid prior to or coincident with CE\ transition low.

4. OE\ = VIL.

5. Transition is measured ±500mV from steady state with CL=5pF as shown in Figure 1B. The

parameter is guaranteed but not 100% tested.

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Low Power CMOS SRAM
256K X 8 Bits

UC62LS2008

-20/-25

AC ELECTRICAL CHARACTERISTICS (TA=0

to 70

, VCC=3.0V~3.6V)

WRITE CYCLE

UC62LS2008-20 UC62LS2008-25

JEDEC

PARAMETER

NAME

PARAMETER

NAME

DESCRIPTION

Min

Typ

Max Min Typ Max

UNIT

AVAX

Write Cycle Time

E1LWH

Chip Select to END of Write

AVWL

Address

Setup

Time

0 - - 0 - - Ns

AVWH

Address valid to End of Write

WLWH

Write Pulse Width

WHAX

Write

Recovery

Time

0 - - 0 - - Ns

WLOZ

WHZ

Write to Output in High Z

DVWH

Data to Write Time Overlap

WHDX

Data Hold Time for Write End

GHOZ

OHZ

Output Disable to Output In High Z

WHQX

End of Write to Output Active

SWITCHING WAVEFORMS (WRITE CYCLE)

WRITECYCLE1

(1)

ADDRESS

OHZ

OUT

(11)

(2)

(4,10)

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Low Power CMOS SRAM
256K X 8 Bits

UC62LS2008

-20/-25

WRITE CYCLE2

(1,6)

ADDRESS

WHZ

OUT

(11)

(2)

(8)

(7)

NOTES:
1. WE\ must be high during address transitions.
2. The internal write time of the memory is defined by the overlap of CE\ and WE\ low. All signals

must be active to initiate a write and any one can terminate a write by going inactive. The data
input setup and hold timing should be referenced to the second transition edge of the signal that
terminates the write.

3. T

is measured from the earlier of CE\ or WE\ going high at the end of write cycle.

4. During this period, DQ pins are in the output state so that the input signals of opposite phase to

the outputs must not be applied.

5. If the CE\ low transition occurs simultaneously with the WE\ low transitions or after the WE\

transition, output remain in a high impedance state.

6. OE\ is continuously low (OE\ = V

7. D

OUT

is the same phase of write data of this write cycle.

8. D

OUT

is the read data of next address.

9. If CE\ is low during this period, DQ pins are in the output state. Then the data input signals of

opposite phase to the outputs must not be applied to them.

10. Transition is measured 500mV from steady state with C

= 5pF as shown in Figure 1B. The

parameter is guaranteed but not 100% tested.

11. TCW is measured from the later of CE\ going low to the end of write.

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Low Power CMOS SRAM
256K X 8 Bits

UC62LS2008

-20/-25

PACKAGE DIMENSIONS

Unit

Symbol

Inch mm

0.0433±0.004 1.10±0.10

0.004±0.002 0.10±0.05

0.039±0.002 1.00±0.05

0.009±0.002 0.22±0.05

0.008±0.001 0.2±0.03

c 0.004~0.008

0.10~0.21

c1 0.004~0.006

0.10~0.16

0.465±0.004 11.8±0.10

0.315±0.004 8.00±0.10

0.020±0.004 0.50±0.10

0.528±0.008 13.40±0.20

0.0197+0.008
-0.004

0.5 +0.2

-0.1

0.0315±0.004 0.80±0.10

0.004 Max

0.1 Max

0" ~ 8"

3 2 - S T S O P

"A "

H D

W IT H P LA T IN G

S E C T IO N A -A

B A S E M E T A L

L 1

1 2

(2 X )

"A " D E T A IL V IE W

S E A T IN G P LA N E

0 .2 5 4

G A U G E P LA N E

1 2

(2X )

1 2

(2 X )

1 2

(2X )

S E A T IN G P L A N E "y"

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Low Power CMOS SRAM
256K X 8 Bits

UC62LS2008

-20/-25

Unit

Symbol

Inch mm

0.0433±0.004 1.10±0.10

0.004±0.002 0.10±0.05

0.039±0.002 1.00±0.05

0.009±0.002 0.22±0.05

0.008±0.001 0.2±0.03

c 0.004~0.008 0.10~0.21

c1 0.004~0.006

0.10~0.16

0.724±0.004

18.40±0.10

0.315±0.004 8.00±0.10

0.020±0.004 0.50±0.10

0.787±0.008 20.00±0.20

L 0.0197+0.008

-0.004

0.5 +0.2
-0.1

0.0315±0.004 0.80±0.10

0.004 Max

0.1 Max

0" ~ 8"

32 - TSOP

"A"

WITH PLATING

SECTION A-A

BASE METAL

(2X)

"A" DETAIL VIEW

SEATING PLANE

0.254

GAUGE PLANE

(2X)

SEATING PLANE "y"

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Low Power CMOS SRAM
256K X 8 Bits

UC62LS2008

-20/-25

Unit

Symbol

Inch mm

0.111±

0.007

2.821±0.176

0.009±0.005 0.229±0.127

0.1055±0.0055

2.680±0.140

0.014 ~ 0.020 0.35

0.50

0.014 ~ 0.018

0.35 ~ 0.46

0.006 ~ 0.012

0.15 ~ 0.32

0.006 ~ 0.011

0.15 ~ 0.28

0.805±0.005

20.447±0.127

0.445±0.005

11.303±0.127

0.555±0.012 14.097±0.305

0.050±0.006

1.270±0.152

0.033±0.010 0.834±0.25

0.055±0.008

1.397±0.203

0.004 Max

0.1 Max

0" ~ 10"

SOP - 32

Seating Plane "y"

"A"

10°

(4X)

DETAIL "A" (2:1)

WITH PLATING

SECTION A-A

BASE METAL

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Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: UC62LS2008

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: UC62LS2008