Low Power CMOS SRAM
256K X 16
UC62LS4096
-20/-25
Features:
Vcc operation voltage : 3.0 V~ 3.6V
Low power consumption :
20mA (Max.) operating current
2uA (Typ.) CMOS standby current
High Speed Access time :
25ns (Max.) at Vcc = 3.0V
Automatic power down when chip is deselected
Three state outputs and TTL compatible
Data retention supply voltage as low as 1.2V
Easy expansion with CE\ and OE\ options
Description
The UC62LS4096 is a high performance, low power
CMOS Static Random Access Memory organized as 262,144
words by 16 and operates from 3.0V to 3.6V supply voltage.
Advanced CMOS technology and circuit techniques provide
both high speed and low power features with a typical CMOS
standby current of 2uA and maximum access time of 25ns in
3.0V operation.
Easy memory expansion is provided enable (CE\), and
active LOW output enable (OE\) and three-state output
drivers.
The UC62LS4096 has an automatic power down feature,
reducing the power consumption significantly when chip is
deselected.
The US62LS4096 is available in the JEDEC standard 44
pin TSOP (Type II) and 48 pin mini-BGA.
PRODUCT FAMILY
Power Consumption
Speed
(ns)
STANDBY Operating
Product Family
Operating
Tempature
Vcc Range
Vcc=3.0V(Max.)
Vcc=3.3V(Typ.)
Vcc=3.6V(Max.)
Package
Type
UC62LS4096JC
TSOPII-44
UC62LS4096KC
BGA-48
UC62LS4096AC
0 ~ 70
3.0V ~ 3.6V
20/25
2uA
20mA
DICE
UC62LS4096JI
TSOPII-44
UC62LS4096KI
BGA-48
UC62LS4096AI
-40 ~
85
3.0V ~ 3.6V
20/25
2uA
20mA
DICE
PIN CONFIGURATIONS
A4
1
A3
2
A2
3
A1
4
A0
5
CE
6
DQ0
7
DQ1
8
DQ2
9
DQ3
10
11
GND
12
DQ4
13
DQ5
14
DQ6
15
DQ7
16
WE
17
A16
18
A15
19
A14
20
A13
21
A12
22
A5
44
A6
43
A7
42
OE
41
UB
40
LB
39
DQ15
38
DQ14
37
DQ13
36
DQ12
35
GND
34
VCC
33
DQ11
32
DQ10
31
DQ9
30
DQ8
29
NC
28
A8
27
A9
26
A10
25
A11
24
A17
23
UC62LS4096JI
LB
OE
A0
A1
A2
NC
DQ8
UB
A3
A4
CE
DQ0
DQ9
DQ10
A5
A6
DQ1
DQ2
GND
DQ11
NC
A7
DQ3
VCC
VCC
DQ12
NC
A16
DQ4
GND
DQ14
DQ13
A14
A15
DQ5
DQ6
DQ15
NC
A12
A13
WE
DQ7
NC
A8
A9
A10
A11
A17
VCC
UC62LS4096JC
BLOCK DIAGRAM
MEMORY ARRAY
256K X 16 Bits
ROW
DECOD
E
R
COLUMN DECODER
SENSE AMPLIFIER
&
WRITE DRIVER
I/O BUFFER
X16
AD
DR
E
S
S
I
N
PU
T
B
U
FFER
CO
N
T
RO
L
BL
O
C
K
CO
N
T
RO
L
I
N
P
U
T
BU
FFE
R
COL
Address
ROW
Address
CE
WE
OE
A0 -
A17
CE
WE
OE
DQ0 ~ DQ15
UB
LB
UB
LB
U-Chip Technology Corp. LTD.
Preliminary
Rev.1.0
Reserves the right to modify document contents without notice.
PAGE
1
Low Power CMOS SRAM
256K X 16
UC62LS4096
-20/-25
PIN DESCRIPTION
Name Type
Function
A0 A17
Input
Address inputs for selecting one of the 262,144 x 16 bit words in the RAM
CE\ Input
CE\ is active LOW. Chip enable must be active when data read from or write to the device. If chip
enable is not active, the device is deselected and not in a standby power down mode. The DQ
pins will be in high impedance state when the device is deselected.
WE\ Input
The Write enable input is active LOW and controls read and write operations. With the chip
selected, when WE\ is HIGH and OE\ is LOW, output data will be present on the DQ pins, when
WE\ is LOW, the data present on the DQ pins will be written into the selected memory location.
OE\ Input
The output enable input is active LOW. If the output enable is active while the chip is selected
and the write enable is inactive, data will be present on the DQ pins and they will be enabled.
The DQ pins will be in the high impedance state when OE\ is inactive.
UB\ and LB\
Input
Lower byte and upper byte data input/output control pins.
DQ0 DQ15
I/O
These 16 bi-directional ports are used to read data from or write data into the RAM.
Vcc Power
Power Supply
Gnd Power
Ground
TRUTH TABLE
Mode
WE\
CE\
OE\
LB\
UB\
I/O 0 ~ 7
I/O 8 ~ 15
Vcc Current
Not Selected
X H X X X High Z
High Z
I
SB
,I
SB1
H L H X X
Output Disabled
X L X H H
High Z
High Z
I
CC
H L L L H D
OUT
High
Z
H L L H L High
Z D
OUT
Read
H L L L L D
OUT
D
OUT
I
CC
L L X L H D
IN
High
Z
L L X H L High
Z D
IN
Write
L L X L L D
IN
D
IN
I
CC
ABSOLUTE MAXIMUM RATINGS
(1)
SYMBOL PARAMETER
RATING
UNIT
V
TERM
Terminal Voltage with
Respect to GND
-0.5 to V
CC
+0.5
V
T
BIAS
Temperature Under Bias
-40 to 125
T
STG
Storage Temperature
-50 to 150
PT Power
Dissipation
0.5
W
I
OUT
DC Output Current
10
mA
1. Stresses greater than those listed under ABSOLUTE
MAXIMUM RATINGS may cause permanent damage to the
device. This is a stress rating only and functional operation of
the device at these or any other conditions above those
indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for
extended periods may affect reliability.
OPERATING RANGE
RANGE
AMBIENT
TEMPERATURE
V
CC
Commercial
0
to 70
3.0V ~ 3.6V
Industrial
-40
to 85
3.0V ~ 3.6V
CAPACITANCE
(1)
(TA=25
,f=1.0MHz)
SYMBOL
PARAMETER
CONDITIONS MAX. UNIT
CIN
Input
Capacitance
VIN=0V 6 pF
CDQ
Input/Output
Capacitance
VDQ 8
pF
1. This parameter is guaranteed and not 100% tested.
U-Chip Technology Corp. LTD.
Preliminary
Rev.1.0
Reserves the right to modify document contents without notice.
PAGE
2
Low Power CMOS SRAM
256K X 16
UC62LS4096
-20/-25
DC ELECTRICAL CHARACTERISTICS (TA=0
to 70
)
Symbol Comment
Test Condition
MIN. TYP.
(1)
MAX. UNITS
V
IL
Guaranteed Input Low
Voltage
(2)
V
CC
=2.4V
-0.5 - 0.8 V
V
IH
Guaranteed Input High
Voltage
(2)
V
CC
=3.6V
2.0 -
Vcc-0.2
V
I
L
Input Leakage Current
V
CC
=3.6V V
IN
=0V to V
CC
- - 1
uA
I
OL
Output Leakage Current
V
CC
=3.6V CE\=V
IH
or OE\=V
IH
V
IO
=0V t V
CC
- - 1
uA
V
OL
Output Low Voltage
V
CC
=3.6V, I
OL
=2mA
- - 0.4
V
V
OH
Output High Voltage
V
CC
=3.0V, I
OH
=-1mA
2.4 - - V
I
CC
Operating Power Supply
Current
CE\=V
IL
,I
DQ
=0mA, F=Fmax
(3)
- - 20
mA
I
SB1
TTL Standby Current
CE\=V
IH
, V
IN
=V
IH
to V
IL
- - 1
mA
I
SB2
CMOS Standby Current
CE\
V
CC
-0.2V, V
IN
=V
CC
-0.2V
or 0.2V , F=0
(4)
- 2 10
uA
1. Typical characteristics are at TA = 25
o
C.
2. These are absolute values with respect to device ground and all overshoots due to system or tester notice are included.
3. Fmax = 1/tRC .
4. F=0 means input signals must be keep in static state.
DATA RETENTION CHARACTERISTICS ( TA=0
to 70
)
Symbol Comment
Test
Condition
MIN. TYP.
(1)
MAX. UNITS
V
DR
VCC to Data Retention
CE\
V
CC
- 0.2V
V
IN
V
CC
-0.2V or V
IN
0.2V
1.2 - - V
I
CCDR
Data Retention Current
CE\
V
CC
- 0.2V
V
IN
V
CC
-0.2V or V
IN
0.2V
- 0.1 1 uA
t
DR
Chip Deselect to Data
Retention Time
0 - - ns
t
R
Operation Recovery Time
See Retention Waveform
T
RC
(2)
- - ns
1. V
CC
= 1.5V, TA = 25
.
2. t
RC
= Read Cycle Time
LOW VCC DATA RETENTION WAVEFORM
(1)
(CE\ Controlled)
Data Retention Mode
V
DR
>= 1. 2V
t
CDR
t
R
VIH
VIH
CE >= V
CC
- 0. 2V
Vcc
CE
U-Chip Technology Corp. LTD.
Preliminary
Rev.1.0
Reserves the right to modify document contents without notice.
PAGE
3
Low Power CMOS SRAM
256K X 16
UC62LS4096
-20/-25
AC TEST CONDITIONS
Input Pulse Levels
Input Rise and Fall Times
Input and Output Timing Reference Level
VCC to 0V
1V/ns
0.5V
CC
AC TEST LOADS AND WAVEFORMS
3.3V
OUTPUT
126
9
1404
30
p
F
INCLUDING
JIG AND
SCOPE
FIGURE 1A
3.3V
OUTPUT
319
353
5pF
INCLUDING
JIG AND
SCOPE
FIGURE 1B
667
TERMINAL EQUIVALENT
OUTPUT
1.73V
GND
V
CC
1V/ns
1V/ns
10%
90%
90%
10%
ALL INPUT PULSES
FIGURE 2
KEY TO SWITCHING WAVEFORMS
WAVEFORMS INPUTS OUTPUTS
MUST BE
STEADY
MUST BE
STEADY
MAY CHANGE
FROM H TO L
WILL BE
CHANGE
FROM H TO L
MAY CHANGE
FROM L TO H
WILL BE
CHANGE
FROM L TO H
DON'T CARE
ANY CHANGE
PERMITTED
CHANGE
STATE
UNKNOWN
DOES NOT
APPLY
CENTER LINE
IS HIGH
IMPEDANCE
OFF STATE
AC ELECTRICAL CHARACTERISTICS (TA=0
to 70
, V
CC
=3.0V~3.6V)
READ CYCLE
UC62LS4096-20 UC62LS4096-25
JEDEC
PARAMETER
NAME
PARAMETER
NAME
DESCRIPTION
Min
Typ
Max Min Typ Max
UNIT
t
AVAX
t
RC
Read
Cycle
Time
20
- - 25 - - ns
t
AVQV
t
AA
Address
Access
Time
- - 20 - - 25
ns
t
ELQV
t
CE
Chip
Select
Access
Time
- - 20 - - 25
ns
t
BA
t
BA
Data Byte Control Access Time
10
10
ns
t
GLQV
t
OE
Output Enable to Output Valid
-
-
10
-
-
10
ns
t
ELQX
t
CLZ
Chip Select to Output Low Z
5
-
-
5
-
-
ns
t
GLQX
t
OLZ
Output Enable to Output Low Z
3
-
-
3
-
-
ns
t
BE
t
BE
Data Byte Control To Output Low Z
5
5
ns
t
EHQZ
t
CHZ
Chip Deselect to Output in High Z
-
-
10
-
-
10
ns
t
GHQZ
t
OHZ
Output Disable to Output in High Z
-
-
10
-
-
10
ns
t
BDO
t
BDO
Data Byte Control To Output High Z
-
10
-
10
ns
t
AXOX
t
OH
Address Chang to Output Change
5
-
-
5
-
-
ns
U-Chip Technology Corp. LTD.
Preliminary
Rev.1.0
Reserves the right to modify document contents without notice.
PAGE
4
Low Power CMOS SRAM
256K X 16
UC62LS4096
-20/-25
SWITCHING WAVEFORMS (READ CYCLE)
READ CYCLE1
(1,2,4)
t
AA
t
OH
t
OH
t
RC
ADDRESS
D
OUT
READ CYCLE2
(1,3,4)
t
CE
t
CLZ
(5)
t
CHZ
(5)
CE
D
OUT
READ CYCLE3
(1,4)
t
AA
t
OH
t
RC
ADDRESS
t
CHZ
(5)
CE
D
OUT
OE
t
OHZ
(1,5)
t
OE
t
OLZ
t
BA
t
BE
t
CE
t
CLZ
(5)
t
BDO
UB/LB
NOTES:
1. WE\ is high in read cycle.
2. Device is continuously selected when CE\ = VIL
3. Address valid prior to or coincident with CE\ transition low.
4. OE\ = VIL.
5. Transition is measured 500mV from steady state with CL=5pF as shown in Figure 1B. The
parameter is guaranteed but not 100% tested.
U-Chip Technology Corp. LTD.
Preliminary
Rev.1.0
Reserves the right to modify document contents without notice.
PAGE
5
Low Power CMOS SRAM
256K X 16
UC62LS4096
-20/-25
AC ELECTRICAL CHARACTERISTICS (TA=0
to 70
, VCC=3.0V~3.6V)
WRITE CYCLE
UC62LS4096-20 UC62LS4096-25
JEDEC
PARAMETER
NAME
PARAMETER
NAME
DESCRIPTION
Min
Typ
Max Min Typ Max
UNIT
t
AVAX
t
WC
Write Cycle Time
20
-
-
25
-
-
ns
t
E1LWH
t
CW
Chip Select to END of Write
15
-
-
15
-
-
ns
t
AVWL
t
AS
Address
Setup
Time
0 - - 0 - - ns
t
AVWH
t
AW
Address valid to End of Write
15
-
-
15
-
-
ns
t
BW
t
BW
Data Byte Control End of Write
15
15
Ns
t
WLWH
t
WP
Write Pulse Width
15
-
-
15
-
-
ns
t
WHAX
t
WR
Write
Recovery
Time
0 - - 0 - - ns
t
WLOZ
t
WHZ
Write to Output in High Z
-
-
8
-
-
10
ns
t
DVWH
t
DW
Data to Write Time Overlap
8
-
10
-
ns
t
WHDX
t
DH
Data Hold Time for Write End
0
-
-
0
-
-
ns
t
GHOZ
t
OHZ
Output Disable to Output In High Z
-
-
8
-
-
10
ns
t
WHQX
t
OW
End of Write to Output Active
5
-
-
5
-
-
ns
SWITCHING WAVEFORMS (WRITE CYCLE)
WRITECYCLE1
(1)
t
WC
ADDRESS
t
DH
t
OHZ
WE
D
OUT
OE
CE
t
CW
(11)
t
WP
(2)
t
AW
t
AS
(4,10)
D
IN
t
DW
t
BW
UB/LB
U-Chip Technology Corp. LTD.
Preliminary
Rev.1.0
Reserves the right to modify document contents without notice.
PAGE
6
Low Power CMOS SRAM
256K X 16
UC62LS4096
-20/-25
WRITE CYCLE2
(1,6)
t
WC
ADDRESS
t
DH
t
WHZ
WE
D
OUT
CE
t
CW
(11)
t
WP
(2)
t
AW
t
AS
D
IN
t
DW
t
OH
(8)
(7)
NOTES:
1. WE\ must be high during address transitions.
2. The internal write time of the memory is defined by the overlap of CE\ and WE\ low. All signals
must be active to initiate a write and any one can terminate a write by going inactive. The data
input setup and hold timing should be referenced to the second transition edge of the signal that
terminates the write.
3. T
WR
is measured from the earlier of CE\ or WE\ going high at the end of write cycle.
4. During this period, DQ pins are in the output state so that the input signals of opposite phase to
the outputs must not be applied.
5. If the CE\ low transition occurs simultaneously with the WE\ low transitions or after the WE\
transition, output remain in a high impedance state.
6. OE\ is continuously low (OE\ = V
IL
).
7. D
OUT
is the same phase of write data of this write cycle.
8. D
OUT
is the read data of next address.
9. If CE\ is low during this period, DQ pins are in the output state. Then the data input signals of
opposite phase to the outputs must not be applied to them.
10. Transition is measured 500mV from steady state with C
L
= 5pF as shown in Figure 1B. The
parameter is guaranteed but not 100% tested.
11. TCW is measured from the later of CE\ going low to the end of write.
U-Chip Technology Corp. LTD.
Preliminary
Rev.1.0
Reserves the right to modify document contents without notice.
PAGE
7
Low Power CMOS SRAM
256K X 16
UC62LS4096
-20/-25
ORDERING INFORMATION
UC62LS4096 AB -- YY
A => GRADE
J
:TSOP(II)
K :BGA
A :DICE
B
=>
GRADE
C
:COMMERCIAL
(0
~
70
)
I
:INDUSTRIAL
(-40
~
85
)
YY
=>
SPEED
20:
20ns
25:
25ns
U-Chip Technology Corp. LTD.
Preliminary
Rev.1.0
Reserves the right to modify document contents without notice.
PAGE
8
Low Power CMOS SRAM
256K X 16
UC62LS4096
-20/-25
PACKAGE DIMENSIONS
TSOPII - 44
E
E1
44
23
22
1
D
e
b
Seating Plane "y"
A2
A1
A
UNIT
SYMBOL
INCH
MM
A1
0.0040.002
0.10.05
A
0.0433
0.004
1.10
0.1
A2
0.0390.002
1.00
0.05
b
0.012 ~ 0.018
0.3 ~ 0.45
c
0.005 ~ 0.008
0.12 ~ 0.21
b1
0.012 ~ 0.016
0.3 ~ 0.4
D
0.7250.004
18.410.1
c1
0.005 ~ 0.006
0.12 ~ 0.16
E1
0.4630.008
11.760.20
E
0.4000.004
10.16
0.1
e
0.03150.004
0.80
0.10
L1
0.01970.004
0.80
0.1
L
0.01970.004
0.500.1
0 ~ 8
0 ~ 8
y
0.004 Max.
0.1 Max.
DETAIL "A" (2:1)
"A"
A
A
L
L1
b
WITH PLATING
c1
c
b1
SECTION A-A
BASE METAL
D 1
D 0.1
E
0.
1
E1
e
Fig. A
Sold er B all diam eter = 0 .35 0.05
F ig. A
B all pitch e= 0.75
D E D 1 E 1
8.0 6.0 5.25 3.75
1.4 MA
X
0.
25
0.
05
S ide V iew
TO P V iew
48 M in i-B G A 6*8m m
U-Chip Technology Corp. LTD.
Preliminary
Rev.1.0
Reserves the right to modify document contents without notice.
PAGE
9
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