Low Power CMOS SRAM
32K X8 Bits
UC62WV0256
-35/-55/-70
Features:
Vcc operation voltage : 2.0V ~ 5.6V
Low power consumption :
15mA (Max.) operating current
2uA (Typ.) CMOS standby current
High Speed Access time :
35ns (Max) at Vcc = 2.7V
55ns (Max) at Vcc = 2.7V
70ns (Max.) at Vcc= 2.0V
Automatic power down when chip is deselected
Three state outputs and TTL compatible
Data retention supply voltage as low as 1.2V
Easy expansion with CE\ and OE\ options
Description
The UC62WV0256 is a high performance, very low
power CMOS Static Random Access Memory organized as
32,768 words by 8 bits and operates from a wide range of
2.7V to 5.6V supply voltage. Advanced CMOS technology
and circuit techniques provide both high speed and low
power features with a typical CMOS standby current of 1uA
and maximum access time of 70ns in 2.0V operation.
Easy memory expansion is provided enable (CE), and
active LOW output enable (OE) and three-state output
drivers.
The UC62WV0256 has an automatic power down
feature, reducing the power consumption significantly when
chip is deselected.
The UC62WV0256 is available in the JEDEC standard 28 pin
330mil Plastic SOP, 300mil Plastic SOJ, 600mil Plastic DIP
and 8mmx13.4mm TSOP (normal type).
PRODUCT FAMILY
Power Consumption
Speed
(ns)
STANDBY
VCC=5.6V
Operating(Max)
Product Family
Operating
Temperature
Vcc Range
Vcc=2.7V Vcc=5.0V
35ns
55ns
70ns
Package
Type
UC62WV0256BC
SOP-28
UC62WV0256CC
TSOP-28
UC62WV0256DC
PDIP-28
UC62WV0256EC
SOJ-28
UC62WV0256AC
0
~ 70
2.0V ~ 5.6V
35/55/70
4uA
25mA
18mA
15mA
DICE
UC62WV0256BI
SOP-28
UC62WV0256CI
TSOP-28
UC62WV0256DI
PDIP-28
UC62WV0256EI
SOJ-28
UC62WV0256AI
-25
~ 85
2.0V ~ 5.6V
35/55/70
4uA
25mA
18mA
15mA
DICE
PIN CONFIGURATIONS
A14
1
A12
2
A7
3
A6
4
A5
5
A4
6
A3
7
A2
8
A1
9
A0
10
DQ0
11
DQ1
12
DQ2
13
GND
14
VCC
28
WE
27
A13
26
A8
25
A9
24
A11
23
OE
22
A10
21
CE
20
DQ7
19
DQ6
18
DQ5
17
DQ4
16
DQ3
15
UC62WV0256BC
UC62WV0256DC
UC62WV0256EC
OE
1
A11
2
A9
3
A8
4
A13
5
WE
6
VCC
7
A14
8
A12
9
A7
10
A6
11
A5
12
A4
13
A3
14
A10
28
CE
27
DQ7
26
DQ6
25
DQ5
24
DQ4
23
DQ3
22
GND
21
DQ2
20
DQ1
19
DQ0
18
A0
17
A1
16
A2
15
UC62WV0256BI
UC62WV0256DI
UC62WV0256EI
UC62WV0256CI
UC62WV0256CC
BLOCK DIAGRAM
MEMORY ARRAY
32K X 8 Bits
ROW
DE
CODE
R
COLUMN DECODER
SENSE AMPLIFIER
&
WRITE DRIVER
I/O BUFFER
X8
ADDRESS INPUT
BUF
F
E
R
CONT
RO
L
BL
OCK
CONT
RO
L
IN
P
U
T
BUF
F
E
R
COL
Address
ROW
Address
CE
WE
OE
A0
-
A1
4
CE
WE
OE
DQ0
DQ1
DQ
2
DQ
3
DQ
4
DQ5
DQ
6
DQ7
U-Chip Technology Corp. LTD.
Revision 2.0
Reserves the right to modify document contents without notice.
PAGE 1
Low Power CMOS SRAM
32K X8 Bits
UC62WV0256
-35/-55/-70
PIN DESCRIPTION
Name Type
Function
A0 A14
Input
Address inputs for selecting one of the 32768 x 8 bit words in the RAM
CE\ Input
CE\ is active LOW. Chip enable must be active when data read from or write to the device. If chip
enable is not active, the device is deselected and not in a standby power down mode. The DQ
pins will be in high impedance state when the device is deselected.
WE\ Input
The Write enable input is active LOW and controls read and write operations. With the chip
selected, when WE\ is HIGH and OE\ is LOW, output data will be present on the DQ pins, when
WE\ is LOW, the data present on the DQ pins will be written into the selected memory location.
OE\ Input
The output enable input is active LOW. If the output enable is active while the chip is selected
and the write enable is inactive, data will be present on the DQ pins and they will be enabled.
The DQ pins will be in the high impedance state when OE\ is inactive.
DQ0 DQ7
I/O
These 8 bi0directional ports are used to read data from or write data into the RAM.
Vcc Power
Power Supply
Gnd Power
Ground
TRUTH TABLE
Mode
WE\
CE\
OE\
I/O state
Vcc Current
Not Selected
X
H
X
High Z
I
SB
,I
SB1
Output
Disabled
H L H
High
Z
I
CC
Read H
L
L
D
OUT
I
CC
Write L
L
X
D
IN
I
CC
ABSOLUTE MAXIMUM RATINGS
(1)
SYMBOL PARAMETER
RATING
UNIT
V
TERM
Terminal Voltage with
Respect to GND
-0.5 to V
CC
+0.5
V
T
BIAS
Temperature Under Bias
-40 to 125
T
STG
Storage Temperature
-50 to 150
PT Power
Dissipation
50mW
W
I
OUT
DC Output Current
10
mA
1. Stresses greater than those listed under ABSOLUTE
MAXIMUM RATINGS may cause permanent damage to the
device. This is a stress rating only and functional operation of
the device at these or any other conditions above those
indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for
extended periods may affect reliability.
OPERATING RANGE
RANGE
AMBIENT
TEMPERATURE
V
CC
Commercial
0
to 70
2.0V ~ 5.6V
Industrial
-25
to 85
2.0V ~ 5.6V
CAPACITANCE
(1)
(TA=25
,f=1.0MHz)
SYMBOL
PARAMETER
CONDITIONS MAX. UNIT
CIN
Input
Capacitance
VIN=0V 6 pF
CDQ
Input/Output
Capacitance
VDQ 8
pF
1. This parameter is guaranteed and not 100% tested.
U-Chip Technology Corp. LTD.
Revision 2.0
Reserves the right to modify document contents without notice.
PAGE 2
Low Power CMOS SRAM
32K X8 Bits
UC62WV0256
-35/-55/-70
DC ELECTRICAL CHARACTERISTICS (TA=-25
to 85
, VCC=2.0V to 5.6V)
Symbol Comment
Test Condition
MIN. TYP.
(1)
MAX. UNITS
V
IL
Guaranteed Input Low
Voltage
(2)
V
CC
=5.0V
-0.5 - 0.8 V
V
IH
Guaranteed Input High
Voltage
(2)
V
CC
=5.0V
2.0 -
Vcc-0.2
V
I
L
Input Leakage Current
V
CC
=5.6V V
IN
=0V to V
CC
- - 1
uA
I
OL
Output Leakage Current
V
CC
=5.6V CE\=V
IH
or OE\=V
IH
V
IO
=0V t V
CC
- - 1
uA
V
OL
Output Low Voltage
V
CC
=5.6V, I
OL
=2mA
- - 0.4
V
V
OH
Output High Voltage
V
CC
=3.0V, I
OH
=-1mA
2.4 - - V
I
CC
Operating Power Supply
Current
CE\=V
IL
,I
DQ
=0mA, F=Fmax
(3)
- - 15
mA
I
SB1
TTL Standby Current
CE\=V
IH
, V
IN
=V
IH
to V
IL
- - 1
mA
I
SB2
CMOS Standby Current
CE\
V
CC
-0.2V, V
IN
=V
CC
-0.2V
to 0.2V
- 2 4
uA
1. Typical characteristics are at TA = 25
.
2. These are absolute values with respect to device ground and all overshoots due to system or tester notice are included.
3. Fmax = 1/tRC, tRC=70ns .
DATA RETENTION CHARACTERISTICS ( TA=0
to 70
)
Symbol Comment
Test
Condition
MIN. TYP.
(1)
MAX. UNITS
V
DR
VCC to Data Retention
CE\
V
CC
- 0.2V
V
IN
V
CC
-0.2V or V
IN
0.2V
1.2 - - V
I
CCDR
Data Retention Current
CE\
V
CC
- 0.2V
V
IN
V
CC
-0.2V or V
IN
0.2V
- 0.5 1 uA
t
DR
Chip Deselect to Data
Retention Time
0 - - ns
t
R
Operation Recovery Time
See Retention Waveform
T
RC
(2)
- - ns
1. V
CC
= 1.5V, TA = 25
.
2. t
RC
= Read Cycle Time
LOW VCC DATA RETENTION WAVEFORM
(1)
(CE\ Controlled)
Data Retention Mode
V
DR
>= 1. 2V
t
CDR
t
R
VIH
VIH
CE >= V
CC
- 0. 2V
Vcc
CE
U-Chip Technology Corp. LTD.
Revision 2.0
Reserves the right to modify document contents without notice.
PAGE 3
Low Power CMOS SRAM
32K X8 Bits
UC62WV0256
-35/-55/-70
AC TEST CONDITIONS
Input Pulse Levels
Input Rise and Fall Times
Input and Output Timing Reference Level
VCC/0V
1V/ns
0.5VCC
AC TEST LOADS AND WAVEFORMS
3.3V
OUTPUT
12
69
1404
100pF
INCLUDING
JIG AND
SCOPE
FIGURE 1A
3.3V
OUTPUT
12
69
1404
5pF
INCLUDING
JIG AND
SCOPE
FIGURE 1B
667
TERMINAL EQUIVALENT
OUTPUT
1.73V
GND
V
CC
5ns
5ns
10%
90%
90%
10%
ALL INPUT PULSES
FIGURE 2
KEY TO SWITCHING WAVEFORMS
WAVEFORMS INPUTS OUTPUTS
MUST BE
STEADY
MUST BE
STEADY
MAY CHANGE
FROM H TO L
WILL BE
CHANGE
FROM H TO L
MAY CHANGE
FROM L TO H
WILL BE
CHANGE
FROM L TO H
DON'T CARE
ANY CHANGE
PERMITTED
CHANGE
STATE
UNKNOWN
DOES NOT
APPLY
CENTER LINE
IS HIGH
IMPEDANCE
OFF STATE
AC ELECTRICAL CHARACTERISTICS (TA=0
to 70
, V
CC
=3.0V)
READ CYCLE
UC62WV0256-35 UC62WV0256-70
JEDEC
PARAMETER
NAME
PARAMETER
NAME
DESCRIPTION
Min Typ
Max
Min
Typ Max
UNIT
t
AVAX
t
RC
Read
Cycle
Time
35 - - 70 - -
ns
t
AVQV
t
AA
Address
Access
Time
-
-
35
-
-
70
ns
t
ELQV
t
CE
Chip
Select
Access
Time
-
-
35
-
-
70
ns
t
GLQV
t
OE
Output Enable to Output Valid
-
-
15
-
-
50
ns
t
ELQX
t
CLZ
Chip Select to Output Low Z
5
-
-
10
-
-
ns
t
GLQX
t
OLZ
Output Enable to Output Low Z
5
-
-
10
-
-
ns
t
EHQZ
t
CHZ
Chip Deselect to Output in High Z
0
-
35
0
-
35
ns
t
GHQZ
t
OHZ
Output Disable to Output in High Z
0
-
20
0
-
30
ns
t
AXOX
t
OH
Address Chang to Output Change
10
-
-
10
-
-
ns
U-Chip Technology Corp. LTD.
Revision 2.0
Reserves the right to modify document contents without notice.
PAGE 4
Low Power CMOS SRAM
32K X8 Bits
UC62WV0256
-35/-55/-70
SWITCHING WAVEFORMS (READ CYCLE)
READ CYCLE1
(1,2,4)
t
AA
t
OH
t
OH
t
RC
ADDRESS
D
OUT
READ CYCLE2
(1,3,4)
t
CE
t
CLZ
(5)
t
CHZ
(5)
CE
D
OUT
READ CYCLE3
(1,4)
t
AA
t
OH
t
RC
ADDRESS
t
CE
t
CLZ
(5)
t
CHZ
(5)
CE
D
OUT
OE
t
OHZ
(1,5)
t
OE
t
OLZ
NOTES:
1. WE\ is high in read cycle.
2. Device is continuously selected when CE\ = VIL
3. Address valid prior to or coincident with CE\ transition low.
4. OE\ = VIL.
5. Transition is measured 500mV from steady state with CL=5pF as shown in Figure 1B. The
parameter is guaranteed but not 100% tested.
U-Chip Technology Corp. LTD.
Revision 2.0
Reserves the right to modify document contents without notice.
PAGE 5
Low Power CMOS SRAM
32K X8 Bits
UC62WV0256
-35/-55/-70
AC ELECTRICAL CHARACTERISTICS (TA=0
to 70
, Vcc=3.0V)
WRITE CYCLE
UC62WV0256-35 UC62WV0256-70
JEDEC
PARAMETER
NAME
PARAMETER
NAME
DESCRIPTION
Min Typ
Max
Min
Typ Max
UNIT
t
AVAX
t
WC
Write
Cycle
Time
35 - - 70 - -
ns
t
E1LWH
t
CW
Chip Select to END of Write
35
-
-
70
-
-
ns
t
AVWL
t
AS
Address
Setup
Time
0 - - 0 - - ns
t
AVWH
t
AW
Address valid to End of Write
35
-
-
70
-
-
ns
t
WLWH
t
WP
Write Pulse Width
20
-
-
50
-
-
ns
t
WHAX
t
WR
Write
Recovery
Time
0 - - 0 - - ns
t
WLOZ
t
WHZ
Write to Output in High Z
-
-
15
-
-
30
ns
t
DVWH
t
DW
Data to Write Time Overlap
15
-
40
-
ns
t
WHDX
t
DH
Data Hold Time for Write End
0
-
-
0
-
-
ns
t
GHOZ
t
OHZ
Output Disable to Output In High Z
0
-
15
0
-
30
ns
t
WHQX
t
OW
End of Write to Output Active
5
-
-
5
-
-
ns
SWITCHING WAVEFORMS (WRITE CYCLE)
WRITECYCLE1
(1)
t
WC
ADDRESS
t
DH
t
OHZ
WE
D
OUT
OE
CE
t
CW
(11)
t
WP
(2)
t
AW
t
AS
(4,10)
D
IN
t
DW
U-Chip Technology Corp. LTD.
Revision 2.0
Reserves the right to modify document contents without notice.
PAGE 6
Low Power CMOS SRAM
32K X8 Bits
UC62WV0256
-35/-55/-70
WRITE CYCLE2
(1,6)
t
WC
ADDRESS
t
DH
t
WHZ
WE
D
OUT
CE
t
CW
(11)
t
WP
(2)
t
AW
t
AS
D
IN
t
DW
t
OH
(8)
(7)
NOTES:
1. WE\ must be high during address transitions.
2. The internal write time of the memory is defined by the overlap of CE\ and WE\ low. All signals
must be active to initiate a write and any one can terminate a write by going inactive. The data
input setup and hold timing should be referenced to the second transition edge of the signal that
terminates the write.
3. T
WR
is measured from the earlier of CE\ or WE\ going high at the end of write cycle.
4. During this period, DQ pins are in the output state so that the input signals of opposite phase to
the outputs must not be applied.
5. If the CE\ low transition occurs simultaneously with the WE\ low transitions or after the WE\
transition, output remain in a high impedance state.
6. OE\ is continuously low (OE\ = V
IL
).
7. D
OUT
is the same phase of write data of this write cycle.
8. D
OUT
is the read data of next address.
9. If CE\ is low during this period, DQ pins are in the output state. Then the data input signals of
opposite phase to the outputs must not be applied to them.
10. Transition is measured 500mV from steady state with C
L
= 5pF as shown in Figure 1B. The
parameter is guaranteed but not 100% tested.
11. TCW is measured from the later of CE going low to the end of write.
U-Chip Technology Corp. LTD.
Revision 2.0
Reserves the right to modify document contents without notice.
PAGE 7
Low Power CMOS SRAM
32K X8 Bits
UC62WV0256
-35/-55/-70
ORDERING INFORMATION
UC62WV0256AB -- YY
A
=>
PACKAGE
A
:
DICE
B : 28 SOP 330mil
C : 28 TSOP 8X13.4mm
D : 28 PDIP 600mil
E : 28 SOJ 300mil
B => GRADE
C :COMMERCIAL; 0 ~ 70
I
: INDUSTRIAL; -25 ~ 85
YY => SPEED
70
:
70ns
55
:
55ns
35
:
35ns
PACKAGE DIMENSIONS
A
A
L
L1
7(4X)
b
WITH PLATING
c1
c
b1
DETAIL "A" (2:1)
SECTION A-A
BASE METAL
SOP - 28
0.0200.005X45"
"A"
E
E1
28
15
14
1
D
e
b
Seating Plane "y"
A2
A1
A
UNIT
SYMBOL
INCH
MM
A1
0.0090.005
0.2260.124
A
0.106
0.006
2.692
0.152
A2
0.0980.005
2.4890.127
b
0.014 ~ 0.020
0.35 ~ 0.50
c
0.008 ~ 0.012
0.20 ~ 0.32
b1
0.014 ~ 0.020
0.35 ~ 0.45
D
0.7130.005
18.1100.127
c1
0.008 ~ 0.011
0.20 ~ 0.28
E1
0.4650.012
11.8110.305
E
0.3310.005
8.4070.127
e
0.0500.006
1.2700.152
L1
0.06770.0079
1.720.2
L
0.03800.0104
0.9640.264
0 ~ 10
0 ~ 10
y
0.004 Max.
0.1 Max.
U-Chip Technology Corp. LTD.
Revision 2.0
Reserves the right to modify document contents without notice.
PAGE 8
Low Power CMOS SRAM
32K X8 Bits
UC62WV0256
-35/-55/-70
PACKAGE DIMENSIONS (continued)
b
WITH PLATING
c1
c
b1
SECTION A-A
BASE METAL
TSOP - 28
UNIT
SYMBOL
INCH
MM
28
15
14
1
28
15
14
1
D
"A"
A
L1
12
(2X)
"A" DETAIL VIEW
A
A2
A1
SEATING PLANE
A
0.254
GAUGE PLANE
12
(2X)
L
E
12
(2X)
12
(2X)
e
b
SEATING PLANE
A1
0.0045
0.0026
0.226
0.124
A
0.0433
0.004
1.10
0.10
A2
0.039
0.002
1.00
0.05
b
0.009
0.020
0.22
0.05
c
0.004 ~ 0.008
0.10 ~ 0.21
b1
0.008
0.001
0.20
0.03
D
0.465
0.004
11.80
0.10
c1
0.004 ~ 0.006
0.10 ~ 0.16
e
0.22
0.004
0.55
0.10
E
0.315
0.004
8.00
0.10
HD
0.528
0.008
13.40
0.20
L1
0.0315
0.004
0.80
0.10
L
0.0197
0.008
0.50
0.20
0
~ 8
0
~ 8
y
0.004 Max.
0.1 Max.
HD
PDIP - 28
S
B
L
UNIT
SYMBOL
INCH(BASE)
E1
eB
e
Q1
MM
L
S
D
B1
e
5 ~ 7
A1
A2
Q1
E1
eB
E
5 ~ 7
c
0.070
0.005
6 3
A1
A2
B1
c
B
D
E
6 3
0.080
0.010
0.130
0.010
0.640
0.020
0.100(TYP)
0.544
0.004
0.600
0.010
0.146
0.005
0.010
0.004
0.060
0.010
0.018
0.005
0.150
0.005
0.010(MIN)
1.778
0.127
2.032
0.254
3.302
0.254
16.256
0.508
2.540(TYP)
13.818
0.102
15.240
0.254
37.084
0.127
0.254
0.102
1.524
0.254
0.457
0.127
3.810
0.127
0.254(MIN)
U-Chip Technology Corp. LTD.
Revision 2.0
Reserves the right to modify document contents without notice.
PAGE 9
Low Power CMOS SRAM
32K X8 Bits
UC62WV0256
-35/-55/-70
PACKAGE DIMENSIONS (continued)
SOJ - 28
E
E1
28
15
14
1
D
Seating Plane
A2
A1
A
UNIT
SYMBOL
INCH
A1
A
--
A2
b
c
b1
D
E
e
H
E
e1
y
S
b
b1
e
e1
L
c
Min
Max
Nom
--
0.140
MM
--
Min
Max
Nom
--
0.140
L
S
0.027
--
--
0.69
--
--
0.095
0.1
0.105
2.41
2.54
2.67
0.026
0.028
0.032
0.66
0.71
0.81
0.016
0.018
0.022
0.41
0.46
0.56
0.008
0.010
0.014
0.20
0.25
0.36
--
0.710
0.730
--
18.03
18.54
0.295
0.300
0.305
7.49
7.62
7.75
0.044
0.050
0.056
1.12
1.27
1.42
0.245
0.265
0.285
6.22
6.73
7.24
0.327
0.337
0.347
8.31
8.56
8.81
0.077
0.087
0.097
1.96
2.21
2.46
--
--
0.045
--
--
1.14
--
--
0.004
--
--
0.10
0
--
10
0
--
10
Note:
1. Dimension D Max & s include mold flash
or tie bar burns.
2. Dimension b does not include dambar
protrusion/intrusion.
3. Dimension D & E include mold mismatch
and are determined at the mold parting line.
4. Controlling dimension: Inch
5. General appearance spec. should be based
on final visual inspection spec.
U-Chip Technology Corp. LTD.
Revision 2.0
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