RTI-1

EATURES

Complete MIL-STD-1553B Remote Terminal
interface compliance

Dual-redundant data bus operation supported

Internal illegalization of selected mode code
commands

External illegal command definition capability

Automatic DMA control and address generation

Operational status available via dedicated lines or
internal status register

ASD/ENASC (formerly SEAFAC) tested and
approved

Available in ceramic 84-lead leadless chip carrier and
84-pin pingrid array

Full military operating temperature range, -55

C to

+125

C, screened to the specific test methods listed in

Table I of MIL-STD-883, Method 5004, Class B

JAN-qualified devices available

Figure 1. UT1553B RTI Functional Block Diagram

MIL-STD-1553B SERIAL BUS

TRANSCEIVER

I/O

OUT

OUTPUT MUL

TIPLEXING AND

SELF TEST

WRAP-AR

OUND

LOGIC

DECODER

CHANNEL

DECODER

CHANNEL

ENCODER

MUX

MODE CODE/

SUB ADDRESS

COMMAND

RECOGNITION

LOGIC

CONTROL

AND

ERROR LOGIC

DATA

TRANSFER

LOGIC

ILLEGAL
COMMAND

MEMORY

ADDRESS
CONTROL

TIMEOUT

CLOCK AND

RESET LOGIC

2MHz

DATA I/O BUS

OUTPUT EN

MEMORY

ADDRESS

OUTPUTS

CONTROL

INPUTS

HOST

SYSTEM

ADDRESS

INPUTS

CONTROL

OUTPUTS

TIMERON

12MHz

RESET

UT1553B RTI Remote Terminal Interface

RTI-2

Table of Contents

1.0 ARCHITECTURE

AND

OPERATION

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3

1.1

Host Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
1.1.1 Direct Memory Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
1.1.2 Transparent Memory Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4

1.2

Internal Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4

1.3

Mode Codes and Subaddresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7

1.4

MIL-STD-1553B Subaddress and Mode Codes . . . . . . . . . . . . . . . . . . . . . . . .9

1.5

Remote Terminal Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9

1.6

Internal Self-Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10

1.7

Power-up and Master Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10

1.8

Encoder and Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

1.9

Illegal Command Decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

2.0

MEMORY MAP EXAMPLE

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

3.0

PIN IDENTIFICATION AND DESCRIPTION

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

4.0

MAXIMUM AND RECOMMENDED OPERATING CONDITIONS

. . . . . . . . . . . . . . . . . 21

5.0

DC ELECTRICAL CHARACTERISTICS

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

6.0

AC ELECTRICAL CHARACTERISTICS

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

7.0

PACKAGE OUTLINE DRAWINGS

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

RTI-3

1.0 A

RCHITECTURE

PERATION

The UT1553B RTI is an interface device linking a MIL-
STD-1553 serial data bus and a host microprocessor system.
The RTI's MIL-STD-1553B interface includes encoding/
decoding logic, error detection, command recognition,
memory address control, clock, and reset circuits.

Decoders

The UT1553B RTI contains two separate free-running
decoders to insure that all redundancy requirements of MIL-
STD-1553B are met. Each decoder receives, decodes, and
verifies biphase Manchester II data. Proper frequency and
edge skew are also verified.

Command Recognition Logic

The command recognition logic monitors the output of both
decoders at all times. Recognition of a valid command
causes a reset of present interface activity followed by
execution of the command. This procedure meets the
requirement for superseding valid commands.

Encoder

The encoder receives serial data from the data transfer logic,
converts it to Manchester II form with proper
synchronization and parity, and passes it to the output and
self-test logic.

Data Transfer Logic

The data transfer logic provides double-buffered 16-bit
parallel-to-serial and serial-to-parallel conversion during
reception and transmission of data.

Memory Address Control

The memory address control logic controls the output of the
three-state address lines during memory access. In DMA
system implementations, the memory address control
provides RTI-generated addresses. In a pseudo-dual-port
memory configuration, the memory address control logic
provides either RTI-generated or host system addressing.

Control and Error Logic

The control and error logic performs the following four
major functions:

Interface control for proper processing of MIL-
STD-1553B commands

Error checking of both MIL-STD-1553B data and
RTI operation

Memory control (DMA or pseudo-dual-port) for
proper data transfer

Operational status and control signal generation

Output Multiplexing and Self-Test Logic

This logic directs the output of the encoder to one of four
places:- Channel A outputs
- Channel B outputs
- Channel A decoders during self-test
- Channel B decoders during self-test

Clock and Reset Logic

The UT1553B RTI requires a 12MHz input clock to operate
properly. The RTI provides a 2MHz output for the system
designer to use. The device provides a hardware reset pin
as well as software-generated reset.

Timer Logic

The UT1553B RTI has a built-in 730ms timer that is
activated when the encoder is about to transmit. The timer
is reset upon receipt of a valid command, master reset, or a
time-out condition.

1.1 HOST INTERFACE

Configure the RTI into the host system for either a direct
memory or transparent memory access. The following
sections discuss the system configuration for each method
of memory management.

1.1.1 Direct Memory Access

In the direct memory access configuration the RTI and host
arbitrate for the shared 2K x 16 memory space. To request
access to memory the RTI asserts direct memory request
output (DMARQ); the system bus arbiter grants the RTI
access to memory by asserting the direct memory access
grant signal (MEMCK). The system arbiter should not assert
the MEMCK signal before the RTI has requested access to
memory (i.e., DMARQ asserted).

Once granted access to memory, the RTI address out
(ADDR OUT(10:0)), RAM chip select (RCS), RAM read/
write (RRD/RWR), and Data bus (DATA I/O(15:0)) provide
the interface signals to control the memory access. Figure
2 shows an example of a direct memory access system
configuration; for clarity the interface buffers and logic are
excluded. The host microprocessor also gains access to
memory by arbitration.

Take care to insure that bus contention does not occur
between the host and RTI Address buses or memory control
signals. To place the RTI Address Out bus in a high
impedance state negate the ADOEN input pin. Also note
that outputs RCS and RRD/RWR are not three-state outputs.
When the RTI is not writing to memory, bidirectional Data
bus DATA I/O(15:0) is an input (i.e., not actively driving
the bus).

RTI-4

The host microprocessor gains access to the RTI internal
registers by controlling input pins CS, CTRL, ADDR IN
(10:0), and RD/WR. During message processing the host
microprocessor should limit access to RTI internal registers.

1.1.2 Transparent Memory Access

Configured in the transparent memory mode the host
microprocessor accesses shared memory through the RTI.
Arbitration for access to the bus is performed as discussed
in section 1.1.1 of this document.

When granted access to memory, the RTI asserts memory
control signals ADDR OUT(10:0), RCS, and RRD/RWR.
For host-controlled memory accesses the RAM memory
address from the host is propagated from the Address In bus
ADDR IN (10:0) to the Address Out bus ADDR OUT (10:0).
Memory control signals RD/WR and CS are also propagated
through the RTI as RRD/RWR and RCS. Input CTRL is
negated during all transparent memory accesses to prevent
the RTI from inadvertently performing an internal register
access or software reset. While CS is asserted, the RTI's
bidirectional Data bus DATA I/O (15:0) is an input (i.e., not
actively driving bus).

1.2 Internal Register Description

The RTI uses three internal registers to allow the host to
control the RTI operation and monitor its status. The host
uses the following inputs Control (CTRL), Chip Select
(CS), Read/Write (RD/WR), and ADDR IN (0) to read the
16-bit System Register or write to the 8-bit Control Register.
The Control Register toggles bits in the MIL-STD-1553B
status word, enables biphase inputs, selects terminal active
flag, and puts the part in self-test. The System Register
supplies operational status of the UT1553B RTI to the host.
The Last Command Register saves the command word for
a Transmit Last Command mode code, along with
operational status from the System Register.

Shared

Memory

Host

Computer

RTI

UT1553B

DMA

CONTROLLER

Figure 2. Direct Memory Access Configuration

DATA(15:0)

ADDR(10:0)

CONTROL

Control Register (Write Only)

Figure 3. Transparent Memory Access Configuration

Shared

Memory

Host

Computer

RTI

UT1553B

DMA

CONTROLLER

DATA(15:0)

ADDR IN (10:0)

CONTROL

ADDR OUT (10:0)

CONTROL

DATA I/O (15:0)

RTI-5

The 8-bit write-only Control Register manages the operation of the RTI. Write to the Control Register by applying a logic zero
to CS, CTRL, RD/WR, and ADDR IN (0); if ADDR IN (0) is a logic one a master reset occurs. Data is loaded into the Control
Register via I/O pins DATA(7:0). Control Register writes must occur 50ns before the rising edge of COMSTR to latch data in
the outgoing status word.

System Register (Read Only)

The 16-bit read-only System Register provides the RTI system status. Read the System Register by applying a logic zero to
CS, CTRL, ADDR IN (0), and a logic one to RD/WR. The 16-bit contents of the System Register are read from data I/O pins
DATA(15:0).

Bit
Number

Initial
Condition Description

[0]

Channel A Enable. A logic one enables Channel A biphase inputs.

[0]

Channel B Enable. A logic one enables Channel B biphase inputs.

[0]

Terminal Flag. A logic one sets the Terminal Flag bit of the Status Register.

[0]

System Busy. A logic one sets the Busy bit of the System Register and inhibits
RTI access to memory. No data words are retrieved or stored; command word is
stored.

[0]

Subsystem Busy. A logic one sets the Subsystem Flag bit of the Status Register.

[0]

Self-Test Channel Select. This bit selects which channel the internal self-test
checks; a logic one selects Channel A and a logic zero selects Channel B.

[0]

Self-Test Enable. A logic one sets the RTI in the internal self-test mode and inhib-
its normal operation. Internal testing is not visible on biphase output
channels.

[0]

Service Request. A logic one sets the Service Request bit of the Status Register.

SRV

SELF
TEST

SUBS

BUSY

CH B

CH A

SELF

[ ] defines reset state

CONTROL REGISTER (WRITE ONLY)

MSB

Figure 4. Control Register

[0]

[0] [0] [0] [0] [0] [0]

LSB

Bit
Number

Initial
Condition

Description

[0]

MCSA(0). The LSB of the mode code or subaddress as indicated by the
logic state of bit 5.

[0]

MCSA(1). Mode code or subaddress as indicated by the state of bit 5.

[0]

MCSA(2). Mode code or subaddress as indicated by the state of bit 5.

[0]

MCSA(3). Mode code or subaddress as indicated by the state of bit 5.

[0]

MCSA(4). Mode code or subaddress as indicated by the state of bit 5.

[0] MC/SA. A logic one indicates that bits 4 through 0 are the subaddress of

the last command word, and that the last command word was a normal
transmit orreceive command. A logic zero indicates that bits 4 through 0
are a mode code, and that the last command was a mode code.

6 [1]

Channel

A/B. A logic one indicates that the most recent command arrived

onChannel A; a logic zero indicates that it arrived on Channel B.

RTI-6

[0]

Channel B Enabled. A logic one indicates that Channel B is available for
both reception and transmission.

[0]

Channel A Enabled. A logic one indicates that Channel A is available for
both reception and transmission.

[1]

Terminal Flag Enabled. A logic one indicates that the Bus Controller has
not issued an Inhibit Terminal Flag mode code. A logic zero indicates that
the Bus Controller, via the above mode code, is overriding the host sys-
tem's ability to set the Terminal Flag bit of the status word.

[0]

Busy. A logic one indicates the Busy bit is set. This bit is reset when the
SystemBusy bit in the Control Register is reset.

[0]

Self-Test. A logic one indicates that the RTI is in the self-test mode. This
bit isreset when the self-test is terminated.

[0]

TA Parity Error. A logic one indicates the wrong Terminal Address parity;
it causes the biphase inputs to be disabled and a message error condition.
This bit is reset by reloading the terminal address latch with correct parity.

[0]

Message Error. A logic one indicates that a message error has occurred
since the last System Register read. This bit is not reset until the System
Register has been examined and the message error condition is removed.

[0]

Valid Message. A logic one indicates that a valid message has been
received since the last System Register read. This bit is not reset until the
System Register has been examined.

[0]

Terminal Active. A logic one indicates the device is executing a transmit or
receive operation. The state of this bit is the logical NAND of the external
XMIT and RCV pins.

MCSA

TAPA

ERR

MESS

ERR

VAL

MESS

MCSA

SELF-

TEST

TERM

ACTV

BUSY

TFEN

CH A

CH B

CHNL

A/B

MC/

Figure 5. System Registers

[0]

[1]

[0]

[1]

[0]

[ ] defines reset state

SYSTEM REGISTER (READ ONLY)

MSB

LSB

RTI-7

Last Command Register (Read Only)

The 16-bit read-only Last Command Register provides the host with last command and operational status information. The
RTI transmits the lower 11 bits of this register along with terminal address upon receipt of a Transmit Last Command mode
code. Read the Last Command Register by applying a logic zero to CS, CTRL, and a logic one to RD/WR and ADDR IN (0).
The 16-bit contents of the Last Command Register are read from data I/O pins DATA(15:0).

1.3 Mode Codes and Subaddresses

The UT1553B RTI provides subaddress and mode code
decoding meeting MIL-STD-1553B. In addition, the device
has automatic internal illegal command decoding for
reserved MIL-STD-1553B mode codes. Upon command
word validation and decode, status pins MCSA(4:0) and
MC/SA become valid. Status pin MC/SA will indicate
whether the data pins MCSA(4:0) are mode code or
subaddress information. Status Register bits 5 through 0
contain the same information as pins MCSA(4:0) and MC/
SA.

The system designer can use signals MCSA(4:0), MC/SA,
BRDCST, XMIT, and RCV to illegalize mode codes,
subaddresses, and other message formats via the Illegal
Command (ILL COMM) input (see figure 23 on
page 36).

The RTI will internally decode the following mode codes
as illegal:

- Dynamic Bus Control

- Selected Transmitter Shutdown

- Override Selected Transmitter Shutdown

- All Reserved Mode Codes

If the RTI receives one of the above mode codes, the RTI
responds by transmitting a status word with the Message
Error bit set to logic one.

Mode codes which involve data transfer are processed like
receive and transmit commands. The RTI will not generate
DMA request for Transmit Status Word and Transmit Last
Command mode codes since the information is stored
internal to the RTI.

The following mode codes require assistance from the host:

- Synchronize

- Initiate Self-Test

- Reset Remote Terminal

For example, the RTI will accept and respond to a Reset
Remote Terminal mode code; however it will not perform
a reset operation. The host must interpret the mode code and
take appropriate action.

The RTI does not define or interpret the following data
words associated with mode code commands:

- Transmit Vector Word

- Synchronize With Data Word

- Transmit Bit Word

The RTI will accept and respond to mode code with data;
the host must interpret or define the data word. The RTI will
store or retrieve the data required for mode code command
from block #1 of the receive or transmit page

Bit
Number

Initial
Condition

Description

0 through 10

[all 1s]

Least significant 11 bits of the last command word.

[0]

Busy Bit. System Register bit 10.

[0]

Self-test. System Register bit 11.

[1]

Terminal Flag Enabled. System Register bit 9.

14 [1]

Channel

A/B. System Register bit 6.

[1]

Illegal Command. The RTI illegalized the last command.

RTI-8

RTI MODE CODE HANDLING PROCEDURE

T/R

Mode Code

Function

Operation

10100

Selected Transmitter Shutdown

1. Command word stored
2. MES ERR pin asserted
3. Message error latch set in System Register
4. Status word transmitted

0 10101

Override

Selected

Transmitter

Shutdown

1. Command word stored
2. MES ERR pin asserted
3. Message error latch set in System Register
4. Status word transmitted

10001

Synchronize (w/data)

1. Command word stored
2. Data word stored
3. Status word transmitted

00000

Dynamic Bus Control

1. Command word stored
2. MES ERR pin asserted
3. Message error latch set in System Register
4. Status word transmitted

1 00001

Synchronize

1. Command word stored
2. Status word transmitted

00010

Transmit Status Word

1. Command word stored
2. Status word transmitted

00011

Initiate Self-Test

1. Command word stored
2. Status word transmitted

00100

Transmitter Shutdown

1. Command word stored
2. Alternate bus shutdown
3. Status word transmitted

00101

Override Transmitter Shutdown

1. Command word stored
2. Alternate bus enabled
3. Status word transmitted

00110

Inhibit Terminal Flag Bit

1. Command word stored
2. Terminal Flag bit set to zero and disabled
3. Status word transmitted

00111

Override Inhibit Terminal Flag Bit

1. Command word stored Bit
2. Terminal Flag bit enabled, but not set to logic one
3. Status word transmitted

01000

Reset Remote Terminal

1. Command word stored
2. Status word transmitted

10010

Transmit Last Command Word

1. Status word transmitted
2. Last command word transmitted

10000

Transmit Vector Word

1. Command word stored
2. Status word transmitted
3. Data word transmitted

10011

Transmit BIT Word

1. Command word stored
2. Status word transmitted
3. Data word transmitted

Notes:

1. Further host interaction required for mode code operation.
2. Reserved mode code; A) MES ERR pin asserted, B) Message Error bit set, C) status word transmitted (ME bit set to logic one).

3.Status word not affected.

RTI-9

1.4 MIL-STD-1553B Subaddress and Mode Code Definitions

1.5 Remote Terminal Address

Assign the RTI remote terminal address by either a software
or hardware exercise. The host assigns the RTI remote
terminal address by performing a Control Register write;
the Terminal Address bus (TA(4:0)) is strobed into the RTI
Remote Terminal Address Register upon completion of the
Control Register write. To assign the RTI remote terminal
address via hardware, use the TALEN/PARITY input pin
operating in the terminal latch address enable mode. The
Terminal Address bus is latched into the RTI while the
TALEN is asserted (i.e., logic low). Valid remote terminal
addresses (RTA) include decimal 0 through 31 if Broadcast
is disabled, 0 through 30 if Broadcast is enabled

Parity Checker

An address parity check is performed to insure the remote
terminal address applied to TA(4:0) was properly latched
into the Remote Terminal Address Register. To perform a
parity check, enable the RTI parity circuit via EXT TEST
and EXT TST CH SEL A/B input pins. The parity bit is
entered through the TALEN/PARITY input pin operating in
the parity mode. Input pins EXT TEST and EXT TST CH
SEL A/B control dual-function input pin TALEN/PARITY;
see table 2 for description of operation.

If a parity error exists, the Parity Error bit of the System
Register is set to a logic one, biphase Channels A and B are
disabled (set to logic zero), the Message Error bit set to logic
one, and the message error pin is asserted.

Table 1. Subaddress and Mode Code Definitions Per MIL-STD-1553B

Subaddress Field
Binary (Decimal)

Message Format

Receive

Transmit

Description

00000 (00)

Mode Code Indicator

00001 (01)

User Defined

00010 (02)

User Defined

00011 (03)

User Defined

00100 (04)

User Defined

00101 (05)

User Defined

00110 (06)

User Defined

00111 (07)

User Defined

01000 (08)

User Defined

01001 (09)

User Defined

01010 (10)

User Defined

01011 (11)

User Defined

01100 (12)

User Defined

01101 (13)

User Defined

01110 (14)

User Defined

01111 (15)

User Defined

10000 (16)

User Defined

10001 (17)

User Defined

10010 (18)

User Defined

10011 (19)

User Defined

10100 (20)

User Defined

10101 (21)

User Defined

10110 (22)

User Defined

10111 (23)

User Defined

11000 (24)

User Defined

11001 (25)

User Defined

11010 (26)

User Defined

11011 (27)

User Defined

11100 (28)

User Defined

11101 (29)

User Defined

11110 (30)

User Defined

11111 (31)

Mode Code Indicator

Note:

1. Refer to mode code assignments per MIL-STD-1553B

RTI-10

The following are examples of sequences used to enter
remote terminal addresses into the RTI.

Example 1.

Hardware-Controlled Remote Terminal
Address (parity check disabled):

STATE 0, 2, or 3 (i.e., 00, 10, or 11)
TALEN - asserted (i.e., logic low)
TA(4:0) - valid RTA

Example 2.

Software-Controlled Remote Terminal
Address (parity check disabled):

EXT TEST and EXT TST CH SEL A/B
in STATE 0, 2, or 3 (i.e., 00, 10, or 11)
CTRL - logic zero
CS - logic zero
RD/WR - logic zero
ADDR IN (0) - logic zero
TALEN - logic one
TA(4:0) - valid RTA

Example 3.

Software Controlled Remote Terminal
Address (parity check enabled):

EXT TEST and EXT TST CH SEL A/B
in STATE 1 (i.e., 01)
CTRL - logic zero
CS - logic zero
RD/WR - logic zero
ADDR IN (0) - logic zero
PARITY - input must provide odd
parity
for the TA(4:0) bus
TA(4:0) - valid RTA

For examples 1 and 2, enabling the parity check circuit
(STATE 1) after the remote terminal address is stored results
in a parity check of the data loaded into the Remote Terminal
Address Register.

1.6 Internal Self-Test

Setting bit 6 of the Control Register to a logic one enables
the internal self-test. Disable Channels A and B at this time
to prevent bus activity during self-test by setting bits 0 and
1 of the Control Register to a logic zero. Normal operation
is inhibited when internal self-test is enabled. The RTI's
self-test capability is based on the fact that the MIL-STD-
1553B status word sync pulse is identical to the command
word sync pulse. Thus, if the status word from the encoder
is fed back to the decoder, the RTI will recognize the
incoming status word as a command word and thus cause
the RTI to transmit another status word. After the host
invokes self-test, the RTI self-test logic forces a status word
transmission even though the RTI has not received a
command word. The status word is sent to decoder A or B
depending on the channel the host selected for self-test. The
host controls the self-test by periodically changing the bit
patterns in the status word being transmitted. Writing to the
Control Register bits 2, 3, 4, and 8 changes the status word.
Monitor the self-test by sampling either the System Register
or the external status pins (i.e. Command Strobe
(COMSTR), Transmit (XMIT), Receive (RCV)). For a more
detailed explanation of internal self-test, consult the UTMC
publication

RTI Internal Self-Test Routine.

1.7 Power-up Master Reset

Reset the RTI by invoking either a hardware or software
master reset after power-up to place the device in a known
state. The master reset clears the decoder and encoder
registers, the command recognition logic, the control and
error logic (which includes the Status, Control and System
Registers), the data transfer logic, and the memory address
control logic. After reset, configure the device for operation
via a Control Register write.

Table 2. Parity Checking

STATE #

EXT TEST

EXT TST CH SEL A/B Function

TALEN/PARITY

Terminal Address Latch Enable. Active low
signal used to latch TA(4:0) into RTI. Internal
parity checker disabled.

Parity. Internal remote terminal address parity
checker enabled. TALEN/PARITY pin func-
tions as parity bit for TA(4:0) bus. Proper oper-
ation requires odd parity.

Terminal Address Latch Enable. Do not assert
EXT TST during reset, otherwise self-test is
invoked.

RTI-11

Perform a hardware reset by asserting the MRST input pin
for a minimum of 500ns. During reset negate the EXT TEST
pin (i.e., logic low); assertion of the EXT TEST pin forces
the RTI to enter the external self-test mode of operation.

Software reset the RTI by simultaneously applying a logic
zero to input pins CS, RD/WR, and CTRL while the least
significant bit of the address input bus is a logic one (ADDR
IN (0)=0).

1.8 Encoder and Decoder

The RTI interfaces directly to a bus transmitter/receiver via
the RTI Manchester II encoder/decoder. The UT1553B RTI
receives the command word from the MIL-STD-1553B bus
and processes it either by the primary or secondary decoder.
Each decode checks for the proper sync pulse and
Manchester waveform, edge skew, correct number of bits,
and parity. If the command is a receive command, the RTI
processes each incoming data word for correct word count
and contiguous data. If an invalid message error is detected,
the message error pin is asserted, the RTI ceases processing
the remainder (if any) of the message, and it then suppresses
status word transmission. Upon command validation
recognition, the external status outputs are enabled.
Reception of illegal commands does not suppress status
word transmission.

A timer precludes transmission greater than 730ms by the
assertion of fail-safe timer (TIMERON). This timer is reset
upon receipt of another valid command.

1.9 Illegal Command Decoding

The host has the option of asserting the ILL COMM pin to
illegalize a received command word. On receipt of an illegal
command, the RTI sets the message error bit in the status

word, sets the Message Error output, and sets the message
error latch in the System Register.

Use the following RTI outputs to externally decode an
illegal command, Mode Code or Subaddress indicator (MC/
SA), Mode Code or Subaddress bus MCSA(4:0), Command
Strobe (COMSTR), Broadcast (BRDCST), etc. (See figure
6 pages 11-12).

To illegalize a transmit command the ILL COMM pin is
asserted 3.3ms after STATUS goes to a logic one. Assertion
of the ILL COMM pin within 3.3ms allows the RTI to
respond with the Message Error bit of the outgoing status
word at a logic one.

For an illegal receive command, the ILL COMM pin is
asserted within 18.2ms after the COMSTR transitions to a
logic zero in order to suppress data words from being stored
(suppress DMARQ assertions). In addition, the ILL COMM
pin must be at a logic one throughout the reception of the
message until STATUS is asserted.

If the illegal command is mode code 2, 4, 5, 6, 7, or 18,
assert the ILL COMM pin within 664ns after Command
Strobe (COMSTR) transitions to logic zero. Asserting the
ILL COMM pin within the 664 nanoseconds inhibits the
mode code function.

The above timing conditions also apply when the host
externally decodes an illegal broadcast command. The host
must remove the illegal command condition so that the next
command is not falsely decoded as illegal. These
requirements are easily met if the COMSTR output is used
to qualify the ILL COMM input to the RTI.

COMMAND WORD

DATA WORD

STATUS WORD

DATA WORD

BIPHASE IN

BIPHASE OUT

RCV

COMSTR

STATUS

Figure 6a. Illegal Receive Command Decoding

ILL COMM

18.2

Note:

1. Illegal command condition; status word Message Error bit set to logic one, RTIMES ERR pin set to a logic one, RTI Status Register Message
Error bit set to logic one.

DMA Activity Suppressed

RTI-12

2.0 M

EMORY

XAMPLE

The RTI is capable of addressing 2048 x 16 of external
memory for message storage. The 2K memory space is
divided into two 1K pages and subdivided into 32 blocks of
32 x 16:

Page 1 (Receive): 32 blocks for receive messages

(32 x 16)

Page 2 (Transmit): 32 blocks for transmit messages

(32 x 16)

Address Decode

The RTI derives addresses (i.e., data pointers) for external
memory directly from the 11 least significant bits of the
command word. The address data pointer corresponds to
ADDR OUT (10:0) during RTI memory accesses.

T/R = ADDR OUT (10)
SUBADDRESS/MODE = ADDR OUT (9:5) WORD
COUNT/MODE CODE = ADDR OUT (4:0)

The T/R bit of the command word becomes the most
significant bit of the data pointer; the T/R bit serves to divide
the RAM into transmit and receive pages of 1K each. The
5-bit subaddress/mode field is used to select 1 of 32 possible
message storage blocks within the transmit or receive
message page. The 5-bit word count/mode code field acts
as a data pointer to select one of 32 locations within the
message storage block. Multiple word messages are stored
from top to bottom within the message storage block.

For mode commands, the address data pointer always
contains 00000 in the MC/SA field, regardless of whether
00000 or 11111 was received. Forcing the mode code field
to 00000 reserves the first message storage block on both
pages (receive and transmit) for mode code messages that
require data. The 5-bit mode code specifies which of the 32
locations within the message storage block to access.

COMMAND WORD

STATUS WORD

BIPHASE IN

BIPHASE OUT

XMIT

STATUS

Figure 6b. Illegal Transmit Command Decoding

ILL COMM

3.3

Note:
1. Illegal command condition; status word Message Error bit set to logic one, RTI MES ERR pin set to a logic one, RTI Status Register

Message Error bit set to logic one.

DMA Activity Suppressed

1.0

s (min)

COMSTR

BIPHASE IN

MC/SA

COMSTR

Figure 6c. Mode Code Command Decoding

ILL COMM

664ns

Note:
1. To illegalize mode codes 2, 4, 5, 6, 7, or 18 assert ILL COMM within 664ns of COMSTR's transition to logic zero. Asserting

the ILL COMM within 664ns inhibits the mode code function.

COMMAND WORD

RTI-13

For "wrap-around" applications (transmission of data
previously received), force the RTI to store and receive
messages on one memory page. To accomplish one-page

operation do not use the T/R output pin. Eliminating the T/
R limits the RTI access to only one page and the RTI will
not differentiate between receive and transmit pages.

Table 3. RTI Memory Map

1: Receive Memory Map

2: Transmit Memory map

Block #

Operation

Address Field (hex)

Block #

Operation

Address Field (hex)

Mode Code

000 to 01F

Mode Code

400 to 41F

Subaddress 1

020 to 03F

Subaddress 1

420 to 43F

Subaddress 2

040 to 05F

Subaddress 2

440 to 45F

Subaddress 3

060 to 07F

Subaddress 3

460 to 47F

Subaddress 4

080 to 09F

Subaddress 4

480 to 49F

Subaddress 5

0A0 to 0BF

Subaddress 5

4A0 to 4BF

Subaddress 6

0C0 to 0DF

Subaddress 6

4C0 to 4DF

Subaddress 7

0E0 to 0FF

Subaddress 7

4E0 to 4FF

Subaddress 8

100 to 11F

Subaddress 8

500 to 51F

Subaddress 9

120 to 13F

Subaddress 9

520 to 53F

Subaddress 10

140 to 15F

Subaddress 10

540 to 55F

Subaddress 11

160 to 17F

Subaddress 11

560 to 57F

Subaddress 12

180 to 19F

Subaddress 12

580 to 59F

Subaddress 13

1A0 to 1BF

Subaddress 13

5A0 to 5BF

Subaddress 14

1C0 to 1DF

Subaddress 14

5C0 to 5DF

Subaddress 15

1E0 to 1FF

Subaddress 15

5E0 to 5FF

Subaddress 16

200 to 21F

Subaddress 16

600 to 61F

Subaddress 17

220 to 23F

Subaddress 17

620 to 63F

Subaddress 18

240 to 25F

Subaddress 18

640 to 65F

Subaddress 19

260 to 27F

Subaddress 19

660 to 67F

Subaddress 20

280 to 29F

Subaddress 20

680 to 69F

Subaddress 21

2A0 to 2BF

Subaddress 21

6A0 to 6BF

Subaddress 22

2C0 to 2DF

Subaddress 22

6C0 to 6DF

Subaddress 23

2E0 to 2FF

Subaddress 23

6E0 to 6FF

Subaddress 24

300 to 31F

Subaddress 24

700 to 71F

Subaddress 25

320 to 33F

Subaddress 25

720 to 73F

Subaddress 26

340 to 35F

Subaddress 26

740 to 75F

Subaddress 27

360 to 37F

Subaddress 27

760 to 77F

Subaddress 28

380 to 39F

Subaddress 28

780 to 79F

Subaddress 29

3A0 to 3BF

Subaddress 29

7A0 to 7BF

Subaddress 30

3C0 to 3DF

Subaddress 30

7C0 to 7DF

Unused

3E0 to 3FF

Unused

7E0 to 7FF

Notes

1. Receive mode codes with data:

- Synchronize with data
- Selected Transmitter Shutdown (Illegal)
- Override Selected Transmitter Shutdown (Illegal)

2. Transmit mode codes with data:

- Transmit Vector Word
- Transmit Bit Word

RTI-14

3.0 P

DENTIFICATION

ESCRIPTION

RCS

RRD/RWR

RCV

XMIT

MC/SA

COMSTR

TIMERON

STATUS

MES ERR

UT1553B

RTI

POWER

GROUND

MRST

BIPHASE
OUT

BIPHASE
IN

BIPHASE IN A O

TERMINAL
ADDRESS

TA0

TA1

TA2

TA3

TA4

TALEN/PARITY

MODE/CODE
SUBADDRESS

MCSA0

MCSA1

MCSA2

MCSA3

MCSA4

STATUS
SIGNALS

BCEN

ILL COMM

RD/WR

CTRL

ADOEN

CONTROL
SIGNALS

ADDR IN 0
ADDR IN 1

ADDRESS BUS
ADDR IN(10:0)

DATA I/O 12
DATA I/O 13

DATA I/O 15

DATA I/O 0
DATA I/O 1
DATA I/O 2
DATA I/O 3
DATA I/O 4
DATA I/O 5
DATA I/O 6
DATA I/O 7
DATA I/O 8
DATA I/O 9
DATA I/O 10
DATA I/O 11

DATA BUS
DATA(15:0)

12MHz

BIPHASE IN A Z

BIPHASE IN B O

BIPHASE IN B Z

BIPHASE OUT A O

BIPHASE OUT A Z

BIPHASE OUT B O

BIPHASE OUT B Z

CLOCK

RESET

2MHz

CH A/B

DATA I/O 14

Figure 7. UT1553B RTI Pin Description

ADDR IN 2
ADDR IN 3
ADDR IN 4
ADDR IN 5
ADDR IN 6
ADDR IN 7
ADDR IN 8
ADDR IN 9
ADDR IN 10

DMARQ

MEMCK

DMA

EXT TEST
EXT TST CH SEL A/B

TEST

ADDR OUT 0
ADDR OUT 1
ADDR OUT 2
ADDR OUT 3
ADDR OUT 4
ADDR OUT 5
ADDR OUT 6
ADDR OUT 7
ADDR OUT 8
ADDR OUT 9
ADDR OUT 10

ADDRESS BUS
ADDR OUT
(10:0)

(K3)
(K1)
(H2)
(G3)
(G1)

(F3)

(E1)
(F2)
(D2)

(B1)
(B2)

(L1)
(J2)

(H1)
(G2)

(F1)
(E3)
(E2)

(D1)
(C1)
(C2)

(L9)

(K9)

(D11)

(F11)

(B10)

(K2)

(F10)

(K11)

(L7)

(G10)

(K7)

(E9)

(E10)

(C11)

(L3)
(L5)

(L6)

(J7)

(F9)

(E11)

(H11)

(B11)

(K6)

(J6)

(G11)

(D10)

(J5)

(L4)

(K4)

(L2)

(K5)

(B8)

(B7)

(A7)

(C6)

(B9)

(C10)

(A1)
(B3)
(A2)

(A3)

(B4)
(A4)
(C5)
(B5)
(A5)

(A6)
(C7)
(B6)
(A8)
(A9)

(A10)
(A11)

(J10)

(K10)

(G9)

(H10)

(L10)

(L11)

(K8)

(L8)

Note:
Pingrid array numbers are in parentheses. LCC pin numbers are not in parentheses.

15
20

13
9

74
73
72
71
70
69
68
67
66
65
63
61

59
57
55
53

11
10

6
4
2

84
82
80
78
76

29
31

48
47

12
42

BRDCST

36 (J11)

(J1)

RTI-15

Legend for TYPE and ACTIVE fields:

TI = TTL input
TUI = TTL input (pull-up)
TDI = TTL input (pull-down)

TO = TTL output
TTO = Three-state TTL output
TTB = Three-state TTL bidirectional

[ ] - Values in parentheses indicate the initialized state of
output pin.

DATA BUS

NAME

PIN NUMBER

TYPE

ACTIVE

DESCRIPTION

LCC

PGA

DATA I/O 15

53 A11 TTB --

Bit 15 (MSB) of the bidirectional Data
bus.

DATA I/O 14

55 A10 TTB --

Bit 14 of the bidirectional Data bus.

DATA I/O 13

57 A9 TTB

Bit 13 of the bidirectional Data bus.

DATA I/O 12

59 A8 TTB

Bit 12 of the bidirectional Data bus.

DATA I/O 11

61 B6 TTB

Bit 11 of the bidirectional Data bus.

DATA I/O 10

63 C7 TTB

Bit 10 of the bidirectional Data bus.

DATA I/O 9

65 A6 TTB

Bit 9 of the bidirectional Data bus.

DATA I/O 8

66 A5 TTB

Bit 8 of the bidirectional Data bus.

DATA I/O 7

67 B5 TTB

Bit 7 of the bidirectional Data bus.

DATA I/O 6

68 C5 TTB

Bit 6 of the bidirectional Data bus.

DATA I/O 5

69 A4 TTB

Bit 5 of the bidirectional Data bus.

DATA I/O 4

70 B4 TTB

Bit 4 of the bidirectional Data bus.

DATA I/O 3

71 A3 TTB

Bit 3 of the bidirectional Data bus.

DATA I/O 2

72 A2 TTB

Bit 2 of the bidirectional Data bus.

DATA I/O 1

73 B3 TTB

Bit 1 of the bidirectional Data bus.

DATA I/O 0

74 A1 TTB

Bit 0 (LSB) of the bidirectional Data bus.

INPUT ADDRESS BUS

NAME

PIN NUMBER

TYPE

ACTIVE

DESCRIPTION

LCC

PGA

ADDR IN 10

75 B2 TI --

Bit 10 (MSB) of the Address Input bus.

ADDR IN 9

77 B1 TI --

Bit 9 of the Address Input bus.

ADDR IN 8

79 D2 TI --

Bit 8 of the Address Input bus.

ADDR IN 7

F2 TI --

Bit 7 of the Address Input bus.

ADDR IN 6

83 E1 TI --

Bit 6 of the Address Input bus.

ADDR IN 5

1 F3 TI

Bit 5 of the Address Input bus.

ADDR IN 4

3 G1 TI --

Bit 4 of the Address Input bus.

ADDR IN 3

5 G3 TI --

Bit 3 of the Address Input bus.

ADDR IN 2

7 H2 TI --

Bit 2 of the Address Input bus.

ADDR IN 1

9 K1 TI --

Bit 1 of the Address Input bus.

ADDR IN 0

13 K3 TI --

Bit 0 (LSB) of the Address Input bus.

RTI-16

;

OUTPUT ADDRESS BUS

NAME

PIN NUMBER

TYPE

ACTIVE

DESCRIPTION

LCC

PGA

ADDR OUT 10

76 C2

TTO

Bit 10 (MSB) of the Address Output bus.

ADDR OUT 9

78 C1

TTO

Bit 9 of the Address Output bus.

ADDR OUT 8

80 D1

TTO

Bit 8 of the Address Output bus.

ADDR OUT 7

82 E2

TTO

Bit 7 of the Address Output bus.

ADDR OUT 6

84 E3

TTO

Bit 6 of the Address Output bus.

ADDR OUT 5

2 F1

TTO

Bit 5 of the Address Output bus.

ADDR OUT 4

4 G2

TTO

Bit 4 of the Address Output bus.

ADDR OUT 3

6 H1

TTO

Bit 3 of the Address Output bus.

ADDR OUT 2

8 J1

TTO

Bit 2 of the Address Output bus.

ADDR OUT 1

10 J2

TTO

Bit 1 of the Address Output bus.

ADDR OUT 0

11 L1

TTO

Bit 0 (LSB) of the Address Output bus.

REMOTE TERMINAL ADDRESS INPUTS

NAME

PIN NUMBER

TYPE

ACTIVE

DESCRIPTION

LCC

PGA

TA4

56 B9 TUI

Remote Terminal Address bit 4 (MSB).

TA3

58 B8 TUI

Remote Terminal Address bit 3.

TA2

60 B7 TUI

Remote Terminal Address bit 2.

TA1

62 A7 TUI

Remote Terminal Address bit 1.

TA0

C6 64 TUI

Remote Terminal Address bit 0.

TALEN/PARITY

C10

TUI

Remote Terminal Address Latch Enable/
Remote Terminal Parity Input. Function
of input is defined by he state of pin EXT
TEST and EXT TST CH SEL A/B. For
EXT TEST = 0, EXT TST CH SEL A/B
= 1, TALEN/PARITY must provide odd
parity for the Remote Terminal Address.
For all other states of EXT TEST and
EXT TST CH SEL A/B (i.e., 00, 10, 11)
TALEN/PARITY functions as an active
low address strobe.

RTI-17

MODE CODE/SUBADDRESS OUTPUTS

NAME

PIN NUMBER

DESCRIPTION

LCC

PGA

MC/SA

21 K6 TO --

Mode Code/Subaddress Indicator. If MC/SA is
low, it indicates that the most recent command
word is a mode code command. If MC/SA is
high, it indicates that the most recent command
word is for a subaddress. This output indicates
whether the mode code/subaddress outputs
(i.e., MCSA(4:0)) contain mode code or sub-
address information.

MCSA4 19

Mode Code/Subaddress 4. If MC/SA is low,
this pin represents the most significant bit of
the the most recent command word (the MSB
of the mode code). If MC/SA is high, this pin
represents the MSB of the subaddress.

MCSA3 18

Mode Code/Subaddress 3.

MCSA2 17

Mode Code/Subaddress 2.

MCSA1 16

Mode Code/Subaddress 1.

MCSA0 14

Mode Code/Subaddress 0. If MC/SA is low,
this pin represents the least significant bit of
the the most recent command word. If MC/SA
is high, this pin represents the LSB of the sub-
address

BIPHASE INPUTS

NAME

PIN NUMBER

DESCRIPTION

LCC

PGA

BIPHASE IN A Z

39 G9 TI --

Receiver - Channel A, Zero Input. Idle low
Manchester input from the 1553 bus transceiver.

BIPHASE IN A O

37 H10 TI --

Receiver - Channel A, One Input. This input is
thecomplement of BIPHASE IN A Z.

BIPHASE IN B Z

34 J10 TI --

Receiver - Channel B, Zero Input. Idle low
Manchester input from the 1553 bus transceiver.

BIPHASE IN B O

33 K10 TI --

Receiver - Channel B, One Input. This input is
the complement of BIPHASE IN B Z.

TYPE

ACTIVE

RTI-18

BIPHASE OUTPUTS

NAME

PIN NUMBER

DESCRIPTION

LCC

PGA

BIPHASE OUT A Z

28 K8 TO --

Transmitter - Channel A, Zero Output. This
Manchester-encoded data output is connected
to the 1553 bus transmitter input. The output is
idle low.

BIPHASE OUT A O

27 L8 TO --

Transmitter - Channel A, One Output. This
output is the complement of BIPHASE OUT
A Z. The output is idle low.

BIPHASE OUT B Z

30 L10 TO --

Transmitter - Channel B, Zero Output. This
Manchester-encoded data output is connected
to the 1553 bus transmitter. The output is idle
low.

BIPHASE OUT B O

32 L11 TO --

Transmitter - Channel B, One Output. This
output is the complement of BIPHASE OUT
B Z. The output is idle low.

MASTER RESET AND CLOCK

NAME

PIN NUMBER

DESCRIPTION

LCC

PGA

MRST

40 G10 TUI

Master Reset. Initializes all internal functions of the
RTI. MRST must be asserted 500 nanoseconds
before normal RTI operation. (500ns minimum).

12MHz

35 K11 TI --

12MHz Input Clock. This is the RTI system clock
that requires an accuracy greater than 0.01% with a
duty cycle from 50%

10%.

2MHz

TO --

2MHz Clock Output. This is a 2MHz output gener-
ated by the 12MHz input clock. This clock is
stopped when MRST is low.

POWER AND GROUND

NAME

PIN NUMBER

DESCRIPTION

LCC

PGA

54 B10

PWR

+5V

. Power supply must be +5V

10%.

12
42

F10

GND
GND

--
--

Ground reference. Zero V

logic ground.

TYPE

ACTIVE

TYPE

ACTIVE

TYPE

ACTIVE

RTI-19

CONTROL PINS

NAME

PIN NUMBER

TYPE

ACTIVE

DESCRIPTION

LCC

PGA

44 E9 TI AL

Chip Select. Active low input for host access of
transparent memory or the RTI internal registers. In
the transparent memory configuration CS is propa-
gated through the RTI to the RCS output.

CTRL

50 C11 TI AL

Control. The host processor uses the active low
CTRL input signal in conjunction with CS and RD/
WR to access the RTI internal registers. CTRL is
also used in the software assignment of the terminal
address and programmed reset.

ADOEN

15 L3 TI AL

Address Output Enable. When ADOEN is low the
Address Out bus (ADDR OUT (15:0)) is active. If
ADOEN = 1 the Address Out bus is high impedance.

RD/WR

46 E10 TI --

Read/Write. The host processor uses a high level on
this input in conjunction with CS and CTRL to read
the RTI internal registers. A low level on this input is
used in conjunction with CS and CTRL to write to
internal RTI registers. In the transparent memory
configuration RD/WR is propagated through the RTI
to the RRD/RWR output.

BCEN

25 K7 TUI

Broadcast Enable. Active low input enables broad-
cast commands.

ILL COMM

20 L5 TDI

Illegal Command. The host processor uses the ILL
COMM input to inform the RTI that the present
command is illegal. ILL COMM is used in conjunc-
tion with MCSA(4:0) and MC/SA to define system
dependent illegal commands.

RTI-20

STATUS OUTPUTS

NAME

PIN NUMBER

TYPE

ACTIVE

DESCRIPTION

LCC

PGA

RCS

43 F9 TO AL

RAM Chip Select. Active low output used to
enable memory for access.

RRD/RWR

45 E11 TO --

RAM Read/Write. High output enables memory
read, low output enables memory write, used in
conjunction with RCS). Normally high output.

COMSTR

22 J6 TO AL

Command Strobe. COMSTR is an active low
output of 500ns duration identifying receipt of a
valid command.

TIMERON

41 G11 TO AL

Fail-safe Timer. The TIMERON output pulses
low for 730ms when the RTI begins transmit-
ting (i.e., rising edge of STATUS) to provide a
fail-safe timer meeting the requirements of
MIL-STD-1553B. This pulse is reset when
COMSTR goes low or during Master Reset. in
the external self-test mode TIMERON does not
recognize COMSTR and resets after 730ms.

MES ERR

49 D10 TO

Message Error. The active high MES ERR out-
put signals that the Message Error bit in the Sta-
tus Register has been set due to receipt of an
invalid command or an error during message
sequence. MES ERR will reset to logic zero on
receipt of next valid command.

CH A/B

26 L6 TO --

Channel A/B. Output identifying the channel on
which the most recent valid command was
received. Channel A = 1, Channel B = 0.

XMIT

38 H11 TO AL

Transmit. Active low output identifies a
transmit command message transfer by the RTI
is in progress.

RCV

51 B11 TO AL

Receive. Active low output identifies a receive
command message transfer by the RTI is in
progress.

BRDCST

36 J11 TO

Broadcast. BRDCST is an active low output
that identifies receipt of a valid broadcast com-
mand.

STATUS

Status. Active high output pulse indicating that
the RTI is in the process of transmitting a status
word.

RTI-21

4.0 O

PERATING

ONDITIONS

ABSOLUTE MAXIMUM RATINGS

(referenced to VSS)

Recommended Operating Conditions

BUS ARBITRATION

NAME

PIN NUMBER

TYPE

ACTIVE

DESCRIPTION

LCC

PGA

DMARQ

47 F11 TO AH

Direct Memory Access Request. Active high
output requesting RTI access to memory.

MEMCK

48 D11 TI AL

Memory Clock (DMA Grant). Active low input
signaling the RTI that a memory access is
granted. Internal to the RTI, receipt of MEMCK
generates RAM chip select and RAM read/write
signals.

EXT TST

29 L9 TDI --

External Self-test Enable. Multi-function input
pin. In self-test mode forcing this pin high
allows the monitoring of self-test activity at the
bus stub. When the RTI is not in self-test this
pin defines the function of TALEN/PARITY.

EXT TST CH SEL
A/B

31 K9 TUI --

External Self-test Channel Select. A/B Multi-
function input pin. In self-test mode forcing this
pin high selects the channel on which the self-
test is performed (Channel A = 1, Channel B =
0). When the RTI is not in self-test this pin
defines the function of TALEN/PARITY.

SYMBOL

PARAMETER

LIMITS

UNIT

DC supply voltage

-0.3 to +7.0

Voltage on any pin

-0.3 to V

+0.3

DC input current

STG

Storage temperature

-65 to +150

Maximum power dissipation

300

Maximum junction temperature

+175

Thermal resistance, junction-to-case

C/W

Note:
1. Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, and functional

operation of the device at these or any other conditions beyond limits indicated in the operational sections of this specification is not
recommended. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

SYMBOL

PARAMETER

LIMITS

UNIT

DC supply voltage

4.5 to 5.5

DC input voltage

0 to V

Temperature range

-55 to +125

Operating frequency

.01%

MHz

RTI-22

5.0 DC E

LECTRICAL

HARACTERISTICS

(VDD = 5.0V

10%; -55

C < TC < +125

SYMBOL

PARAMETER

CONDITION

MINIMUM

MAXIMUM

UNIT

Low-level input voltage

0.8

High-level input voltage

2.0

Input leakage current
TTL inputs
Inputs with pull-down resistors
Inputs with pull-up resistors

= V

or V

= V

-10
110
-2750

10
2750
-110

Low-level output voltage

= 4mA

0.4

High-level output voltage

= -400

2.4

Three-state output
leakage current

= V

or V

-10

+10

Short-circuit output current

1, 2

= 5.5V, V

= V

= 5.5V, V

= 0V

-90

mA
mA

Input capacitance

= 1MHz @ 0V

OUT

Output capacitance

= 1MHz @ 0V

Bidirect I/O capacitance

= 1MHz @ 0V

Average operating current

1, 4

= 12MHz, CL = 50pF

Quiescent current

Note 5

1.5

Notes:
1. Supplied as a design limit but not guaranteed or tested.
2. Not more than one output may be shorted at a time for a maximum duration of one second.
3. Measured only for initial qualification, and after process or design changes that could affect input/output capacitance.
4. Includes current through input pull-ups. Instantaneous surge currents on the order of 1 ampere can occur during output switching.

Voltage supply should be adequately sized and decoupled to handle a large surge current.

5. All inputs with internal pull-ups or pull-downs should be left open circuit. All other inputs tied high or low.

SYNC

BIT TIMES

COMMAND

WORD

DATA WORD

STATUS WORD

SYNC

REMOTE TERMINAL

ADDRESS

SUBADDRESS/MODE

CODE

T/R

DATA WORD COUNT/

MODE CODE

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

DATA

Figure 8. MIL-STD-1553B Word Formats

REMOTE TERMINAL

ADDRESS

MESSA

GE ERR

INSTR

UMENT

TION

SER

VICE REQ

UEST

RESERVED

ADCAST COMMAND RECEIVED

USY

SUBSYSTEM FLA

YNAMIC B

US CONTR

OL A

CCEPT

ANCE

TERMINAL FLA

ARITY

RTI-23

6.0 AC E

LECTRICAL

HARACTERISTICS

3, 4

(Over recommended operating conditions)

to data valid

to high Z

to response

INPUT

to high Z

to data valid

INPUT

to response

PARAMETER

SYMBOL

BUS

OUTPUT

OUT-OF-PHASE

OUTPUT

IN-PHASE

INPUT

Notes:
1. Timing measurements made at (V

MIN + V

MAX)/2.

2. Timing measurements made at (V

MAX + V

MIN)/2.

3. Based on 50pF load.

MIN

MAX

MIN

MAX

MIN

MAX

MIN

MAX

MIN

MAX

Figure 9a. Typical Timing Measurements

90%

Figure 9b. AC Test Loads and Input Waveforms

Note:
30pF including scope probe and test socket

Input Pulses

10%

90%

< 2ns

50pF

REF

(source)

REF

(sink)

RTI-24

DMARQ

MEMCK

RCS

RRD/RWR

DATA BUS

ADDR OUT BUS

10a

SYMBOL

PARAMETER

MINIMUM

MAXIMUM

UNITS

ADDR OUT valid to DMARQ active

DMARQ active to MEMCK active

2, 3

MEMCK active to RCS active

MEMCK inactive to RCS inactive

MEMCK active to RRD/RWR active

MEMCK inactive to RRD/RWR inactive

MEMCK pulse width

1, 2, 4

MEMCK active to DATA bus valid

MEMCK inactive to DATA bus high

impedance

883

992

115

101

Notes:
1. Allows a 20ns data valid set-up time before RCS and RRD/RWR go high.
2. The sum t

+ t

must not exceed 18.8ms.

3. Supplied as a design limit, but not guaranteed or tested.
4. Guaranteed by test.

Figure 10. RTI Memory Write

10a

10b

10e

10c

10h

10f

10d

10i

10g

10b

10c

10d

10e

10f

10g

10h

10i

RTI-25

DMARQ

MEMCK

RCS

DATA BUS

ADDR OUT BUS

SYMBOL

PARAMETER

MINIMUM

MAXIMUM

UNITS

ADDR OUT valid to DMARQ active

DMARQ active to MEMCK active

MEMCK active to RCS active

MEMCK inactive to RCS inactive

MEMCK pulse width

1, 2, 4

Input DATA valid to MEMCK inactive

Input DATA valid after RCS inactive

883

992

Notes:
1. Allows a 20ns data valid set-up time before RCS and RRD/RWR go high.
2. The sum t

+ t

must not exceed 18.8ms.

3. Supplied as a design limit, but not guaranteed or tested.
4. Guaranteed by test.

Figure 11. RTI Memory Read

11a

14.9

18.3

DMARQ active to MEMCK inactive

11h

11b

11e

11c

11f

11d

11g

11a

11b

11c

11d

11e

11f

11g

11h

RTI-29

RCS

ADOEN

ADDR IN BUS

Figure 15. RTI Propagation Delays

ADDR OUT BUS

MEMCK

SYM-

PARAMETER

MINIMUM

MAXIMUM

UNITS

CS active to RCS active

CS negation to RCS negation

RD/WR active to RRD/RWR active

RD/WR negation to RRD/RWR negation

ADOEN active to ADDR OUT active

CS active to ADDR OUT valid

ADDR IN valid to ADDR OUT valid

ADOEN negation to ADDR OUT high

impedance

Note:
1. Supplied as a design limit, but not guaranteed or tested.
2. Guaranteed by test.

15a

RD/WR

RRD/RWR

CS active to MEMCK active

(MEMCK not recognized)

CS negation to MEMCK active

(MEMCK recognized)

15a

15e

15i

15c

15f

15g

15h

15j

15dv

15b

15c

15d

15e

15f

15g

15h

15i

15j

RTI-30

COMSTR

Figure 16. Command Word Validation

16a

BIPHASE IN

RCV

XMIT

CH A/B

COMMAND

BRDCST

MC/SA

MCSA(4:0)

ADDR OUT

MESS ERR

SYMBOL

PARAMETER

MINIMUM

MAXIMUM

UNITS

Command word parity to COMSTR and

RCV or XMIT active

COMSTR pulse width

Command word parity to CH A/B valid

Status output signals valid to COMSTR

active

2, 4

MES ERR reset after COMSTR active

3.67

430

745

3.58

2.58

2.66

750

Notes:
1. ADOEN is asserted (i.e., logic low).
2. Status signals include BRDCST, MC/SA, MCSA(4:0), and ADDR OUT.
3. Measured from mid-bit parity crossing.
4. Supplied as a design limit, but not guaranteed or tested.

499

502

16b

16c

16d

16e

16a

16b

16c

16d

16e

RTI-31

Figure 17. Receive Command Message Processing

BIPHASE IN

DMARQ

STATUS

DATA

SYMBOL

PARAMETER

MINIMUM

MAXIMUM

UNITS

Data word parity bit to status word

response

1, 3

Data word parity bit to DMARQ active

2, 3

STATUS active to BIPHASE OUT active

STATUS pulse width

9.37

4.98

4.48

8.80

3.58

3.68

Notes:
1. Measured from last data word mid-bit parity crossing.
2. Measured from transmitted status word sync field mid-bit crossing.
3. Supplied as a design limit, but not guaranteed or tested.

BIPHASE OUT

STATUS

SYNC

17a

RCV

1.24

1.25

ADDR OUT

ADDR OUT valid before DMARQ (H)

0.90

17b

17c

17d

17e

17a

17b

17c

17d

17e

RTI-33

Figure 19. Mode Command Message Processing

BIPHASE IN

DATA/CMD

SYMBOL

PARAMETER

MINIMUM

MAXIMUM

UNITS

Response time BIPHASE IN to BI-

PHASE OUT

Command word parity bit to COMSTR asser-

tion

3.67

3.58

8.80

9.37

Notes:
1. Measured from data or command word mid-bit parity crossing.
2. Measured from transmitted status word sync field mid-bit crossing.
* Supplied as a design limit but not guaranteed or tested.

BIPHASE

19a

MES ERR

19g

19a

19b

STATUS

SYNC

19c

19b

19e

19f

19d

STATUS active to BIPHASE OUT active

1.24

1.25

* t

19c

STATUS pulse width

4.48

4.98

* t

19d

Command word parity bit to XMIT assertion

3.58

3.67

* t

19e

XMIT pulse width for mode code reception

1.00

* t

19f

Command word parity bit to MES ERR as-

sertion

6.57

6.68

* t

19g

COMSTR

STATUS

XMIT

RTI-38

ACKAGE

UTLINE

RAWINGS

Figure 26a. UT1553B RTI Pingrid Array Configuration

(Bottom View)

ADDR OUT 5

ADDR IN 7

ADDR IN 5

RCS

F10 V

F11 DMARQ

ADDR IN 4

ADDR OUT 4

ADDR IN 3

BIPHASE IN A Z

G10 MRST
G11 TIMERON

ADDR OUT 3

ADDR IN 2

H10

BIPHASE IN A O

H11 XMIT

ADDR OUT 9

ADDR OUT 10

DATA I/O 6

TA 0

DATA I/O 10

C10 TALEN/PARITY
C11 CTRL

ADDR OUT 8

ADDR IN 8

D10 MES

ERR

D11 MEMCK

ADDR IN 6

ADDR OUT 7

ADDR OUT 6

E9 CS
E10 RD/WR
E11 RRD/RWR

DATA I/O 0

A2 DATA I/O 2
A3 DATA I/O 3
A4 DATA I/O 5
A5 DATA I/O 8
A6 DATA I/O 9
A7 TA 1
A8 DATA I/O 12
A9 DATA I/O 13
A10 DATA I/O 14
A11 DATA I/O 15

B1 ADDR IN 9
B2 ADDR IN 10
B3 DATA I/O 1
B4 DATA I/O 4
B5 DATA I/O 7
B6 DATA I/O 11
B7 TA 2
B8 TA 3
B9 TA 4
B10 V

B11 RCV

ADDR OUT 2

ADDR OUT 1

J5 MCSA

J6 COMSTR
J7 STATUS
J10

BIPHASE IN B Z

J11

BRDCST

ADDR IN 1

ADDR IN 0

MCSA 1

MCSA 4

MC/SA

BCEN

BIPHASE OUT A Z

EXT TST CH SEl A/B

K10

BIPHASE IN B O

K11 12MHz

ADDR OUT 0

L2 MCSA

L3 ADOEN
L4

MCSA 2

L5 ILL

COMM

CH A/B

L7 2MHz
L8

BIPHASE OUT A

EXT TEST

L10

BIPHASE OUT B

L11 BIPHASE OUT B

RTI-39

ADDR IN 5

ADDR OUT 5

ADDR IN 4

ADDR OUT 4

ADDR IN 3

ADDR OUT 3

ADDR IN 2

ADDR OUT 2

ADDR IN 1

ADDR OUT 1

ADDR OUT 0

ADDR IN 0

MCSA0

ADOEN

MCSA1

MCSA2

MCSA3

DATA I/O 1

DATA I/O 0

ADDR IN 10

ADDR OUT 10

ADDR IN 9

ADDR OUT 9

ADDR IN 8

ADDR OUT 8

ADDR IN 7

ADDR OUT 7

ADDR IN 6

ADDR OUT 6

MCSA 4

ILL COMM

MC/SA

COMSTR

STATUS

2MHz

BCEN

CH A/B

BIPHASE OUT A O

BIPHASE OUT A Z

EXT TEST

BIPHASE OUT B Z

EXT TST CH SEL A/B

BIPHASE OUT B O

BIPHASE IN B O

BIPHASE IN B Z

12MHz

36 BRDCST

BIPHASE IN A O

38 XMIT
39

BIPHASE IN A Z

40 MRST
41

TIMERON

RCS

RRD/RWR

RD/WR

DMARQ

MEMCK

MES ERR

50 CTRL
51

RCV

52 TALEN/PARITY
53

DATA I/O 15

DATA I/O 14

TA4

DATA I/O 13

TA3

DATA I/O 12

TA2

DATA I/O 11

62 TA1
63

DATA I/O 10

TA0

DATA I/O 9

DATA I/O 8

DATA I/O 7

DATA I/O 6

DATA I/O 5

DATA I/O 4

DATA I/O 3

DATA I/O 2

11 10

84 83 82 81 80 79 78 77 76 75

Figure 26b. UT1553B RTI Chip Carrier Configuration

(Top View)

Document Outline

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: UT1553BRTIGPA

Document Outline

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: UT1553BRTIGPA