UTRON

UT621024

Rev. 1.5

128K X 8 BIT LOW POWER CMOS SRAM

________________________________________________________________________________________________
UTRON TECHNOLOGY INC. P80036
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919

FEATURES

Access time : 35/55/70ns (max.)

Low power consumption :

Operating : 60/50/40 mA (typical)

Standby : 2

µA (typical) L-version

µA (typical) LL-version

Single 5V power supply
All inputs and outputs TTL compatible
Fully static operation
Three state outputs
Data retention voltage : 2V (min.)
Package : 32-pin 600 mil PDIP

32-pin 450 mil SOP
32-pin 8mmx20mm TSOP-1
32-pin 8mmx13.4mm STSOP

FUNCTIONAL BLOCK DIAGRAM

COLUMN I/O

COLUMN DECODER

ROW

DECODER

I/O

CONTROL

LOGIC

CONTROL

A15

I/O1

VSS

VCC

I/O8

.
.

. .

A13

A11

A2 A1 A0

A10

.
.
.

MEMORY ARRAY

1024 ROWS × 1024 COLUMNS

A14

A12

A16

CE2

PIN DESCRIPTION

SYMBOL DESCRIPTION
A0 - A16

Address Inputs

I/O1 - I/O8

Data Inputs/Outputs

CE ,CE2

Chip enable 1,2 Inputs

Write Enable Input

Output Enable Input

Power

Supply

Ground

NC No

Connection

GENERAL DESCRIPTION

The UT621024 is a 1,048,576-bit low power
CMOS static random access memory
organized as 131,072 words by 8 bits. It is
fabricated using high performance, high
reliability CMOS technology.

The UT621024 is designed for low power
application. It is particularly well suited for
battery back-up nonvolatile memory
application.

The UT621024 operates from a single 5V
power supply and all inputs and outputs are
fully TTL compatible.

PIN CONFIGURATION

A12

A7
A6

I/O1

I/O2

CE2

A11

A10

I/O8

I/O7

I/O6

I/O5

I/O4

I/O3

Vss

UT621024

PDIP / SOP

A13

A14

A16

Vcc

A15

TSOP-I/STSOP

I/O4

A11

A13

I/O3

A10

A14

A12

Vcc

I/O8

I/O7

I/O6

I/O5

Vss

I/O2

I/O1

UT621024

CE2

A15

A16

UTRON

UT621024

Rev. 1.5

128K X 8 BIT LOW POWER CMOS SRAM

ABSOLUTE MAXIMUM RATINGS*

PARAMETER

SYMBOL

RATING

UNIT

Terminal Voltage with Respect to Vss

TERM

-0.5 to +7.0

Operating Temperature

0 to +70

Storage Temperature

STG

-65 to +150

Power Dissipation

DC Output Current

OUT

Soldering Temperature (under 10 sec)

solder

260

*Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This
is a stress rating only and functional operation of the device or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to the absolute maximum rating conditions for extended
period may affect device reliability.

TRUTH TABLE

MODE

CE2 OE

I/O OPERATION

SUPPLY CURRENT

Standby

High - Z

SB1

Standby

High -Z

SB1

Output Disable

High - Z

Read

OUT

Write

Note: H = V

, L=V

, X = Don't care.

DC ELECTRICAL CHARACTERISTICS (V

= 5V± 10%, T

= 0 to 70)

PARAMETER

SYMBOL TEST CONDITION

MIN. TYP. MAX.

UNIT

Input High Voltage

2.2 - V

+0.5 V

Input Low Voltage

- 0.5 -

0.8

Input Leakage Current

- 1

µA

Output Leakage Current

I/O

CE =V

or CE2 = V

OE = V

or WE = V

- 1

µA

Output High Voltage

= - 1mA

2.4

Output Low Voltage

= 4mA

0.4

Cycle time=min, 100% duty,

CE =V

, CE2 = V

I/O

= 0mA

-35
-55
-70

-
-
-

60
50
40

100

85
70

mA
mA
mA

Average Operating
Power Supply Courrent

CC1

Cycle time=1µs,100% duty,I

I/O

=0mA

CE 0.2V,CE2V

-0.2V,

other pins at 0.2V or V

-0.2V,

- - 10 mA

CE =V

or CE2 = V

other pins at 0.2V or V

-0.2V,

- - 3 mA

100

- L

40*

µA

Standby Power

Supply Current

SB1

CE V

-0.2V or

CE20.2V

other pins at 0.2V or V

-0.2V, -

- 1

15*

µA

*Those parameters are for reference only under 50

UTRON

UT621024

Rev. 1.5

128K X 8 BIT LOW POWER CMOS SRAM

_________________________________________________________________________________________________
UTRON TECHNOLOGY INC. P80036
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919

CAPACITANCE (T

=25, f=1.0MHz)

PARAMETER

SYMBOL

MIN.

MAX.

UNIT

Input Capacitance

Input/Output Capacitance

I/O

Note : These parameters are guaranteed by device characterization, but not production tested.

AC TEST CONDITIONS

Input Pulse Levels

0V to 3.0V

Input Rise and Fall Times

5ns

Input and Output Timing Reference Levels

1.5V

Output Load

=100pF, I

=-1mA/4mA

AC ELECTRICAL CHARACTERISTICS (V

= 5V± 10% , T

= 0 to 70)

(1) READ CYCLE
PARAMETER

SYMBOL

UT621024-35 UT621024-55 UT621024-70 UNIT

MIN. MAX. MIN. MAX. MIN. MAX.

Read Cycle Time

35 - 55 - 70 - ns

Address Access Time

- 35 - 55 - 70 ns

Chip Enable Access Time

ACE1

, t

ACE2

- 35 - 55 - 70 ns

Output Enable Access Time

- 25 - 30 - 35 ns

Chip Enable to Output in Low-Z

CLZ1

*, t

CLZ2

10 - 10 - 10 - ns

Output Enable to Output in Low-Z t

OLZ

5 - 5 - 5 - ns

Chip Disable to Output in High-Z

CHZ1

*, t

CHZ2

- 25 - 30 - 35 ns

Output Disable to Output in High-Z t

OHZ

- 25 - 30 - 35 ns

Output Hold from Address Change t

5 - 5 - 5 - ns

(2) WRITE CYCLE

PARAMETER

SYMBOL UT621024-

UT621024-55

UT621024-70 UNIT

MIN. MAX. MIN. MAX. MIN. MAX.

Write Cycle Time

35 - 55 - 70 -

Address Valid to End of Write

30 - 50 - 60 -

Chip Enable to End of Write

CW1

, t

CW2

30 - 50 - 60 -

Address Set-up Time

Write Pulse Width

25 - 40 - 45 -

Write Recovery Time

Data to Write Time Overlap

20 - 25 - 30 -

Data Hold from End of Write-Time t

Output Active from End of Write

Write to Output in High-Z

WHZ

- 15 - 20 - 25

*These parameters are guaranteed by device characterization, but not production tested.

UTRON

UT621024

Rev. 1.5

128K X 8 BIT LOW POWER CMOS SRAM

TIMING WAVEFORMS

READ CYCLE 1 (Address Controlled)

(1,2,4)

Address

DOUT

Data Valid

READ CYCLE 2 (

CE , CE2 and OE Controlled)

(1,3,5,6)

Notes :
1.

is HIGH for read cycle.

2. Device is continuously selected

CE =V

and CE2=V

IH.

3. Address must be valid prior to or coincident with

CE and CE2 transition; otherwise t

is the limiting parameter.

4. OE is low.
5. t

CLZ1

, t

CLZ2

, t

OLZ

, t

CHZ1

, t

CHZ2

and t

OHZ

are specified with C

=5pF. Transition is measured ± 500mV from steady state.

6. At any given temperature and voltage condition, t

CHZ1

is less than t

CLZ1

, t

CHZ2

is less than t

CLZ2

, t

OHZ

is less than t

OLZ.

ACE1

ACE2

OLZ

CLZ1

CLZ2

High-Z

CHZ1

CHZ2

OHZ

Data Valid

High-Z

Address

CE2

OUT

UTRON

UT621024

Rev. 1.5

128K X 8 BIT LOW POWER CMOS SRAM

WRITE CYCLE 1 ( WE Controlled)

(1,2,3,5)

Address

OUT

High-Z

Data Valid

CE2

CW2

CW1

WHZ

(4)

WRITE CYCLE 2 (

CE and CE2 Controlled)

(1,2,5)

Address

OUT

High-Z

(4)

Data Valid

CE2

CW1

CW2

WHZ

Notes :
1.

CE must be HIGH or CE2 must be LOW during all address transitions.

2. A write occurs during the overlap of a low

CE , a high CE2 and a low

3. During a

controlled with write cycle with OE LOW, t

must be greater than t

WHZ

to allow the I/O drivers

to turn off and data to be placed on the bus.
4. During this period, I/O pins are in the output state, and input singals must not be applied.
5. If

the 1

CE LOW transition occurs simultaneously with or after

LOW transition, the outputs remain in a high

impedance state.
6. t

and t

WHZ

are specified with C

=5pF. Transition is measured ± 500mV from steady state.

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