UTRON

UT62256C

Rev. 1.0

32K X 8 BIT LOW POWER CMOS SRAM

____________________________________________________________________________________________
UTRON TECHNOLOGY INC. P80027
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919

FEATURES

Access time : 35/70ns (max.)
Low power consumption:

Operating : 40/30 mA (typical.)

Standby : 3mA (typical) normal

2uA (typical) L-version
1uA (typical) LL-version

Single 5V power supply
All inputs and outputs are TTL compatible
Fully static operation
Three state outputs
Data retention voltage : 2V (min.)
Package : 28-pin 600 mil PDIP

28-pin 330 mil SOP

28-pin 8mmx13.4mm STSOP

FUNCTIONAL BLOCK DIAGRAM

COLUMN I/O

COLUMN DECODER

ROW

DECODER

I/O

CONTROL

LOGIC

CONTROL

I/O1

VSS

VCC

I/O8

.
.

. .

A14

A13

A12
A7

A5
A8

A2 A1 A0

A10

.
.
.

MEMORY ARRAY

512 ROWS × 512 COLUMNS

A11

PIN DESCRIPTION

SYMBOL DESCRIPTION

A0 - A14

Address Inputs

I/O1 - I/O8

Data Inputs/Outputs

Chip Enable Input

Write Enable Input

Output Enable Input

Power

Supply

Ground

GENERAL DESCRIPTION

The UT62256C is a 262,144-bit low power
CMOS static random access memory
organized as 32,768 words by 8 bits. It is
fabricated using high performance, high
reliability CMOS technology.

The UT62256C is designed for high-speed
and low power application. It is particularly
well suited for battery back-up nonvolatile
memory application.

The UT62256C operates from a single 5V
power supply and all inputs and outputs are
fully TTL compatible

PIN CONFIGURATION

A12

I/O1

I/O2

Vcc

A11

A10

I/O8

I/O7

I/O6

I/O5

I/O4

I/O3

Vss

UT62256C

PDIP/SOP

A13

A14

I/O4

A11

A13

I/O3

A10

A14

A12

Vcc

I/O8

I/O7

I/O6

I/O5

Vss

I/O2

I/O1

UT62256C

STSOP

UTRON

UT62256C

Rev. 1.0

32K X 8 BIT LOW POWER CMOS SRAM

ABSOLUTE MAXIMUM RATINGS*

PARAMETER

SYMBOL

RATING

UNIT

Terminal Voltage with Respect to V

TERM

-0.5 to +7.0

Operating Temperature

0 to +70

Storage Temperature

STG

-65 to +150

Power Dissipation

1 W

DC Output Current

OUT

50 mA

Soldering Temperature (under 10 sec0

Tsolder

260

*Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device.
This is a stress rating only and functional operation of the device or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to the absolute maximum rating conditions for
extended period may affect device reliability.

TRUTH TABLE

MODE

I/O OPERATION

SUPPLY CURRENT

Standby H

High - Z

ISB, ISB1

Output Disable

High - Z

Read L

OUT

Write L

Note: H = V

, L=V

, X = Don't care.

DC ELECTRICAL CHARACTERISTICS (VCC = 5V±10%, TA = 0 to 70)

PARAMETER

SYMBOL

TEST CONDITION

MIN. TYP. MAX. UNIT

Input High Voltage

2.2 - VCC+0.5 V

Input Low Voltage

0.5 -

0.8 V

Input Leakage Current

µA

Output Leakage
Current

I/O

CE =V

or OE = V

= V

µA

Output High Voltage

= - 1mA

2.4

Output Low Voltage

= 4mA

0.4

- 35

CE = V

I/O

= 0mA ,Cycle=Min. - 70

1 Tcycle

=500ns

- - 20 mA

Operating Power

Supply Current

CE = 0.2V; I

I/O

= 0mA

other pins at 0.2V or
V

-0.2V

Tcycle
=1ms

- - 10 mA

CE =V

1 10 mA

SB1

CE V

-0.2V

normal -

0.3 5 mA

CE =V

-L/-LL - - 3 mA

SB1

CE V

-0.2V

-L - 2 100 µA

Standby Power
Supply Current

-LL

µA

UTRON

UT62256C

Rev. 1.0

32K X 8 BIT LOW POWER CMOS SRAM

_____________________________________________________________________________________________
UTRON TECHNOLOGY INC. P80027
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919

CAPACITANCE (TA=25, f=1.0MHz)

PARAMETER

SYMBOL

MIN.

MAX

UNIT

Input Capacitance

8 pF

Input/Output Capacitance

I/O

10 pF

Note : These parameters are guaranteed by device characterization, but not production tested.

AC TEST CONDITIONS

Input Pulse Levels

0V to 3.0V

Input Rise and Fall Times

5ns

Input and Output Timing Reference Levels

1.5V

Output Load

= 100pF, I

= -1mA/4mA

AC ELECTRICAL CHARACTERISTICS

(VCC = 5V±10% , TA = 0 to 70)

(1) READ CYCLE

PARAMETER

SYMBOL

UT62256C-35 UT62256C-70 UNIT

MIN. MAX. MIN. MAX.

Read Cycle Time

35 - 70 - ns

Address Access Time

- 35 - 70

Chip Enable Access Time

ACE

- 35 - 70

Output Enable Access Time

- 25 - 35

Chip Enable to Output in Low Z

CLZ*

10 - 10 - ns

Output Enable to Output in Low Z

OLZ*

5 - 5 -

Chip Disable to Output in High Z

CHZ*

- 25 - 35

Output Disable to Output in High Z

OHZ*

- 25 - 35

Output Hold from Address Change

5 - 5 -

(2) WRITE CYCLE

PARAMETER

SYMBOL

UT62256C-35 UT62256C-70 UNIT

MIN. MAX. MIN. MAX.

Write Cycle Time

35 - 70 - ns

Address Valid to End of Write

30 - 60 - ns

Chip Enable to End of Write

30 - 60 - ns

Address Set-up Time

Write Pulse Width

25 - 50 - ns

Write Recovery Time

Data to Write Time Overlap

20 - 30 - ns

Data Hold from End of Write Time

Output Active from End of Write

OW*

5 - 5 -

Write to Output in High Z

WHZ*

- 15 - 25

*These parameters are guaranteed by device characterization, but not production tested.

UTRON

UT62256C

Rev. 1.0

32K X 8 BIT LOW POWER CMOS SRAM

TIMING WAVEFORMS

READ CYCLE 1

(Address Controlled)

(1,2,4)

Address

DOUT

Data Valid

READ CYCLE 2

(

and

Controlled)

(1,3,5,6)

OUT

Address

ACE

CLZ

OLZ

High-z

OHZ

CHZ

Data valid

High-Z

Notes :
1.

is HIGH for read cycle.

2. Device is continuously selected CE =V

IL.

3. Address must be valid prior to or coincident with CE transition; otherwise t

is the limiting parameter.

4. OE is LOW.
5. t

CLZ

, t

OLZ

, t

CHZ

and t

OHZ

are specified with C

= 5pF. Transition is measured ±500mV from steady state.

6. At any given temperature and voltage condition, t

CHZ

is less than t

CLZ

, t

OHZ

is less than t

OLZ.

UTRON

UT62256C

Rev. 1.0

32K X 8 BIT LOW POWER CMOS SRAM

WRITE CYCLE 1

(

Controlled)

(1,2,3,5)

OUT

WHZ

(4)

High-Z

(4)

Address

Data Valid

WRITE CYCLE 2

(

Controlled)

(1,2,5)

High-Z

(4)

Data Valid

OUT

WHZ

Address

Notes :
1.

or CE must be HIGH during all address transitions.

2. A write occurs during the overlap of a low CE and a low

3. During a

controlled with write cycle with OE LOW, t

must be greater than t

WHZ

to allow the drivers

to turn off and data to be placed on the bus.

4. During this period, I/O pins are in the output state, and input signals must not be applied.

5. If the

LOW

transition occurs simultaneously with or after

LOW

transition, the

outputs remain in a high impedance state.

6. t

and t

WHZ

are specified with C

= 5pF. Transition is measured ±500mV from steady state.

UTRON

UT62256C

Rev. 1.0

32K X 8 BIT LOW POWER CMOS SRAM

DATA RETENTION CHARACTERISTICS (TA = 0 to 70)

PARAMETER SYMBOL

TEST

CONDITION

MIN.

TYP.

MAX.

UNIT

Vcc for Data Retention

CE V

-0.2V

2.0

5.5

Data Retention Current

Vcc=3V

- L

50 µA

CE V

-0.2V

- LL -

0.5

20 µA

Chip Disable to Data

CDR

See Data Retention

Retention Time

Waveforms (below)

Recovery Time

RC*

- - ns

RC*

= Read Cycle Time

DATA RETENTION WAVEFORM

CDR

4.5V

Data Retention Mode

-0.2V

4.5V

UTRON

UT62256C

Rev. 1.0

32K X 8 BIT LOW POWER CMOS SRAM

PACKAGE OUTLINE DIMENSION

28 pin 600 mil PDIP PACKAGE OUTLINE DIMENSION

UNIT

SYMBOL

INCH(BASE) MM(REF)

0.010 (MIN)

0.254 (MIN)

0.150±0.005 3.810±0.127

B 0.020

(MAX)

0.508(MAX)

B1 0.055

(MAX)

1.397(MAX)

0.012 (MAX)

0.304 (MAX)

1.430 (MAX) 36.322 (MAX)

0.6 (TYP)

15.24 (TYP)

0.52 (MAX)

13.208 (MAX)

e 0.100

(TYP)

2.540(TYP)

0.625 (MAX)

15.87 (MAX)

L 0.180(MAX)

4.572(MAX)

0.06 (MAX)

1.524 (MAX)

Q1 0.08(MAX)

2.032(MAX)

(MAX) 15

(MAX)

UTRON

UT62256C

Rev. 1.0

32K X 8 BIT LOW POWER CMOS SRAM

28 pin 330 mil SOP PACKAGE OUTLINE DIMENSION

UNIT

SYMBOL

INCH(BASE) MM(REF)

0.120 (MAX)

3.048 (MAX)

A1 0.002(MIN)

0.05(MIN)

0.098±0.005 2.489±0.127

b 0.0016

(TYP)

0.406(TYP)

c 0.010

(TYP)

0.254(TYP)

0.728 (MAX) 18.491 (MAX)

0.340 (MAX)

8.636 (MAX)

0.465±0.012 11.811±0.305

e 0.050

(TYP)

1.270(TYP)

0.05 (MAX)

1.270 (MAX)

0.067±0.008 1.702

0.203

0.047 (MAX)

1.194 (MAX)

y 0.003(MAX)

0.076(MAX)

UTRON

UT62256C

Rev. 1.0

32K X 8 BIT LOW POWER CMOS SRAM

28 pin 8x13.4mm STSOP PACKAGE OUTLINE DIMENSION

Note
E dimension is not including end flash
the total of both sides' end flash is
not above 0.3mm.

UNIT

SYMBOL

INCH(BASE) MM(REF)

0.047 (MAX)

1.20 (MAX)

0.004±0.002 0.10±0.05

0.039±0.002 1.00±0.05

b 0.006

(TYP)

0.15(TYP)

c 0.010

(TYP)

0.254(TYP)

0.465±0.004 11.80±0.10

0.315±0.004 8.00±0.10

e 0.022

(TYP)

0.55(TYP)

0.528±0.008 13.40±0.20

0.020±0.004 0.50±0.10

0.0315±0.004 0.80±0.10

y 0.08(MAX)

0.003(MAX)

UTRON

UT62256C

Rev. 1.0

32K X 8 BIT LOW POWER CMOS SRAM

ORDERING INFORMATION

PART NO.

ACCESS TIME

(ns)

STANDBY CURRENT

(

µA)

PACKAGE

UT62256CPC-70

5 mA

28PIN PDIP

UT62256CPC-70L 70

100 µA

28PIN PDIP

UT62256CPC-70LL 70

40 µA

28PIN PDIP

UT62256CSC-35

5 mA

28PIN SOP

UT62256CSC-35L 35

100 µA

28PIN SOP

UT62256CSC-35LL 35

40 µA

28PIN SOP

UT62256CSC-70

5 mA

28PIN SOP

UT62256CSC-70L 70

100 µA

28PIN SOP

UT62256CSC-70LL 70

40 µA

28PIN SOP

UT62256CLS-35L 35

100 µA

28PIN STSOP

UT62256CLS-35LL 35

50 µA

28PIN STSOP

UT62256CLS-70L 70

100 µA

28PIN STSOP

UT62256CLS-70LL 70

40 µA

28PIN STSOP

UTRON

UT62256C

Rev. 1.0

32K X 8 BIT LOW POWER CMOS SRAM

REVISION HISTORY

REVISION DESCRIPTION

DATE

REV. 0.9

1. Original.

Apr. 26,2001

REV. 1.0

1. The test condition of I

CC1

and

CC2

have been revised.

2. The symbols CE#,OE# and WE# are revised as

, OE and

3. The ordering information of PACKAGE ,STSOP-1 is

revised as STSOP.

MAY. 14,2001

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