UTRON

UT6264C

Rev. 1.1

8K X 8 BIT LOW POWER CMOS SRAM

UTRON TECHNOLOGY INC.

P80028

1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919

FEATURES

Access time : 35/70ns (max.)

Low power consumption :

Operating : 45/30 mA (typ.)

CMOS Standby : 2mA (typ.) normal

µA (typ.) L-version

µA (typ.) LL-version

Single 4.5V~5.5V power supply

Operating temperature :

Commercial : 0~70

All inputs and outputs TTL compatible
Fully static operation
Three state outputs
Data retention voltage : 2V (min.)
Package : 28-pin 600 mil PDIP

28-pin 330 mil SOP

FUNCTIONAL BLOCK DIAGRAM

DECODER

I/O DATA

CIRCUIT

CONTROL

CIRCUIT

8K × 8

MEMORY

ARRAY

COLUMN I/O

A0-A12

Vcc
Vss

I/O1-I/O8

CE1
CE2

PIN DESCRIPTION

SYMBOL DESCRIPTION

A0 - A12

Address Inputs

I/O1 - I/O8

Data Inputs/Outputs

CE ,CE2

Chip Enable Inputs

Write Enable Input

Output Enable Input

Power

Supply

Ground

NC No

connection

GENERAL DESCRIPTION

The UT6264C is a 65,536-bit low power CMOS
static random access memory organized as 8,192
words by 8 bits. It is fabricated using high
performance, high reliability CMOS technology.

Easy memory expansion is provided by using two
chip enable input.(

CE ,CE2) ,and supports low

data retention voltage for battery back-up
operation with low data retention current.

The UT6264C operates from a single 4.5V~5.5V
power supply and all inputs and outputs are fully
TTL compatible.

PIN CONFIGURATION

A12

I/O1

I/O2

Vcc

A11

A10

I/O8

I/O7

I/O6

I/O5

I/O4

I/O3

Vss

UT6264C

PDIP/SOP

CE2

UTRON

UT6264C

Rev. 1.1

8K X 8 BIT LOW POWER CMOS SRAM

UTRON TECHNOLOGY INC.

P80028

1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919

ABSOLUTE MAXIMUM RATINGS*

PARAMETER

SYMBOL

RATING

UNIT

Terminal Voltage with Respect to V

TERM

-0.5 to +7.0

Operating Temperature

Commercial

0 to +70

Storage Temperature

STG

-65 to +150

Power Dissipation

DC Output Current

OUT

Soldering Temperature (under 10 sec)

Tsolder

260

*Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress
rating only and functional operation of the device or any other conditions above those indicated in the operational sections of this
specification is not implied. Exposure to the absolute maximum rating conditions for extended period may affect device reliability.

TRUTH TABLE

MODE

CE2

WE I/O OPERATION

SUPPLY CURRENT

Standby

High - Z

ISB, ISB1

Standby

High - Z

ISB, ISB1

Output Disable

High - Z

Icc,Icc1,Icc2

Read

OUT

Icc,Icc1,Icc2

Write

Icc,Icc1,Icc2

note: H = V

, L=V

, X = Don't care.

DC ELECTRICAL CHARACTERISTICS

= 4.5V~5.5V, T

= 0 to 70)

PARAMETER

SYMBOL TEST CONDITION

MIN. TYP. MAX. UNIT

Power Voltage

Vcc

4.5

5.0

5.5

Input High Voltage

2.2

+0.5 V

Input Low Voltage

0.5

0.8

Input Leakage Current

- 1

µA

Output Leakage Current

I/O

CC;

CE =V

IH;

or CE2=V

IL;

or OE = V

;

or WE = V

- 1

µA

Output High Voltage

= - 1mA

2.4

Output Low Voltage

= 4mA

0.4

- 35

Cycle time=Min,I

I/O

0mA;

CE = V

IL ,

CE2= V

- 70

Icc1

Cycle time=1us; I

I/O

= 0mA ;

CE =0.2V; CE2=Vcc-0.2V;

other pins at 0.2V or Vcc-0.2V

- 20 30 mA

Operating Power
Supply Current

Icc2

Cycle time=500ns;I

I/O

= 0mA;

CE =0.2V; CE2=Vcc-0.2V;

other pins at 0.2V or Vcc-0.2V

- 10 15 mA

Normal - 1 10 mA

Standby Current (TTL)

= V

or CE2= V

- L/- LL

0.3

Normal - 2

5 mA

- L

100

µA

Standby Current (CMOS)

SB1

VCC-0.2V ;

or CE2

0.2V;

other pins at 0.2V or Vcc-0.2V

- LL

µA

UTRON

UT6264C

Rev. 1.1

8K X 8 BIT LOW POWER CMOS SRAM

UTRON TECHNOLOGY INC.

P80028

1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919

CAPACITANCE

=25, f=1.0MHz)

PARAMETER

SYMBOL

MIN.

MAX

UNIT

Input Capacitance

8 pF

Input/Output Capacitance

I/O

10 pF

Note : These parameters are guaranteed by device characterization, but not production tested.

AC TEST CONDITIONS

Input Pulse Levels

0V to 3.0V

Input Rise and Fall Times

5ns

Input and Output Timing Reference Levels

1.5V

Output Load

= 100pF, I

= -1mA/4mA

AC ELECTRICAL CHARACTERISTICS

= 4.5V~5.5V, T

= 0 to 70)

(1) READ CYCLE

UT6264C-35 UT6264C-70

PARAMETER

SYMBOL

MIN. MAX. MIN. MAX.

UNIT

Read Cycle Time

35 - 70 - ns

Address Access Time

Chip Enable Access Time

ACE1,

ACE2

- 35 - 70 ns

Output Enable Access Time

Chip Enable to Output in Low-Z

CLZ1*,

CLZ2*

10 - 10 - ns

Output Enable to Output in Low-Z

OLZ*

5 - 5 - ns

Chip Disable to Output in High-Z

CHZ1*,

CHZ2*

- 25 - 35 ns

Output Disable to Output in High-Z

OHZ*

Output Hold from Address Change

5 - 5 - ns

(2) WRITE CYCLE

UT6264C-35 UT6264C-70

PARAMETER

SYMBOL

MIN. MAX. MIN. MAX.

UNIT

Write Cycle Time

35 - 70 - ns

Address Valid to End of Write

30 - 60 - ns

Chip Enable to End of Write

CW1,

CW2

30 - 60 - ns

Address Set-up Time

0 - 0 - ns

Write Pulse Width

25 - 50 - ns

Write Recovery Time

0 - 0 - ns

Data to Write Time Overlap

20 - 30 - ns

Data Hold from End of Write-Time

0 - 0 - ns

Output Active from End of Write

OW*

5 - 5 - ns

Write to Output in High-Z

WHZ*

*These parameters are guaranteed by device characterization, but not production tested.

UTRON

UT6264C

Rev. 1.1

8K X 8 BIT LOW POWER CMOS SRAM

UTRON TECHNOLOGY INC.

P80028

1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919

TIMING WAVEFORMS

READ CYCLE 1 (Address Controlled)

(1,2,4)

Address

DOUT

Data Valid

READ CYCLE 2 (

CE , CE2 and OE Controlled)

(1,3,5,6)

ACE1

ACE2

CHZ1

CHZ2

OHZ

CLZ1

CLZ2

OLZ

HIGH-Z

Data Valid

HIGH-Z

Address

CE1

CE2

Dout

Notes :
1. WE is HIGH for a read cycle.
2. Device is continuously selected OE

CE =V

and CE2=V

IH.

3. Address must be valid prior to or coincident with

low

and CE2 high transition; otherwise t

is the limiting parameter.

4. OE is low.
5. t

CLZ1

, t

CLZ2

, t

OLZ

, t

CHZ1

, t

CHZ2

and t

OHZ

are specified with C

=5pF. Transition is measured ± 500mV from steady state.

6. At any given temperature and voltage condition, t

CHZ1

is less than t

CLZ1

, t

CHZ2

is less than t

CLZ2

, t

OHZ

is less than t

OLZ.

UTRON

UT6264C

Rev. 1.1

8K X 8 BIT LOW POWER CMOS SRAM

UTRON TECHNOLOGY INC.

P80028

1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919

WRITE CYCLE 1 ( WE Controlled)

(1,2,3,5,6)

CW1

WHZ

CW2

Address

CE1

CE2

Dout

Din

Data Valid

High-Z

(4)

WRITE CYCLE 2 (

CE and CE2 Controlled)

(1,2,5)

CW1

CW2

WHZ

Data Valid

Address

CE1

CE2

Dout

Din

High-Z

Notes :
1.

WE or

CE must be HIGH or CE2 must be LOW during all address transitions.

2. A write occurs during the overlap of a low

CE , a high CE2 and a low

WE .

3. During a

WE controlled with write cycle with OE LOW, t

must be greater than t

WHZ

to allow the I/O drivers to turn off

and data to be placed on the bus.

4. During this period, I/O pins are in the output state, and input singals must not be applied.
5. If the 1

CE LOW transition occurs simultaneously with or after WE LOW transition, the outputs remain in a high Impedance state.

6. t

and t

WHZ

are specified with C

=5pF. Transition is measured ± 500mV from steady state.

UTRON

UT6264C

Rev. 1.1

8K X 8 BIT LOW POWER CMOS SRAM

UTRON TECHNOLOGY INC.

P80028

1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919

DATA RETENTION CHARACTERISTICS

(TA = 0 to 70)

PARAMETER SYMBOL

TEST

CONDITION

MIN.

TYP.

MAX.

UNIT

Vcc for Data Retention

CE V

-0.2V or CE2

0.2V

2.0 - 5.5 V

-L - 1 50

µA

Data Retention Current

Vcc=2V

CE V

-0.2V or CE2

0.2V -LL - 0.5 20 µA

Chip Disable to Data
Retention Time

CDR

See Data RetentionWaveforms
(below)

0 - - ns

Recovery Time

RC*

- - ns

RC*

= Read Cycle Time

DATA RETENTION WAVEFORM

Low Vcc Data Retention Waveform (1) (

CE controlled)

Data Retention Mode

CE1 V

-0.2V

Vcc

CE1

CDR

Low Vcc Data Retention Waveform (2) (CE2 controlled)

Data Retention Mode

Vcc

CDR

CE2 0.2V

CE2

UTRON

UT6264C

Rev. 1.1

8K X 8 BIT LOW POWER CMOS SRAM

UTRON TECHNOLOGY INC.

P80028

1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919

PACKAGE OUTLINE DIMENSION

28 pin 600 mil PDIP Package Outline Dimension

UNIT

SYMBOL

INCH(BASE) MM(REF)

0.010 (MIN)

0.254 (MIN)

0.150± 0.005 3.810± 0.127

B 0.020

(MAX)

0.508(MAX)

B1 0.055

(MAX)

1.397(MAX)

0.012 (MAX)

0.304 (MAX)

1.430 (MAX) 36.322 (MAX)

0.625 (MAX)

15.87 (MAX)

0.52 (MAX)

13.208 (MAX)

e 0.100

(TYP)

2.540(TYP)

0.6 (TYP)

15.24 (TYP)

L 0.180(MAX)

4.572(MAX)

0.06 (MAX)

1.524 (MAX)

Q1 0.08(MAX)

2.032(MAX)

(MAX) 15

(MAX)

UTRON

UT6264C

Rev. 1.1

8K X 8 BIT LOW POWER CMOS SRAM

UTRON TECHNOLOGY INC.

P80028

1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919

28 pin 330 mil SOP Package Outline Dimension

INCH(REF) MM(BASE)

A 0.112(max)

2.845(max)

A1 0.004(MIN)

0.102(MIN)

A2 0.098±0.005

2.489±0.127

b 0.016(TYP)

0.406(TYP)

c 0.010(TYP)

0.254(TYP)

D 0.713±0.005

18.110±0.127

E 0.331±0.005

8.407±0.127

E1 0.465±0.012

11.811±0.305

e 0.050(TYP)

1.270(TYP)

L 0.0404±0.008

1.0255±0.203

L1 0.067±0.008

1.702±0.203

S 0.047(MAX)

1.194(MAX)

y 0.003(MAX)

0.076(MAX)

0°~10°

UNIT

SYMBOL

UTRON

UT6264C

Rev. 1.1

8K X 8 BIT LOW POWER CMOS SRAM

UTRON TECHNOLOGY INC.

P80028

1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919

ORDERING INFORMATION

PART NO.

ACCESS TIME

(ns)

STANDBY CURRENT

(µA) (TYP.)

PACKAGE

UT6264CPC-35

2mA

28 PIN PDIP

UT6264CPC-35L 35

2µA

28 PIN PDIP

UT6264CPC-35LL 35

1µA

28 PIN PDIP

UT6264CPC-70

2mA

28 PIN PDIP

UT6264CPC-70L 70

2µA

28 PIN PDIP

UT6264CPC-70LL 70

1µA

28 PIN PDIP

UT6264CSC-35

2mA

28 PIN SOP

UT6264CSC-35L 35

2µA

28 PIN SOP

UT6264CSC-35LL 35

1µA

28 PIN SOP

UT6264CSC-70

2mA

28 PIN SOP

UT6264CSC-70L 70

2µA

28 PIN SOP

UT6264CSC-70LL 70

1µA

28 PIN SOP

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