Copyright 1998, V3 Semiconductor Corp.
V292BMC Data Sheet Rev 3.2X
1
V292BMC
Rev. D
HIGH PERFORMANCE BURST
DRAM CONTROLLER
FOR Am29030/40 PROCESSORS
V3 Semiconductor reserves the right to change the specifications of this product without notice.
V292BMC is trademark of V3 Semiconductor. All other trademarks are the property of their respective owners.
Am29030/40
CPU
V292BMC
MEMORY
CONTROL
D
R
A
M
ROM
VxxxEPC
LOCAL TO
PCI BRIDGE
PCI
PERIPHERAL
PCI SLOT or EDGE CONNECTOR
TYPICAL APPLICATION
Pin/Software compatible with earlier V292BMC.
Direct interfaces to Am29030/40 processors.
3.3V DRAM interface support.
Near SRAM performance achieved with DRAM.
Supports up to 512Mb of DRAM.
Interleaved or non-interleaved operation.
Supports symmetric and non-symmetric arrays.
Software-configured operational parameters.
Integrated Page Cache Management.
2Kbyte burst transaction support.
On chip memory address multiplexer/drivers.
Two 24-bit timers, 8-bit bus watch timer.
Up to 40MHz operation.
Low cost 132-pin PQFP package.
T h e V 2 9 2 B M C R e v i s i o n D B u r s t D R A M
Controller is an enhanced version of the previous
V292BMC with improved timing and provides
dedicated Power and Ground rails to support the
increasingly popular 3.3V DRAM modules.
Timing parameters are also improved over the
older versions of the device.
The V292BMC provides the DRAM access
protocols, buffer signals, data multiplexer
signals, and bus timing resources required to
work with DRAM. By using the V2926BMC,
system designers can replace tedious design
work, expensive FPGAs and valuable board
space with a single, high-performance, easily
configured device. The processor interface of the
V292BMC implements the bus protocol of the
Am29030/40. The pin naming convention has
been duplicated on the V292BMC; simply wire
like-named pins together to create the interface.
The V292BMC supports a total DRAM memory
subsystem size of 512Mbytes. The array may be
organized as 1 or 2 leafs of 32-bits each.
Standard memory sizes of 256Kbit to 64Mbit
devices are supported and 8, 16, and 32-bit
accesses are allowed. The V292BMC takes
advantage of Fast Page Mode or EDO DRAMs
and row comparison logic to achieve static RAM
performance using dynamic RAMs. Control
signals required for optional external data path
b u f f e r s / l a t c h e s a r e a l s o p r o v i d e d b y t h e
V292BMC. The V292BMC provides an 8-bit bus
watch timer to detect and recover from accesses
to unpopulated memory regions.Two 24-bit
counters/timers can supply an external interrupt
signal at a constant frequency relative to the
system clock. The V292BMC is packaged in a
low-cost 132-pin PQFP package and is available
in 25, 33, or 40MHz versions.
This document contains the product codes,
pinouts, package mechanical information, DC
characteristics, and AC characteristics for the
V292BMC. Detailed functional information is
contained in the User's Manual.
V292BMC Rev.D
2
V292BMC Rev D Data Sheet Rev 3.2
Copyright 1998, V3 Semiconductor Inc.
V3 Semiconductor retains the rights to change documentation, specifications, or device
functionality at any time without notice. Please verify that you have the latest copy of all
documents before finalizing a design.
1.0 Product Codes
Table 1: Pin Types
2.0 Pin Description and Pinout
Table 2 below lists the pin types found on the V292BMC. Table 3 describes the function of each pin on
the V292BMC. Table 4 lists the pins by pin number. Figure 1 shows the pinout for the 132-pin PQFP
package and Figure 2 shows the mechanical dimensions of the package.
Product Code
Processor
Bus Type
Package
Frequency
V292BMC-33LP
Am29030/35/40
32-bit demultiplexed
132-pin PQFP
33MHz
V292BMC-40LP
Am29030/35/40
32-bit demultiplexed
132-pin PQFP
40MHz
Table 2: Pin Types
Pin Type
Description
I/O
12
TTL I/O pin with 12 mA output drive
I
TTL input only pin
O
12
TTL Output pin with 12 mA output drive
O
12-3
TTL Output pin with 12 mA output drive that can be
configured for either 5 volt or 3.3 volt signaling, These
outputs can be configured for 3.3V operation by
connecting the Vcc3 power pins to a 3.3V power plane
(Vcc should always be connected to a 5V supply). Vcc3
can also be connected to the 5V plane if 5V signaling is
desired.
V292BMC Rev.D
Copyright 1998, V3 Semiconductor Corp.
V292BMC Rev D Data Sheet Rev 3.2
3
Table 3: Signal Descriptions
Memory Interface Signals
Signal
Type
R
a
Description
AA[11:0]
AB[11:0]
O
12-3
X
Leaf A and B row and column address, multiplexed on the same
pins. When non-interleaved operation is selected, only address bus
AA should be used.
RASA[3:0]
RASB[3:0]
O
12-3
H
Row Address Strobe. These strobes indicate the presence of a valid
row address on busses AA(B)[11:0]. These signals are to be con-
nected one to each 32-bit leaf of memory.
CASA[3:0]
CASB[3:0]
O
12-3
H
Column Address Strobe. These strobes latch a column address from
AA(B)[11:0]. They are assigned one to each byte in a leaf.
MWEA
MWEB
O
12-3
H
Memory Write Enable. These are the DRAM write strobes. One is
supplied for each leaf to minimize signal loading.
RFS/AUXT
O
12
H
Refresh in progress. This output is multi-function signal. The signal
name, as it appears on the logic symbol, is the default signal names.
This signal gives notice that a refresh cycle is to be executed. The
timing leads RAS only refresh by one cycle. The output may also
function as AUX timer interrupt.
Configuration
Signal
Type
R
Description
MOD4
I
Selects Modulo 4 (word) bursting for multiplexed address AA(B).
Buffer Controls Signals
Signal
Type
R
Description
TXA
TXB
O
12
H
Data Transmit A and B. These outputs are multi-function signals.
The signal names, as they appear on the logic symbol, are the
default signal names (Mode 0). The purpose of these outputs is to
control buffer output enables during data read transactions and, in
effect, control the multiplexing of data from each memory leaf onto
the Am29030/40 data bus.
LEA
LEB
O
12
L
These outputs are mode independent, however, the timing of the
signals change for different operational modes. They control trans-
parent latches that hold data transmitted during a write transaction.
In modes 0 and 1, the latch controls follow the timing of CAS for
each leaf, while in modes 2 and 3 the timing of LEA and LEB is
shortened to 1/2 clock.
Local Bus Interface
V292BMC Rev.D
4
V292BMC Rev D Data Sheet Rev 3.2
Copyright 1998, V3 Semiconductor Inc.
Signal
Type
R
Description
A[31:2]
I
Local address bus.
ALE
I
Address Latch Enable: controls a set of transparent latches on the
address bus. When asserted high, the address input flows through
the latch. When ALE is low, the internal address holds the previous
value. With an Am29030/40 processor ALE is not typically used and
has an internal pull-up resistor that will keep it high when not con-
nected (to provide backward pin compatibility with earlier versions).
I/D
I
Data/Code.
BWE[3:0]
I
Local bus byte write enables.
R/W
I
Read/write.
REQ
I
Asserted low to indicate the beginning of a bus cycle.
RDY
O
12
Z
Local bus data ready.
PRDY
I
Processor ready
SUP/US
I
Indicates supervisor mode. Required for access to configuration reg-
isters.
BURST
I
Burst request.
ERR
O
12
H
Bus Time-out error.
INT
O
12
H
Local interrupt request. This signal is asserted when the 24-bit
counter reaches terminal count, and interrupt out is enabled. May
be programmed for pulse or level operation.
RESET
I
Local bus reset signal.
MEMCLK
I
Local bus clock.
ID[2:0]
I
These inputs select the address offset of the configuration registers.
Power and Ground Signals
Signal
Type
R
Description
Vcc
-
POWER leads intended for external connection to a 5V Vcc plane
Vcc3
-
POWER for DRAM control outputs. Can be connected to 3.3V or 5V.
GND
-
GROUND leads intended for external connection to a GND plane.
a.
R indicates state during reset.
Table 3: Signal Descriptions (cont'd)
V292BMC Rev.D
Copyright 1998, V3 Semiconductor Corp.
V292BMC Rev D Data Sheet Rev 3.2
5
Table 4: Pin Assignments
PIN #
Signal
PIN #
Signal
PIN #
Signal
PIN #
Signal
1
A14
34
REQ
67
AA10
100
AB9
2
A15
35
BWE2
68
AA11
101
AB10
3
A16
36
BWE3
69
Vcc3
102
AB11
4
Vcc
37
GND
70
GND
103
Vcc3
5
A17
38
RDY
71
CASA0
104
GND
6
A19
39
ID0
72
CASA1
105
CASB0
7
A20
40
ID1
73
CASA2
106
CASB1
8
A18
41
ID2
74
CASA3
107
CASB2
9
A21
42
RFS/AUXT
75
Vcc3
108
CASB3
10
A24
43
LEA
76
GND
109
Vcc3
11
A22
44
LEB
77
RASA0
110
GND
12
A23
45
TXA
78
RASA1
111
RASB0
13
A26
46
TXB
79
RASA2
112
RASB1
14
A25
47
Vcc
80
RASA3
113
RASB2
15
A27
48
GND
81
Vcc3
114
RASB3
16
ALE
49
-
82
MWEA
115
Vcc
17
-
50
-
83
-
116
-
18
-
51
-
84
-
117
MOD4
19
A31
52
-
85
-
118
MWEB
20
A28
53
AA0
86
GND
119
GND
21
A29
54
AA1
87
AB0
120
RESET
22
A30
55
AA2
88
AB1
121
A2
23
I/D
56
AA3
89
AB2
122
A3
24
SUP/US
57
Vcc3
90
AB3
123
A4
25
MEMCLK
58
GND
91
Vcc3
124
A5
26
INT
59
AA4
92
GND
125
A6
27
ERR
60
AA5
93
AB4
126
A7
V292BMC Rev.D
6
V292BMC Rev D Data Sheet Rev 3.2
Copyright 1998, V3 Semiconductor Inc.
Figure 1: Pinout for 132-pin PQFP (top view)
PIN #
Signal
PIN #
Signal
PIN #
Signal
PIN #
Signal
28
R/W
61
AA6
94
AB5
127
A8
29
BWE0
62
AA7
95
AB6
128
A9
30
PRDY
63
Vcc3
96
AB7
129
A10
31
BURST
64
GND
97
Vcc3
130
A11
32
BWE1
65
AA8
98
GND
131
A12
33
GND
66
AA9
99
AB8
132
A13
Table 4: Pin Assignments (cont'd)
V292BMC Rev.D
Copyright 1998, V3 Semiconductor Corp.
V292BMC Rev D Data Sheet Rev 3.2
7
Figure 2: 132-pin PQFP mechanical details
V292BMC Rev.D
8
V292BMC Rev D Data Sheet Rev 3.2
Copyright 1998, V3 Semiconductor Inc.
3.0 DC Specifications
1. For 3.3 Volt DRAM intreface operation.(See also note 8 table 11)
Table 5: Absolute Maximum Ratings
Symbol
Parameter
Rating
Units
V
CC
Supply voltage
-0.3 to +7
V
V
IN
DC input voltage
-0.3 to V
CC
+0.3
V
I
IN
DC input current
50
mA
T
STG
Storage temperature
-65 to +150
C
Table 6: Guaranteed Operating Conditions
Symbol
Parameter
Rating
Units
V
CC,
V
CC3
Supply voltage
4.75 to 5.25
V
V
CC3
Supply voltage for 3.3 Volt DRAM inter-
face operation
1
. Vcc is still as above
3.0 to 3.6
V
T
A
Ambient temperature range
0 to 70
C
Table 7: DC Operating Specifications Vcc=5 Volt and Vcc3=5 Volt
Symbol
Description
Conditions
Min
Max
Units
V
IL
Low level input voltage
Vcc = 4.75V
0.8
V
V
IH
High level input voltage
Vcc = 5.25V
2.0
V
I
IL
Low level input current
V
IN
= GND, V
CC
= 5.25V
-10
A
I
IH
High level input current
V
IN
= V
CC
= 5.25V
10
A
V
OL
Low level output voltage
V
IN
= V
IL
or
V
IH
I
OL
= -12 mA
0.4
V
V
OH
High level output voltage
V
IN
= V
IL
or
V
IH
I
OL
= -12 mA
V
CC
-1.0
V
V292BMC Rev.D
Copyright 1998, V3 Semiconductor Corp.
V292BMC Rev D Data Sheet Rev 3.2
9
4.0 AC Specifications
1. For 3.3 Volt DRAM interface operation.(See also note 8 table 11)
I
OZL
Low level float input
leakage
V
IN
= V
IL
or
V
IH
V
O
= -GND
-20
A
I
OZH
High level float input
leakage
V
IN
= V
IL
or
V
IH
V
O
= -5.25V
20
A
I
CC
(max)
Maximum supply current
Continuous simple access
Continuous burst access
100
30
mA
C
IO
Input and output
capacitance
20
pF
Table 8: DC Operating Specifications Vcc3=3.3 Volt and Vcc=5 Volt
Symbol
Description
Conditions
Min
Max
Units
V
OL
Low level output voltage
V
IN
= Vcc3
I
OL
= 12 mA
0.4
V
V
OH
High level output voltage
V
IN
= Vcc3
I
OL
= -12 mA
2.4
V
I
OZL
Low level float input
leakage
V
IN
= Vcc3
V
O
= GND
-10
A
I
OZH
High level float input
leakage
V
IN
= Vcc3
V
O
=4.465 V
10
A
I
CC
(max)
Maximum supply current
Continuous simple access
Continuous burst access
140
40
mA
Table 9: AC Test Conditions
Symbol
Parameter
Limits
Units
V
CC,
V
CC3
Supply voltage
4.75 to 5.25
V
V
CC3
Supply voltage for 3.3 Volt DRAM inter-
face operation
1
(Vcc is still as above)
4.75 to 5.25
V
V
IN
Input low and high voltages
0.4 and 4.25
V
C
OUT
Capacitive load on output and I/O pins
50
pF
Table 7: DC Operating Specifications Vcc=5 Volt and Vcc3=5 Volt
Symbol
Description
Conditions
Min
Max
Units
V292BMC Rev.D
10
V292BMC Rev D Data Sheet Rev 3.2
Copyright 1998, V3 Semiconductor Inc.
Table 10: Capacitive Derating for Output and I/O Pins
Output Drive Limit
Supply voltage
Derating
12 mA
Vcc=5 Volt, Vcc3=3.3 Volt
0.06 ns/pF for loads > 50 pF
12 mA
Vcc=5 Volt, Vcc3=5 Volt
0.04 ns/pF for loads > 50 pF
Table 11: Timing Parameters for V292BMC Vcc = 5 Volts +/- 5% and Vcc3 = 5
or 3.3
8
Volts +/- 5%
33 MHz
40 MHz
Symbol
Description
Note
Min
Max
Min
Max Units
t
C
MEMCLK period
30
25
ns
t
CH
MEMCLK high time
12
11
ns
t
CL
MEMCLK low time
12
11
ns
t
SU
Synchronous input setup
9
8
ns
t
H
Synchronous input hold
1
0.5
ns
t
H
Synchronous input hold (RESET#)
3
3
ns
t
RZH
RDY 3-state to valid delay
1
3
13
3
10
ns
t
RHL
RDY synchronous assertion delay
3
13
3
11
ns
t
RLH
RDY synchronous de-assertion delay
3
13
3
11
ns
t
RHZ
RDY valid to 3-state delay
1
3
10
3
7
ns
t
EHL
ERR synchronous assertion delay
3
13
3
11
ns
t
ELH
ERR synchronous de-assertion delay
3
12
3
10
ns
t
IHL
INT synchronous assertion delay
3
13
3
11
ns
t
ILH
INT synchronous de-assertion delay
3
12
3
10
ns
t
ARA1
Address Input to Row Address output delay
(Interleaved)
3
14
3
12
ns
t
ARA2
Address Input to Row Address output delay
(Non-interleaved)
4
18
4
15
ns
t
RAH
Row address hold from RAS assertion
2
t
M
t
M
+2
t
M
t
M
+2
ns
t
CAV
Column address valid from RAS assertion
2
t
M
+1
t
M
+4
t
M
+1
t
M
+4
ns
t
CAH
Column address hold from CAS assertion
t
C
t
C
ns
t
BCAV
Column address valid delay from previous
CAS assertion (Burst)
t
C
+3
t
C
+3
ns
t
RHL
MEMCLK to RAS asserted delay
3
13
3
11
ns
t
RLH
MEMCLK to RAS de-asserted delay
3
13
3
11
ns
t
RAS
RAS pulse width
3
3t
C
-1
3t
C
-1
ns
t
RSH
RAS hold from last CAS assertion
4
t
N
t
N
ns
t
RP
RAS precharge time
5
t
P
-2
t
P
-2
ns
t
CHL
MEMCLK to CAS asserted delay
1
3
13
3
12
ns
V292BMC Rev.D
Copyright 1998, V3 Semiconductor Corp.
V292BMC Rev D Data Sheet Rev 3.2
11
NOTES:
1. Specified from MEMCLK falling edge.
2. t
M
= t
C
when T_MUX = 1; t
M
= 0.5
t
C
when T_MUX = 0.
3. Maximum RAS pulse width depends on the number of burst access.
4. t
N
= 1.5
t
C
when T_RAS = 0; t
N
= 2.5
t
C
when T_RAS = 1.
5. t
P
= 2
t
C
when T_RAS = 0; t
P
= 2
t
C
when T_RAS = 1 and T_RP = 1;
t
P
= 3
t
C
when T_RAS = 1 and T_RP = 0.
6. Rising delay is measured from MEMCLK falling edge, falling delay is measured from MEMCLK rising edge.
7. Except for Mode 2 and 3 at TXA pin.
8. In order to have 3.3 Volt DRAM interface Vcc3 pins must be connected to 3.3 Volt.
Vcc3 pins are: PIN # 91, 97, 103, 57, 63, 69, 75, 81.
The power supply pins that must always be connected to 5 Volt are Vcc.
Vcc pins are: PIN # 4, 47, 115.
Figure 3: Clock and Synchronous Signals
t
CLH
MEMCLK to CAS de-asserted delay
4
12
3
11
ns
t
CAS
CAS pulse width
4
t
N
-1
t
N
-1
ns
t
CPN
CAS precharge time
0.5t
C
0.5t
C
ns
t
RCD
RAS to CAS delay time
1.5t
C
-2
1.5t
C
1.5t
C
-2
1.5t
C
ns
t
WESU
Write Enable setup to RAS assertion
10
9
ns
t
WEH
Write Enable hold from RAS de-assertion
1
3
1
3
ns
t
LED
MEMCLK to Latch Enable output delay
6
3
12
3
10
ns
t
TXHL1
MEMCLK to Buffer Control fall delay
7
3
13
3
11
ns
t
TXHL2
MEMCLK to Buffer Control fall delay (Mode 2
and 3 at TXA pin only)
4
15
4
13
ns
t
TXLH
MEMCLK to Buffer Control rise delay
3
12
3
10
ns
t
RFHL
REFRESH synchronous assertion delay
3
13
3
11
ns
t
RFLH
REFRESH synchronous de-assertion delay
3
13
3
11
ns
t
ASU
Address setup to ALE Falling
6
5
ns
t
AH
Address hold from ALE Falling
5
4
ns
Table 11: Timing Parameters for V292BMC Vcc = 5 Volts +/- 5% (cont'd)and
Vcc3 = 5 or 3.3
8
Volts +/- 5%
V292BMC Rev.D
12
V292BMC Rev D Data Sheet Rev 3.2
Copyright 1998, V3 Semiconductor Inc.
Figure 4: ALE Timing
Figure 5: Basic Access Timing
V292BMC Rev.D
Copyright 1998, V3 Semiconductor Corp.
V292BMC Rev D Data Sheet Rev 3.2
13
Figure 6: Burst Access Timing
V292BMC Rev.D
14
V292BMC Rev D Data Sheet Rev 3.2
Copyright 1998, V3 Semiconductor Inc.
5.0 Revision History
Table 12: Revision History
Revision
Number
Date
Comments and Changes
3.2
7/98
V292BMC Rev D timing parameters with 3.3V DRAM support.
3.1
10/96
Data Book revision.
3.0
05/96
Updated timings to final D-step values.
Simplified data sheet format.
2.0
7/92
Updated timings to final A-step values.
1.0
7/92
First pre-silicon revision of preliminary data sheet.
DC and AC specs TBD. Sent only to a limited number of customers
PDF 
ZIP