ZFx86 Data Book 1.0 Rev C

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Legal Notice

THIS DOCUMENT AND THE INFORMATION CONTAINED THEREIN IS PROVIDED "AS-IS"
AND WITHOUT A WARRANTY OF ANY KIND. YOU, THE USER, ACCEPT FULL RESPONSI-
BILITY FOR PROPER USE OF THE MATERIAL. ZF MICRO DEVICES, INC. MAKES NO REP-
RESENTATIONS OR WARRANTIES THAT THIS DATA BOOK OR THE INFORMATION
CONTAINED THERE-IN IS ERROR FREE OR THAT THE USE THEREOF WILL NOT
INFRINGE ANY PATENTS, COPYRIGHT OR TRADEMARKS OF THIRD PARTIES. ZF MICRO
DEVICES, INC. EXPLICITLY ASSUMES NO LIABILITY FOR ANY DAMAGES WHATSOEVER
RELATING TO ITS USE.

LIFE SUPPORTPOLICY

ZF MICRO DEVICES' PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPO-
NENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN
APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF ZF MICRO DEVICES, INC.

As used herein:

1. Life support devices or systems are devices or systems which, (a) are intended for surgical
implant into the body, or (b) support or sustain life, and whose failure to perform when properly
used in accordance with instructions for use provided in the labeling, can be reasonably
expected to result in a significant injury to the user.

2. A critical component is any component of a life support device or system whose failure to
perform can be reasonably expected to cause the failure of the life support device or system, or
to affect its safety or effectiveness.

ZFx86, FailSafe FailSafe Boot ROM, Z-tag ZF-Logic, InternetSafe, OEMmodule SCC, ZF
SystemCard, ZF FlashDisk-SC, netDisplay, ZF 104Card, ZF SlotCard, and ZF Micro Devices
logo are trademarks of ZF Micro Devices, Inc. Other brands and product names are trademarks
of their respective owners.

ZFx86 Data Book 1.0 Rev C

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Table of Contents

1. Overview .................................................................................................................. 23

2. 32-bit x86 Processor................................................................................................ 25

2.1. Overview ...................................................................................................................... 25

2.1.1. Internal Clock Logic ............................................................................................ 26
2.1.2. On-Chip Write-Back Cache ................................................................................ 26
2.1.3. System Management Mode................................................................................ 27
2.1.4. Power Management............................................................................................ 27
2.1.5. Signal Summary ................................................................................................. 27

2.2. Programming Interface ................................................................................................ 27

2.2.1. Processor Initialization........................................................................................ 28
2.2.2. Instruction Set Overview..................................................................................... 29
2.2.3. Register Set ........................................................................................................ 30
2.2.4. Address Spaces.................................................................................................. 53
2.2.5. Interrupts and Exceptions ................................................................................... 59
2.2.6. System Management Mode................................................................................ 64
2.2.7. Shutdown and Halt ............................................................................................. 73
2.2.8. Protection............................................................................................................ 73
2.2.9. Virtual 8086 Mode............................................................................................... 75
2.2.10. FPU Operations ................................................................................................ 76

2.3. Instruction Set .............................................................................................................. 79

2.3.1. General Instruction Fields................................................................................... 80
2.3.2. Instruction Set Tables ......................................................................................... 86

3. North Bridge ........................................................................................................... 108

3.1. North Bridge Features ............................................................................................... 108
3.2. Interface Signals ........................................................................................................ 111
3.3. Functional Description ............................................................................................... 113

3.3.1. Processor Interface........................................................................................... 113
3.3.2. DRAM Controller............................................................................................... 117
3.3.3. Configuration and Testability ............................................................................ 121
3.3.4. PCI bus interface and arbiter ............................................................................ 122
3.3.5. PCI WriteBuffer and Bursts.............................................................................. 124
3.3.6. Write buffer architecture ................................................................................... 129
3.3.7. System Management Mode.............................................................................. 129
3.3.8. Power Management.......................................................................................... 131

3.4. Register Set ............................................................................................................... 131

3.4.1. Register Address Map ...................................................................................... 132
3.4.2. DRAM registers ................................................................................................ 144
3.4.3. Power Management registers ........................................................................... 155
3.4.4. Test Signals ...................................................................................................... 157
3.4.5. PCI configuration registers ............................................................................... 157

4. South Bridge .......................................................................................................... 160

4.1. South BridgeModule................................................................................................. 160

4.1.1. South Bridge Features...................................................................................... 160

Table of Contents

ZFx86 Data Book 1.0 Rev C

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Table of Contents

4.2. Architecture................................................................................................................ 161

4.2.1. Front-sidePCI / Back-SidePCI Bus ................................................................. 162
4.2.2. IDE Controller ................................................................................................... 163
4.2.3. Universal Serial Bus ......................................................................................... 163
4.2.4. Integrated SuperI/O .......................................................................................... 164
4.2.5. ISA Bus Interface.............................................................................................. 164
4.2.6. Power Management.......................................................................................... 165
4.2.7. GPIO Interface.................................................................................................. 166
4.2.8. ZF-Logic............................................................................................................ 166

4.3. Signal Descriptions .................................................................................................... 167

4.3.1. System Interface Signals .................................................................................. 168
4.3.2. Back-SidePCI InterfaceSignals....................................................................... 170
4.3.3. Integrated SuperI/O Interface Signals .............................................................. 183

4.4. Register Descriptions................................................................................................. 190

4.4.1. PCI Configuration Space and Access Methods ................................................ 191
4.4.2. Register Summaries ......................................................................................... 192
4.4.3. Chipset Register Space .................................................................................... 201
4.4.4. USB Controller Registers - PCIUSB ................................................................. 241
4.4.5. ISA Legacy Register Space.............................................................................. 243

4.5. SuperI/O - A PC98 Compliant Cell ............................................................................ 253

4.5.1. Outstanding Features ....................................................................................... 253
4.5.2. Features............................................................................................................ 254
4.5.3. SIGNAL/PIN Descriptions................................................................................. 256
4.5.4. Device Architecture and Configuration ............................................................. 256
4.5.5. Standard Logical Device Configuration Register Definitions ............................ 260
4.5.6. Standard Configuration Registers..................................................................... 262

4.6. SuperI/O Configuration Registers .............................................................................. 264

4.6.1. Register Type Abbreviations ............................................................................ 264

4.7. Floppy Disk Controller (FDC) Configuration .............................................................. 267
4.8. Parallel Port Configuration ......................................................................................... 269

4.8.1. Logical Device 1 (PP) Configuration................................................................. 269

4.9. System Wake-Up Control (SWC) .............................................................................. 271

4.9.1. Overview........................................................................................................... 271
4.9.2. Functional Description ...................................................................................... 271
4.9.3. Event Detection ................................................................................................ 272
4.9.4. SWC Register Bitmap....................................................................................... 286
4.9.5. Keyboard/Mouse Control .................................................................................. 289
4.9.6. Infrared Communication Port Configuration ..................................................... 292

4.10. ACCESS.Bus Interface (ACB) Configuration........................................................... 293
4.11. Real-time Clock (RTC)............................................................................................. 295

4.11.1. RTC Overview ................................................................................................ 297
4.11.2. Functional Description .................................................................................... 297
4.11.3. RTC Configuration Registers.......................................................................... 302
4.11.4. RTC Registers ................................................................................................ 304

ZFx86 Data Book 1.0 Rev C

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Table of Contents

4.11.5. RTC General-purpose RAM Map

.................................................................. 316

4.12. ACCESS.bus Interface (ACB) ................................................................................. 317

4.12.1. Functional Description .................................................................................... 317
4.12.2. ACB Registers ................................................................................................ 324

4.13. Legacy Functional Blocks ........................................................................................ 330

4.13.1. Keyboard and Mouse Controller (KBC) .......................................................... 330
4.13.2. Floppy Disk Controller (FDC).......................................................................... 331
4.13.3. Parallel Port .................................................................................................... 332
4.13.4. UART Functionality (SP1/SP2) ....................................................................... 335
4.13.5. IR Communication Port (IRCP) Functionality ................................................. 340

5. ZF-Logic and Clocking .......................................................................................... 397

5.1. Features..................................................................................................................... 397
5.2. ZFL Register Space Summary .................................................................................. 398

5.2.1. Pins Associated with ZF-Logic.......................................................................... 402

5.3. ISA Memory Mapper for Flash/SRAM ....................................................................... 404

5.3.1. Window settings registers ................................................................................ 409
5.3.2. Control (R/W, 8/16) ........................................................................................... 412
5.3.3. Events (SMI, etc.) ............................................................................................. 412
5.3.4. Initialization of mem_cs0 .................................................................................. 412
5.3.5. SampleCodefor Memory Window Calculation ................................................ 415

5.4. GPCS I/O mapper...................................................................................................... 416

5.4.1. GPCS control.................................................................................................... 418
5.4.2. GPCS baselow byte......................................................................................... 418
5.4.3. GPCS basehigh byte....................................................................................... 418
5.4.4. GPCS Events................................................................................................... 418

5.5. Watchdog Timer ........................................................................................................ 418

5.5.1. Watchdog Registers ......................................................................................... 420

5.6. PWM generator.......................................................................................................... 424
5.7. Z-tag Overview .......................................................................................................... 428
5.8. Boot Parameters Register ......................................................................................... 431

5.8.1. Special Notes of Interest................................................................................... 434
5.8.2. Design Example................................................................................................ 435
5.8.3. Clocking and Control Overview ........................................................................ 437

5.9. Data registers (F0H to FEH) ...................................................................................... 438
5.10. BUR Base Register.................................................................................................. 439
5.11. System Clocking ...................................................................................................... 441

5.11.1. mhz_14c [AF16].............................................................................................. 442
5.11.2. 32KHZC_C [AF01].......................................................................................... 443
5.11.3. SYSCLK_C [A20]............................................................................................ 444
5.11.4. USB_48MHz_C [AE15]................................................................................... 447
5.11.5. PCI Clocking ................................................................................................... 448

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