WR (START CONVERSION)

BUSY (END OF CONVERSION)

(LSB)

RD (OUTPUT ENABLE)

CLOCK

EXT

REF

OUT

(MSB)

GROUND

(+5V)

WR (START CONVERSION)

BUSY (END OF CONVERSION)

(LSB)

RD (OUTPUT ENABLE)

CLOCK

EXT

REF

OUT

(MSB)

GROUND

(+5V)

C to +70

0.5

ZN448/ZN449

8-BIT MICROPROCESSOR COMPATIBLE A-D CONVERTER

DS3013 - 2.2

The ZN448 and ZN449 are 8-bit successive

approximation A-D converters designed to be easily
interfaced to microprocessors. All active circuitry is contained
on-chip including a clock generator and stable 2.5V bandgap
reference, control logic and double buffered latches with
reference.

Only a reference resistor and capacitor, clock resistor and

capacitor and input resistors are required for operation with
either unipolar or bipolar input voltage.

FEATURES

Easy Interfacing to Microprocessor, or operates as a
'Stand-Alone' Converter

Fast: 9 microseconds Conversion time Guaranteed

Choice of Linearity: 0.5 LSB - ZN448, 1 LSB - ZN449

On-Chip Clock

Choice of On-Chip or External Reference Voltage

Unipolar or Bipolar Input Ranges

Commercial Temperature Range

ORDERING INFORMATION

Device type

ZN448E

ZN449D

ZN449E

Package

DP18

MP18

DP18

Operating

temperature

Linearity

error (LSB)

ZN448/9E (DP18)

ZN449D (MP18)

Fig.1 Pin connection - top view

Fig.2 System diagram

SUCCESSIVE

APPROXIMATION REGISTER

3-STATE BUFFERS

8-BIT DAC

2.5V

REFERENCE

CLOCK

GENERATOR

INTERFACE

AND

CONTROL

LOGIC

CK RC OR
EXT CLOCK

REXT

BUSY

DB0

DB7

VCC (+5V)

GROUND

VREF OUT

VREF IN

ANALOGUE

INPUT

COMPARATOR

ZN448/9

DP package

REF

= 2.560V

MP package
DP package
V

REF

= 2.560V

= +3V, R

EXT

= 82k

V - = -5V

REF

= 390

REF

= 4

ABSOLUTE MAXIMUM RATINGS

Supply voltage V

Max. voltage, logic and V

REF

input

Operating temperature range

C to +70

C (MP and DP package)

Storage temperature range

-55

C to +125

-
-

2.545

-
-

2.542

-
-
-
-

4.5

-
-

-3

-0.5

2.520
2.520

-
-

2.550

-
-

12
15

2.550

2.5

125

100

-5

2.550
2.550

0.5

0.75

2.555

17
20

2.558

-
-
-
-
-

5.5

200

-
-

150

-30

+3.5

2.580
2.600

Min.

Typ.

Max.

LSB
LSB

mV
mV

bits

ppm/

V
V

ppm/

Parameter

Units

Conditions

ELECTRICAL CHARACTERISTICS

(at V

= 5V, T

amb

= 25

C and f

CLK

= 1.6MHz unless otherwise specified).

ZN448
Linearity error
Differential linearity error
Zero transition
(00000000

00000001)

Full-scale

transition

(11111110 11111111)

ZN449
Linearity error
Differential linearity error
Zero transition
(00000000

00000001)

Full-scale

transition

(11111110 11111111)

All Types
Resolution
Linearity temperature coefficient
Differential linearity temperature coefficient
Full-scale temperature coefficient
Zero temperature coefficient
Reference input range
Supply voltage
Supply current
Power consumption

Comparator
Input current
Input resistance
Tail current
Negative supply
Input voltage

On-chip reference
Output voltage

ZN448
ZN449

Slope resistance
V

REF

temperature coefficient

Reference current

ZN448/9

ELECTRICAL CHARACTERISTICS

(Cont.)

= +4V, V

= MAX

= +0.8V, V

= MAX

= +2.4V, V

= MAX

= +0.4V, V

= MAX

= +2.4V, V

= MAX

= +0.4V, V

= MAX

= +2.4V, V

= MAX

= +0.4V, V

= MAX

OUT

= +2V

-
-
-

0.9

500

-
-
-

2.4

-
-
-
-
-
-

180

60
80
60

200

+0.5

-
-
-
-
-
-
-

-
-

300

-
-

+150

-300

-
-
-
-
-
-

180
210

110

-
-

2
1

-
-

0.8

800

-500

0.8

-
-

0.8

-
-
-

0.4

-100

1.6

-1.5
250
260
100
140
100

250

Min.

Typ.

Max.

MHz

V
V

ns
ns
ns
ns
ns
ns
ns

Parameter

Units

Conditions

Clock
On-chip clock frequency
Clock frequency temperature coefficient
Clock resistor
Maximum external clock frequency
Clock pulse width
High level input voltage V

Low level input voltage V

High level input current I

Low level input current I

Logic (over operating temperature range)
Convert input
High level input voltage V

Low level input voltage V

High level input current I

Low level input current I

input

High level input voltage V

Low level input voltage V

High level input current I

Low level input current I

High level output voltage V

Low level output voltage V

High level output current I

Low level output current I

Three-state disable output leakage
Input clamp diode voltage

input to data output

Enable/disable delay times T

Convert pulse width t

input to

BUSY

output

GENERAL CIRCUIT OPERATION

The ZN448/9 utilises the successive approximation
technique. Upon receipt of a negative-going pulse at the

input the

BUSY

output goes low, the MSB is set to 1 and all

other bits are set to 0, which produces an output voltage of
V

REF/2

from the DAC. This is compared to the input voltage V

;

a decision is made on the next negative clock edge to reset the

MSB to 0 if < V

or leave it set to 1 if < V

Bit 2 is set to 1 on the same clock edge, producing an output

from the DAC of or + depending on the state

of the MSB. This voltage is compared to V

and on the next

clock edge a decision is made regarding bit 2, whilst bit 3 is set
to 1. This procedure is repeated for all eight bits. On the eighth
negative clock edge

BUSY

goes high indicating that the

conversion is complete.

REF

During a conversion the RD input will normally be held high to
keep the three-state buffers in their high impedance state.
Data can be read out by taking

low, thus enabling the

three-state output. Readout is non-destructive.

CONVERSION TIMING

The ZN448/9 will accept a low-going CONVERT pulse, which
can be completely asynchronous with respect to the clock,
and will produce valid data between 7.5 and 8.5 clock pulses
later depending on the relative timing of the clock and
CONVERT signals. Timing diagrams for the conversion are
shown in Fig.3.

The converter is cleared by a low-going CONVERT pulse,
which sets the most significant bit and results all the other bits
and the

BUSY

flag. Whilst the CONVERT input is low the MSB

output of the DAC is continuously compared with the analogue
input, but otherwise the converter is inhibited.

ZN448/9

After the CONVERT input goes high again the MSB decision
is made and the successive approximation routine runs to
completion.

The CONVERT pulse can be as short as 200ns; however the
MSB must be allowed to settle for at least 550ns before the
MSB decision is made. To ensure that this criterion is met
even with short CONVERT pulses the converter waits, after
the CONVERT input goes high, for a rising clock edge followed
by a falling clock edge, the MSB decision being taken on the
falling clock edge. This ensures that the MSB is allowed to
settle for at least half a clock period, or 550ns at maximum

clock frequency. The CONVERT input is not locked out during
a conversion and if it is oulsed low at any time the converter
will restart.

The

BUSY

output goes high simultaneously with the LSB

decision, at the end of a conversion indicating data valid. Note
that if the three-state data outputs are enabled during a
conversion the valid data will be available at the outputs after
the rising edge of the

BUSY

signal. If, however the outputs are

not enabled until after

BUSY

goes high then the data will be

subject to the propagation delay of the three-state buffers.
(See under DATA OUTPUTS).

Fig.3 ZN448/9 timing diagram

ZN448/9

If a free-running conversion is required, then the converter can
be made to cycle by inverting the

BUSY

output and feeding it

. To ensure that the converter starts reliably after power-

up an initial start pulse is required. This can be ensured by
using a NOR gate instead of an inverter and feeding it with a
positive-going pulse which can be derived from a simple RC
network that gives a single pulse when power is applied, as
shown in Fig.4a.

The ADC will complete a conversion on every eighth clock
pulse, with the

BUSY

output going high for a period

determined by the propagation delay of the NOR gate, during

which time the data can be stored in a latch. The time available
for storing data can be increased by inserting delays into the
inverter path.

A timing diagram for the continuous conversion mode is
shown in Fig.3b.

As the

BUSY

output uses a passive pull-up the rise time of this

output depends on the RC time constant of the pull-up resistor
and load capacitance. In the continuous conversion mode the
use of a 4k7 external pull-up resistor is recommended to
reduce the risetime and ensure that a logic 1 level is reached.

Fig.4b Timing for continuous conversion

DATA OUTPUTS

The data outputs are provided with three-state buffers to allow
connection to a common data bus. An equivalent circuit is
shown in Fig.5. Whilst the

input is high both output

transistors are turned off and the ZN448/9 presents only a high
impedance load to the bus.

When

is low the data outputs will assume the logic states

present at the outputs of the successive register.

A test circuit and timing diagram for the output enable/disable
delays are given in Fig.6.

Fig.4a Circuit for continuous conversion

ZN448/9

Fig.8 Clock circuit external components

BUSY

OUTPUT

The

BUSY

output, shown in Fig.7, utilises a passive pull-up for

CMOS/TTL compatibility. This allows up to four

BUSY

outputs

to be wire-ANDed together to form a common interrupt line.

Fig.7

BUSY

output

ON-CHIP CLOCK

The on-chip clock operates with only a single external
capacitor connected between pin 3 and ground, as shown in
Fig.8a. A graph of typical oscillator frequency versus
capacitance is given in Fig.9. The oscillator frequency may be
trimmed by means of an external resistor in series with the
capacitor, as shown in Fig.8b. However, due to processing
tolerance, the absolute clock frequency may vary

considerably between devices. For optimum accuracy and
stability of the oscillator frequency, it may be possible to use
a crystal or ceramic resonator with suitable load components,
as shown in Fig.8c. The final option is to overdrive the
oscillator input with an external clock signal from a TTL or
CMOS gate, as shown in Fig.8d.

OSC

GND

MAX

1.2k

VCC

Xtal

1MHz

56pF

2200pF

4.7k

Load circuit to suit

device used

a) Fixed/variable capacitor

b) Fixed capacitor + variable resistor

c) Crystal or resonator

d) External TTL or CMOS drive

ZN448/9

Fig.10 R-2R ladder network

Fig.9 Typical clock frequency v C

= 0)

1MHz

100kHz

10kHz

1kHz

10p

100p

10n

100n

ANALOG CIRCUITS

D-A converter
The converter is of the voltage switching type and uses an R-
2R ladder network as shown in Fig.10. Each element is
connected to either 0V or V

REF IN

by transistor voltage switches

specially designed for low offset voltage (1mV).

A binary weighted voltage is produced at the output of the R-
2R ladder.

D to A output = n (V

REF IN

-V

) + V

256
where n is the digital input to the D-A from the successive
approximation register.

is a small offset voltage that is produced by the device

supply current flowing in the package lead resistance. The
offset will normally be removed by the setting up procedure
and since the offset temperature coefficient is low (8

the effect on accuracy will be neglible.

The D-A output range can be considered to be 0 - V

REF IN

through an output resistance R (4k).

R(4k)

D TO A OUTPUT

DB6

DB0

VOS

DB1

DB7

0 VOLTS
(PIN 9)

VREF IN
(PIN 7)

VOLTAGE

SWITCHES

ZN448/9

REFERENCE
(a) Internal reference
The internal reference is an active bandgap circuit which is
equivalent to a 2.5V Zener diode with a very low slope
impedance (Fig.11). A Resistor (R

REF

) should be connected

between pins 8 and 10.

The recommended value of 390

will supply a nominal

reference current of (5 - 2.5)/0.39=6.4mA. A stabilising/
decoupling capacitor, C

REF

7), is required between pins 8

and 9. For internal reference operation V

REF OUT

(pin 8) is

connected to V

REF IN

(pin 7).

UP to five ZN448/9's may be driven from one internal
reference, there being no need to reduce R

REF

. This useful

feature saves power and gives excellent gain tracking
between the converters.

Alternatively the internal reference can be used as the
reference voltage for other external circuits and can source or
sink up to 3mA.

(b) External reference
If required an external reference in the range +1.5 to +3.0V
may be connected to V

REF IN

. The slope resistance of such a

reference source should be less than 2.5

, where n is the

number of converters supplied.

GROUND

(PIN 9)

CREF

(0.47µ)

RREF

(390)

VREFOUT

(PIN 8)

VCC +5V

(PIN 10)

Fig.11 Internal voltage reference

RATIOMETRIC OPERATION

If the output from a transducer varies with its supply then an
external reference for the ZN4448/9 should be derived from
the same supply. The external reference can vary from +1.5
to +3.0V. The ZN448/9 will operate if V

REF IN

is less than +1.5V

but reduced overdrive to the comparator will increase its delay
and so the conversion time will need to be increased.

COMPARATOR

The ZN448/9 contains a fast comparator, the equivalent input
circuit of which is shown in Fig.12. A negative supply voltage
is required to supply the tail current of the comparator.
However as this is only 25 to 150

A and need not be well

stabilised it can be supplied by a simple diode pump circuit
driven from the

BUSY

output.

ZN448/9

Several suitable circuits are shown in Fig.13. The principle of
operation is the same in each case. Whilst the

BUSY

output

is high, capacitor C1 is charged to about 4-4.5V. During a
conversion the

BUSY

output goes low and the upper end of C1

is thus also pulled low. The lower end of C1 therefore applies
about -4V to R2, thus providing the tail current for the
comparator. The time constant R2. C1 is chosen according
to the clock frequency so that droop of the capacitor voltage is
not significant during a conversion.

The constraint on using this type of circuit is that C1 must be
recharged whilst the

BUSY

output is high. If the

BUSY

output

is high for greater than one converter clock period then the
circuit of Fig.13a will suffice. If this is not the case, for example,
in the continuous conversion mode, then the circuits of Figs.
13b and 13c are recommended, since these can pump more
current into the capacitor.

Where several ZN448/9's are used in a system the self-
oscillating diode pump circuit Fig.14 is recommeded.
Alternatively, if a negative supply is available in the system
then this may be utilised. A list of suitable resistor values for
different supply voltages is given in Table 1.

Fig.14 Diode pump circuit to supply comparator tail current for up to five ZN448/9's

22n

330

470

100n

IN914

-3.5V

V (volts)

3
5
10
12
15
20
25
30

EXT

)

47
82
150
180
220
330
390
470

Table 1

ZN448/9

ANALOG INPUT RANGES

The basic connection of the ZN448/9 shown in Fig.15 has an
analogue input range 0 to V

REF IN

which, in some applications,

may be made available from previous signal conditioning/
scaling circuits. Input voltage ranges greater than this are
accommodated by providing an attenuator on the comparator
input, whilst for smaller input ranges the signal must be
amplified to a suitable level.

Bipolar input ranges are accommodated by off-setting the
analogue input input range so that the comparator always
sees a positive input voltage.

Fig.15 External components for basic operation

LSB

DB0

MSB

DB7

VCC

(+5V)

BUSY

V-

(-5V)

AIN

VREFIN

VREFOUT

GND

(0V)

RREF

(390

)

REXT

(82k)

RIN
(4k)

VIN

CREF

(4µ7)

DIGITAL OUTPUTS

NOMINAL AIN RANGE = 0 TO VREFIN

ZN448/9

UNIPOLAR OPERATION

The general connection for unipolar operation is shown in
Fig.16.

The values of R

and R

are chosen so that V

= V

REF IN

when

the analog input (A

) is at full-scale.

The resulting full-scale range is given by:

FS = 1 + , V

REF IN

= G.V

REF IN

To match the ladder resistance R

) = 4k.

The required nominal values of R

and R

are given by R

4Gk, R

= 4G k

G-1

Fig.16 General unipolar input connections

680k

ZERO

ADJUST

GROUND

ZN448/9

VIN

AIN

VREF IN

Using these relationships a table of nominal values of R

and

can be constructed for V

REF IN

= 2.5V.

Gain adjustment
Due to tolerance in R

and R

, tolerance in V

REF

and the gain

(full-scale) error of the DAC, some adjustment should be
incorporated into R

to calibrate the full-scale of the converter.

When used with the internal reference and 2% resistors a
preset capable of adjusting R

by at least

5% of its nominal

value is suggested.

5.33k

16k

2
4

Input range

+5V

+10V

Zero adjustment
Due to offsets in the DAC and comparator the zero (0 to 1)
code transition would occur with typically 15mV applied to the
comparator input, which correpsonds to 1.5LSB with a 2.56V
reference.

Zero adjustment must therefore be provided to set the zero
transition to its correct value of +0.5LSB or 5mV with a 2.56V
reference. This is achieved by applying an adjustable positive
offset to the comparator input via P2 and R3. The values
shown are suitable for all input ranges greater than 1.5 times
V

REF IN

Practical circuit values for +5 and +10V input ranges are given
in Fig.17, which incorporates both zero and gain adjustments.

ZN448/9

Fig.17 Unipolar operation component values

AIN

VREF IN

TO PIN 6

R1 11k

R2 5k6

680k

P1 10k

GAIN

ADJUST

ZERO

ADJUST

± 2% RESISTORS

±20% POTENTIOMETERS

AIN

VREF IN

TO PIN 6

R1 5k6

R2 8k2

680k

P1 5k

GAIN

ADJUST

ZERO

ADJUST

+5V FULL-SCALE

+10V FULL-SCALE

Unipolar adjustment prodedure

(i) Apply continuous convert pulses at intervals long enough

to allow a complete conversion and monitor the digital
outputs.

(ii) Apply full-scale minus 1.5LSB to A

and adjust off-set until

the bit 8 (LSB) output just flickers between 0 and 1 with all
other bits at 0.

(iii) Apply 0.5LSB to A

and adjust zero until 8 bit just flickers

between 0 and 1 with all other bits at 1.

Unipolar setting up points

FS - 1.5LSB

4.9707V
9.9414V

1LSB = FS
256

Input range, +FS

+5V

+10V

0.5LSB

9.8mV

19.5mV

Bipolar logic coding

Analogue input (A

)

(Nominal code centre value)

FS - 1LSB
FS - 2LSB
0.75FS
0.5FS + 1LSB
0.5FS
0.5FS - 1LSB
0.25FS
1LSB
0

Output code

(offset binary)

11111111
11111110
11000000
10000001
10000000
01111111
01000000
00000001
00000000

ZN448/9

BIPOLAR OPERATION

For bipolar operation the input to the ZN448/9 is offset by half
full-scale by connecting a resistor R

between V

REF IN

and V

(Fig.18).

Fig.18 Basic bipolar input connection

GROUND

ZN448/9

VIN

AIN

VREF IN

When A

= -FS, V

needs to be equal to zero.

When A

= +FS, V

needs to be equal to V

REF IN

If the full-scale range is

G. V

REF IN

then R

= (G - 1). R

and

= G. R

fulfil the required conditions.

To match the ladder resistance, R

(=R

) = 4k.

Thus the nominal values of R

, R

are given by R

= 8 Gk,

= 8G/(G - 1)k, R

= 8k.

A bipolar range of

REF IN

(which corresponds to the basic

unipolar range 0 to +V

REF IN

) results if R

= R

= 8k and R

Assuming the V

REF IN

= 2.5V the nominal values of resistors for

5 and

10V input ranges are given in the following table.

16k

10.66k

16k
32k

2
4

Input range

+5V

+10V

Minus full-scale (offset) is set by adjusting R

about its nominal

value relative to R

. Plus full-scale (gain) is set by adjusting R

relative to R

Practical circuit realisations are given in Fig.19.

8k
8k

Note that in the

5V case R

has been chosen as 7.5k (instead

of 8.2k) to obtain a more symmetrical range of adjustment
using standard potentiometers.

ZN448/9

Fig.19 Bipolar operation component values

AIN

VREF

TO PIN 6

13k

7k5

OFFSET
ADJUST

13k

GAIN

ADJUST

± 2% RESISTORS

±20% POTENTIOMETERS

±5VOLTS FULL SCALE

AIN

VREF

TO PIN 6

27k

8k2

10k

OFFSET
ADJUST

8k2

GAIN

ADJUST

±10VOLTS FULL SCALE

Bipolar adjustment prodedure

(i) Apply continuous SC pulses at intervals long enough to

allow a complete conversion and monitor the digital
outputs.

(ii) Apply -(FS -0.5LSB) to A

and adjust off-set until the bit 8

(LSB) output just flickers between 0 and 1 with all other bits
at 0.

(iii) Apply +(FS -1.5LSB) to A

and adjust gain until the 8 bit

just flickers between 0 and 1 with all other bits at 1.

(iv) Repeat step (ii).

Bipolar setting up points

+(FS -1.5LSB)

+4.9414V
+9.8828V

1LSB =2FS
256

Input range,

+5V

+10V

-(FS -0.5LSB)

-4.9805V
-9.9609V

Bipolar logic coding

Analogue input (A

)

(Nominal code centre value)

+(FS - 1LSB)
+(FS - 2LSB)
+0.5FS
+1LSB
0
-1LSB
-0.5FS
-(FS - 1LSB)
-FS

Output code

(offset binary)

11111111
11111110
11000000
10000001
10000000
01111111
01000000
00000001
00000000

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