Et r onT ech
EM636165
Etron Technology, Inc.
No. 6, Technology Road V, Science-Based Industrial Park, Hsinchu, Taiwan 30077, R.O.C.
TEL: (886)-3-5782345
FAX: (886)-3-5778671
Etron Technology, Inc., reserves the right to make changes to its products and specifications without notice.
1Mega x 16 Synchronous DRAM (SDRAM)
Preliminary (Rev. 1.8, 11/2001)
Features
Fast access time: 4.5/5/5/5.5/6.5/7.5 ns
Fast clock rate: 200/183/166/143/125/100 MHz
Self refresh mode: standard and low power
Fully synchronous operation
Internal pipelined architecture
512K x 16 bit x 2-bank
Programmable Mode registers
- CAS# Latency: 1, 2, or 3
- Burst Length: 1, 2, 4, 8, or full page
- Burst Type: interleaved or linear burst
- Burst stop function
Individual byte controlled by LDQM and UDQM
Auto Refresh and Self Refresh
4096 refresh cycles/64ms
CKE power down mode
Single +3.3V
0.3V power supply
Interface: LVTTL
50-pin 400 mil plastic TSOP II package
60-Ball, 6.4 mm x 10.1 mm VFBGA package
(Max total package height=1.0 mm)
Pin Assignment (Top View)
Key Specifications
EM636165
-5/55/6/7/7L/8/10
t
CK3
Clock Cycle time(min.)
5/5.5/6/7/7/8/10 ns
t
RAS
Row Active time(max.)
30/32/36/42/42/48/60 ns
t
AC3
Access time from CLK
(max.)
4.5/5/5/5.5/5.5/6.5/7.5 ns
t
RC
Row Cycle time(min.)
48/48/54/63/63/72/90 ns
Ordering Information
1. Operating temperature : 0~70
C
Part Number
Frequency
Package
EM636165TS/VE-5
200MHz
TSOP II ,VFBGA
EM636165TS/VE-55
183MHz
TSOP II ,VFBGA
EM636165TS/VE -6
166MHz
TSOP II ,VFBGA
EM636165TS/VE -7
143MHz
TSOP II ,VFBGA
EM636165TS/VE-7L 143MHz TSOP
II,VFBGA
EM636165TS/VE -8
125MHz
TSOP II,VFBGA
EM636165TS/VE -10
100MHz
TSOP II,VFBGA
2. Industrial Operating temperature : -40~85
C
Part Number
Frequency
Package
EM636165TS/VE -10
I
100MHz TSOP
II,VFBGA
V
DD
DQ 0
DQ 1
V
S SQ
DQ 2
DQ 3
V
DDQ
DQ 4
DQ 5
V
S SQ
DQ 6
DQ 7
V
DDQ
L D Q M
WE#
CA S#
RA S#
CS #
A 1 1
A 1 0
A 0
A 1
A 2
A 3
V
DD
Vss
D Q 1 5
D Q 1 4
V
S SQ
D Q 1 3
D Q 1 2
V
DDQ
D Q 1 1
D Q 1 0
V
S SQ
DQ 9
DQ 8
V
DDQ
NC
UD QM
CL K
CKE
NC
A 9
A 8
A 7
A 6
A 5
A 4
Vss
1
2
3
4
5
6
7
8
9
1 0
1 1
1 2
1 3
1 4
1 5
1 6
1 7
1 8
1 9
2 0
2 1
2 2
2 3
2 4
2 5
5 0
4 9
4 8
4 7
4 6
4 5
4 4
4 3
4 2
4 1
4 0
3 9
3 8
3 7
3 6
3 5
3 4
3 3
3 2
3 1
3 0
2 9
2 8
2 7
2 6
A
B
C
D
E
F
G
H
V D D
N C
A 5
A 7
V S S
A 8
D Q 6
D Q 7
C L K
D Q 8
D Q 9
D Q 3
D Q 1
N C
D Q 1 5
D Q 1 4
D Q 1 2
V D D Q
D Q 4
V D D Q
D Q 1 1
V D D Q
D Q 5
V S S Q
U D Q M
V S S Q
D Q 1 0
V S S Q
A 6
V D D
C K E
A 9
A 0
A 1 0
N C
N C
V S S Q
D Q 1 3
N C
N C
N C
A 1 1
V S S
A 4
N C
N C
V D D Q
D Q 2
N C
N C
N C
L D Q M
W E #
C A S #
R A S #
C S #
A 3
A 2
A 1
J
K
L
M
N
P
R
1
2
3
4
5
6
7
D Q 0
EtronTech
1M x 16 SDRAM
EM636165
Preliminary
2
Rev. 1.8
Nov 2001
Overview
The EM636165 SDRAM is a high-speed CMOS synchronous DRAM containing 16 Mbits. It is internally configured
as a dual 512K x 16 bit DRAM with a synchronous interface (all signals are registered on the positive edge of the clock
signal, CLK). Each of the 512K x 16 bit bank is organized as 2048 rows by 256 columns by 16 bits. Read and write
accesses to the SDRAM are burst oriented; accesses start at a selected location and continue for a programmed number
of locations in a programmed sequence.
The EM636165 provides for programmable Read or Write burst lengths of 1, 2, 4, 8, or full page, with a burst
termination option. An auto precharge function may be enabled to provide a self-timed row precharge that is initiated at
the end of the burst sequence. The refresh functions, either Auto or Self Refresh are easy to use. By having a
programmable mode register, the system can choose the most suitable modes to maximize its performance. These
devices are well suited for applications requiring high memory bandwidth and particularly well suited to high performance
PC applications.
Block Diagram
REFRESH
COUNTER
COLUMN
COUNTER
ADDRESS
BUFFER
A0
A11
CONTROL
SIGNAL
GENERATOR
LDQM
UDQM
CLOCK
BUFFER
COMMAND
DECODER
Column Decoder
Sense Amplifier
Row Decoder
2048 X 256 X 16
CELL ARRAY
(BANK #0)
Sense Amplifier
Column Decoder
Row Decoder
2048 X 256 X 16
CELL ARRAY
(BANK #1)
CLK
CKE
CS#
RAS#
CAS#
WE#
DQ0
D
DQ15
DQs Buffer
MODE
REGISTER
EtronTech
1M x 16 SDRAM
EM636165
Preliminary
3
Rev. 1.8
Nov 2001
Pin Descriptions
Table 1. Pin Details of EM636165
Symbol Type
Description
CLK Input
Clock: CLK is driven by the system clock. All SDRAM input signals are sampled
on the positive edge of CLK. CLK also increments the internal burst counter and
controls the output registers.
CKE Input
Clock Enable: CKE activates(HIGH) and deactivates(LOW) the CLK signal. If
CKE goes low synchronously with clock(set-up and hold time same as other
inputs), the internal clock is suspended from the next clock cycle and the state of
output and burst address is frozen as long as the CKE remains low. When both
banks are in the idle state, deactivating the clock controls the entry to the Power
Down and Self Refresh modes. CKE is synchronous except after the device
enters Power Down and Self Refresh modes, where CKE becomes
asynchronous until exiting the same mode. The input buffers, including CLK, are
disabled during Power Down and Self Refresh modes, providing low standby
power.
A11 Input
Bank Select: A11(BS) defines to which bank the BankActivate, Read, Write, or
BankPrecharge command is being applied.
A0-A10 Input
Address Inputs: A0-A10 are sampled during the BankActivate command (row
address A0-A10) and Read/Write command (column address A0-A7 with A10
defining Auto Precharge) to select one location out of the 256K available in the
respective bank. During a Precharge command, A10 is sampled to determine if
both banks are to be precharged (A10 = HIGH). The address inputs also provide
the op-code during a Mode Register Set command.
CS# Input
Chip Select: CS# enables (sampled LOW) and disables (sampled HIGH) the
command decoder. All commands are masked when CS# is sampled HIGH.
CS# provides for external bank selection on systems with multiple banks. It is
considered part of the command code.
RAS# Input
Row Address Strobe: The RAS# signal defines the operation commands in
conjunction with the CAS# and WE# signals and is latched at the positive edges
of CLK. When RAS# and CS# are asserted "LOW" and CAS# is asserted
"HIGH," either the BankActivate command or the Precharge command is
selected by the WE# signal. When the WE# is asserted "HIGH," the
BankActivate command is selected and the bank designated by BS is turned on
to the active state. When the WE# is asserted "LOW," the Precharge command
is selected and the bank designated by BS is switched to the idle state after the
precharge operation.
CAS#
Input
Column Address Strobe: The CAS# signal defines the operation commands in
conjunction with the RAS# and WE# signals and is latched at the positive edges
of CLK. When RAS# is held "HIGH" and CS# is asserted "LOW," the column
access is started by asserting CAS# "LOW." Then, the Read or Write command
is selected by asserting WE# "LOW" or "HIGH."
WE# Input
Write Enable: The WE# signal defines the operation commands in conjunction
with the RAS# and CAS# signals and is latched at the positive edges of CLK.
The WE# input is used to select the BankActivate or Precharge command and
Read or Write command.
LDQM,
UDQM
Input
Data Input/Output Mask: LDQM and UDQM are byte specific, nonpersistent
I/O buffer controls. The I/O buffers are placed in a high-z state when
LDQM/UDQM is sampled HIGH. Input data is masked when LDQM/UDQM is
sampled HIGH during a write cycle. Output data is masked (two-clock latency)
when LDQM/UDQM is sampled HIGH during a read cycle. UDQM masks DQ15-
DQ8, and LDQM masks DQ7-DQ0.
EtronTech
1M x 16 SDRAM
EM636165
Preliminary
4
Rev. 1.8
Nov 2001
DQ0-DQ15 Input/Output Data I/O: The DQ0-15 input and output data are synchronized with the positive
edges of CLK. The I/Os are byte-maskable during Reads and Writes.
NC -
No Connect: These pins should be left unconnected.
V
DDQ
Supply
DQ Power: Provide isolated power to DQs for improved noise immunity.
( 3.3V
0.3V )
V
SSQ
Supply
DQ Ground: Provide isolated ground to DQs for improved noise immunity.
( 0 V )
V
DD
Supply
Power Supply: +3.3V
0.3V
V
SS
Supply
Ground
EtronTech
1M x 16 SDRAM
EM636165
Preliminary
5
Rev. 1.8
Nov 2001
Operation Mode
Fully synchronous operations are performed to latch the commands at the positive edges of CLK.
Table 2 shows the truth table for the operation commands.
Table 2. Truth Table (Note (1), (2) )
Command State
CKE
n-1
CKE
n
DQM
(6)
A11 A
10
A
0-9
CS# RAS# CAS# WE#
BankActivate
Idle
(3)
H X X V
V
V L L H H
BankPrecharge
Any H X X V
L
X
L
L H L
PrechargeAll
Any H X X X
H
X
L
L H L
Write
Active
(3)
H X X V L V L H L L
Write and AutoPrecharge
Active
(3)
H X X V H V L H L L
Read
Active
(3)
H X X V L V L H L H
Read and Autoprecharge
Active
(3)
H X X V H V L H L H
Mode Register Set
Idle H X X V
V
V
L
L L L
No-Operation
Any H X X X
X
X
L
H H
H
Burst Stop
Active
(4)
H X X X X X L H H L
Device Deselect
Any H X X X
X
X
H X X X
AutoRefresh
Idle H H X X
X
X
L
L L
H
SelfRefresh Entry
Idle H L X X
X
X
L
L L
H
SelfRefresh Exit
Idle L H X X
X
X
H X X X
(SelfRefresh)
L
H
H
H
Clock Suspend Mode Entry
Active H L X X
X
X
X X X X
Power Down Mode Entry
Any
(5)
H L X X
X
X
H X X X
L
H
H
H
Clock Suspend Mode Exit
Active L H X X
X
X
X X X X
Power Down Mode Exit
Any L H X X
X
X
H X X X
(PowerDown)
L
H
H
H
Data Write/Output Enable
Active H X L X
X X X X X X
Data Mask/Output Disable
Active H X H X
X X X X X X
Note: 1. V=Valid X=Don't Care L=Low level H=High level
2. CKE
n
signal is input level when commands are provided.
CKE
n-1
signal is input level one clock cycle before the commands are provided.
3. These are states of bank designated by BS signal.
4. Device state is 1, 2, 4, 8, and full page burst operation.
5. Power Down Mode can not enter in the burst operation.
When this command is asserted in the burst cycle, device state is clock suspend mode.
6. LDQM and UDQM
PDF 
ZIP