Et r onT ech
EM658160
Etron Technology, Inc.
No. 6, Technology Rd. V, Science-Based Industrial Park, Hsinchu, Taiwan 30077, R.O.C.
TEL: (886)-3-5782345
FAX: (886)-3-5778671
Etron Technology, Inc., reserves the right to make changes to its products and specifications without notice.
4M x 16 DDR Synchronous DRAM (SDRAM)
Etron Confidential
(Rev. 1.1 Jan./2002)
Features
Fast clock rate: 300/285/250/200/166/143/125MHz
Differential Clock CK & /CK
Bi-directional DQS
DLL enable/disable by EMRS
Fully synchronous operation
Internal pipeline architecture
Four internal banks, 1M x 16-bit for each bank
Programmable Mode and Extended Mode registers
- /CAS Latency: 2, 2.5, 3
- Burst length: 2, 4, 8
- Burst Type: Sequential & Interleaved
Individual byte write mask control
DM Write Latency = 0
Auto Refresh and Self Refresh
4096 refresh cycles / 64ms
Precharge & active power down
Power supplies: V
DD
= 3.3V
0.3V
V
DDQ
= 2.5V
0.2V
Interface: SSTL_2 I/O Interface
Package: 66 Pin TSOP II, 0.65mm pin pitch
Ordering Information
Part Number
Frequency
Package
EM658160TS-3.3
300MHz
TSOP II
EM658160TS-3.5
285MHz
TSOP II
EM658160TS-4
250MHz
TSOP II
EM658160TS-5
200MHz
TSOP II
EM658160TS-6
166MHz
TSOP II
EM658160TS-7
143MHz
TSOP II
EM658160TS-8
125MHz
TSOP II
Overview
Pin Assignment (Top View)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
VDD
DQ0
VDDQ
DQ1
DQ2
VSSQ
DQ3
DQ4
VDDQ
DQ5
DQ6
VSSQ
DQ7
NC
VDDQ
LDQS
NC
VDD
NC
LDM
/WE
/CAS
/RAS
/CS
NC
BS0
BS1
A10/AP
A0
A1
A2
A3
VDD
VSS
DQ15
VSSQ
DQ14
DQ13
VDDQ
DQ12
DQ11
VSSQ
DQ10
DQ9
VDDQ
DQ8
NC
VSSQ
UDQS
NC
VREF
VSS
UDM
/CK
CK
CKE
NC
NC
A11
A9
A8
A7
A6
A5
A4
VSS
The EM658160 SDRAM is a high-speed CMOS
double data rate synchronous DRAM containing 64
Mbits. It is internally configured as a quad 1M x 16
DRAM with a synchronous interface (all signals are
registered on the positive edge of the clock signal, CK).
Data outputs occur at both rising edges of CK and /CK.
Read and write accesses to the SDRAM are burst
oriented; accesses start at a selected location and
continue for a programmed number of locations in a
programmed sequence. Accesses begin with the
registration of a BankActivate command which is then
followed by a Read or Write command. The EM658160
provides programmable Read or Write burst lengths of 2,
4, 8, full page.
An auto precharge function may be enabled to
provide a self-timed row precharge that is initiated at the
end of the burst sequence. The refresh functions, either
Auto or Self Refresh are easy to use. In addition,
EM658160 features programmable DLL option. By
having a programmable mode register and extended
mode register, the system can choose the most suitable
modes to maximize its performance. These devices are
well suited for applications requiring high memory
bandwidth, result in a device particularly well suited to
high performance main memory and graphics
applications.
Et r onT ech
4Mx16 DDR SDRAM
EM658160
Etron Confidential
2
Rev. 1.1
Jan. 2002
Block Diagram
REFRESH
COUNTER
COLUMN
COUNTER
ADDRESS
BUFFER
A0
A11
BS0
BS1
CONTROL
SIGNAL
GENERATOR
LDM, UDM
DLL
CLOCK
BUFFER
COMMAND
DECODER
Column Decoder
Sense Amplifier
Row Decoder
1MX16
CELL ARRAY
(BANK #0)
Sense Amplifier
Column Decoder
Row Decoder
1MX16
CELL ARRAY
(BANK #3)
MODE
REGISTER
CK
/CK
CKE
/CS
/RAS
/CAS
/WE
A10/AP
DQ0
D
DQ15
Sense Amplifier
Column Decoder
Row Decoder
1MX16
CELL ARRAY
(BANK #1)
Sense Amplifier
Column Decoder
Row Decoder
1MX16
CELL ARRAY
(BANK #2)
LDQS,
UDQS
DATA
STROBE
BUFFER
DQ
BUFFER
Et r onT ech
4Mx16 DDR SDRAM
EM658160
Etron Confidential
3
Rev. 1.1
Jan. 2002
Pin Descriptions
Table 1. Pin Details of EM658160
Symbol
Type
Description
CK, /CK
Input
Differential Clock: CK, /CK are driven by the system clock. All SDRAM input signals
are sampled on the positive edge of CK. Both CK and /CK increment the internal burst
counter and controls the output registers.
CKE
Input
Clock Enable: CKE activates(HIGH) and deactivates(LOW) the CK signal. If CKE
goes low synchronously with clock, the internal clock is suspended from the next clock
cycle and the state of output and burst address is frozen as long as the CKE remains
low. When all banks are in the idle state, deactivating the clock controls the entry to
the Power Down and Self Refresh modes.
BS0, BS1
Input
Bank Select: BS0 and BS1 defines to which bank the BankActivate, Read, Write, or
BankPrecharge command is being applied.
A0-A11
Input
Address Inputs: A0-A11 are sampled during the BankActivate command (row
address A0-A11) and Read/Write command (column address A0-A7with A10 defining
Auto Precharge).
/CS
Input
Chip Select: /CS enables (sampled LOW) and disables (sampled HIGH) the
command decoder. All commands are masked when /CS is sampled HIGH. /CS
provides for external bank selection on systems with multiple banks. It is considered
part of the command code.
/RAS
Input
Row Address Strobe: The /RAS signal defines the operation commands in
conjunction with the /CAS and /WE signals and is latched at the positive edges of CK.
When /RAS and /CS are asserted "LOW" and /CAS is asserted "HIGH," either the
BankActivate command or the Precharge command is selected by the /WE signal.
When the /WE is asserted "HIGH," the BankActivate command is selected and the
bank designated by BS is turned on to the active state. When the /WE is asserted
"LOW," the Precharge command is selected and the bank designated by BS is
switched to the idle state after the precharge operation.
/CAS
Input
Column Address Strobe: The /CAS signal defines the operation commands in
conjunction with the /RAS and /WE signals and is latched at the positive edges of CK.
When /RAS is held "HIGH" and /CS is asserted "LOW," the column access is started
by asserting /CAS "LOW." Then, the Read or Write command is selected by asserting
/WE "HIGH " or LOW"."
/WE
Input
Write Enable: The /WE signal defines the operation commands in conjunction with
the /RAS and /CAS signals and is latched at the positive edges of CK. The /WE input
is used to select the BankActivate or Precharge command and Read or Write
command.
LDQS,
UDQS
Input /
Output
Bidirectional Data Strobe: Specifies timing for Input and Output data. Read Data
Strobe is edge triggered. Write Data Strobe provides a setup and hold time for data
and DQM. LDQS is for DQ0~7, UDQS is for DQ8~15.
LDM,
UDM
Input
Data Input Mask: Input data is masked when DM is sampled HIGH during a write
cycle. LDM masks DQ0-DQ7, UDM masks DQ8-DQ15.
DQ0 - DQ15
Input /
Output
Data I/O: The DQ0-DQ15 input and output data are synchronized with the positive
edges of CK and /CK. The I/Os are byte-maskable during Writes.
Et r onT ech
4Mx16 DDR SDRAM
EM658160
Etron Confidential
4
Rev. 1.1
Jan. 2002
V
DD
Supply
Power Supply: +3.3V
0.3V
V
SS
Supply
Ground
V
DDQ
Supply
DQ Power: +2.5V
0.2V. Provide isolated power to DQs for improved noise immunity.
V
SSQ
Supply
DQ Ground: Provide isolated ground to DQs for improved noise immunity.
V
REF
Supply
Reference Voltage for Inputs: +0.5*V
DDQ
NC
-
No Connect: These pins should be left unconnected.
Et r onT ech
4Mx16 DDR SDRAM
EM658160
Etron Confidential
5
Rev. 1.1
Jan. 2002
Operation Mode
Fully synchronous operations are performed to latch the commands at the positive edges of CK. Table 2
shows the truth table for the operation commands.
Table 2. Truth Table (Note (1), (2) )
Command
State
CKE
n-1
CKE
n
DM BS
0,1
A
10
A
0-9,11
/CS /RAS /CAS /WE
BankActivate
Idle
(3)
H
X
X
V
Row address
L
L
H
H
BankPrecharge
Any
H
X
X
V
L
X
L
L
H
L
PrechargeAll
Any
H
X
X
X
H
X
L
L
H
L
Write
Active
(3)
H
X
X
V
L
L
H
L
L
Write and AutoPrecharge
Active
(3)
H
X
X
V
H
Column
address
(A0 ~ A7)
L
H
L
L
Read
Active
(3)
H
X
X
V
L
L
H
L
H
Read and Autoprecharge
Active
(3)
H
X
X
V
H
Column
address
(A0 ~ A7)
L
H
L
H
Mode Register Set
Idle
H
X
X
OP code
L
L
L
L
Extended MRS
Idle
H
X
X
OP code
L
L
L
L
No-Operation
Any
H
X
X
X
X
X
L
H
H
H
Burst Stop
Active
(4)
H
X
X
X
X
X
L
H
H
L
Device Deselect
Any
H
X
X
X
X
X
H
X
X
X
AutoRefresh
Idle
H
H
X
X
X
X
L
L
L
H
SelfRefresh Entry
Idle
H
L
X
X
X
X
L
L
L
H
SelfRefresh Exit
Idle
L
H
X
X
X
X
H
X
X
X
(SelfRefresh)
L
H
H
H
Clock Suspend Mode Entry
Active
H
L
X
X
X
X
X
X
X
X
Power Down Mode Entry
Any
(5)
H
L
X
X
X
X
H
X
X
X
L
H
H
H
Clock Suspend Mode Exit
Active
L
H
X
X
X
X
X
X
X
X
Power Down Mode Exit
Any
L
H
X
X
X
X
H
X
X
X
(PowerDown)
L
H
H
H
Data Write/Output Enable
Active
H
X
L
X
X
X
X
X
X
X
Data Mask/Output Disable
Active
H
X
H
X
X
X
X
X
X
X
Note:
1. V=Valid data, X=Don't Care, L=Low level, H=High level
2. CKE
n
signal is input level when commands are provided.
CKE
n-1
signal is input level one clock cycle before the commands are provided.
3. These are states of bank designated by BS signal.
4. Device state is 1, 2, 4, 8, and full page burst operation.
5. Power Down Mode can not enter in the burst operation.
When this command is asserted in the burst cycle, device state is clock suspend mode.
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