EXAR Corporation, 48720 Kato Road, Fremont, CA 94538
(510) 668-7000
FAX (510) 668-7017
XR16C2852
Rev. 1.00
PLCC Package
DUAL UART WITH 128-byte FIFOs AND
RS-485 HALF DUPLEX DIRECTION CONTROL
DESCRIPTION
The XR16C2852
*1
(2852) is a dual universal asynchronous receiver and transmitter (UART). The device is
designed for high performance communication systems to provide maximum full-duplex data throughput. Each
UART provides enhanced functions with 128 byte of transmit and receive FIFOs, automatic RTS/CTS and software
flow control, programmable FIFO trigger level, automatic RS-485 half duplex transmit/receive direction control,
wireless infrared (IrDA ver 1.0) data encoder/decoder, and a modem control interface. Onboard status registers
provide the user with error indications and operational status. An alternate function register supports concurrent
write to UART A and B. System interrupts and modem control features may be tailored by software to meet user
requirements. Independent programmable baud rate generators are provided to select data rates up to 1.5 Mbps.
An internal loopback capability allows onboard diagnostics. The 2852 is available in a 44-pin PLCC package and
is pin-to-pin and functionally compatible with the ST16C2552. The device is fabricated in advanced CMOS process
to achieve low power and high speed requirements.
FEATURES
Pin and functionally compatible to ST16C2552, and
National PC16552/NS16C552
Independent channel A/B control
Up to 1.5 Mbps data rate operation
128 byte transmit FIFO to reduce CPU bandwidth
requirement
128 byte receive FIFO with error flags to reduce
CPU bandwdth requirement
Programmable transmit and receive FIFO trigger
level from 0 to 127
Automatic RTS/CTS flow control with hysteresis
Automatic software flow control
Automatic RS485 half duplex direction control on
-RTS pin.
Modem control signals (-CTS, -RTS, -DSR, -DTR,
-RI, -CD, and software controllable line break)
Infrared (IrDA ver 1.0) transmit and receive data
encoder/decoder
Device identification and revision
Standard 460.8 Kbps transmit/receive data rate
with 7.3728 MHz crystal or external clock source
+5V or 3.3V operation
Industrial and commercial temperature grades
44-pin PLCC package
ORDERING INFORMATION
Part number
Pins Package
Operating temperature
XR16C2852CJ
44
PLCC
0 C to + 70 C
XR16C2852IJ
44
PLCC
-40 C to + 85 C
6
5
4
3
2
1
44
43
42
41
40
7
8
9
10
11
12
13
14
15
16
17
39
38
37
36
35
34
33
32
31
30
29
18
19
20
21
22
23
24
25
26
27
28
D5
D6
D7
A0
XTAL1
GND
XTAL2
A1
A2
CHSEL
INTB
-C
S
-M
F
B
-
IOW
RE
S
E
T
GN
D
-R
T
S
B
-
IOR
RX
B
TX
B
-D
T
R
B
-C
T
S
B
RXA
TXA
-DTRA
-RTSA
-MFA
INTA
VCC
-TXRDYB
-RIB
-CDB
-DSRB
D4
D3
D2
D1
D0
-T
XR
D
Y
A
VC
C
-R
I
A
-C
D
A
-D
S
R
A
-C
T
S
A
XR16C2852CJ
July 1999
Visit Exar at www.exar.com
Note*1: Covered by U.S. patent #5,649,122 and patent pending.
XR16C2852
2
Rev. 1.00
Visit Exar at www.exar.com
Figure 2, Block Diagram
D0-D7
-IOR
-IOW
RESET
A0-A2
-CS
CHSEL
INT A/B
-RXRDY A/B
-TXRDY A/B
-DTR A/B
-RTS A/B
-MF A/B
-CTS A/B
-RI A/B
-CD A/B
-DSR A/B
TX A/B
TXIR A/B
RX A/B
RXIR A/B
XTAL1
XTAL2
D
a
ta bu
s
&
Con
t
r
o
l L
o
gic
Re
g
i
st
er
S
e
lect
L
o
gic
Modem
Control
Logic
In
t
e
r
r
u
p
t
Con
t
rol
L
o
gic
Transmit
FIFO
Registers
Flow
Control
Logic
Transmit
Shift
Register
Receive
FIFO
Registers
Flow
Control
Logic
Receive
Shift
Register
I
n
te
r C
o
n
n
ec
t
B
u
s L
i
n
e
s
&
Con
t
r
o
l s
i
gn
als
Clock
&
Bau
d
Ra
te
Ge
ner
a
to
r
Ir
Encoder
Ir
Decoder
XR16C2852
3
Rev. 1.00
Visit Exar at www.exar.com
SYMBOL DESCRIPTION
A0
10
I
Address-0 Select Bit. - Internal register address selection.
A1
14
I
Address-1 Select Bit. - Internal register address selection.
A2
15
I
Address-2 Select Bit. - Internal register address selection.
CHSEL
16
I
Channel Select - UART channel A or B is selected by the logical state of this
pin when the -CS is a logic 0. A logic 0 on CHSEL selects the UART channel
B while a logic 1 selects UART channel A. Normally, CHSEL could just be
an address line from the user CPU such as A4.
-CS
18
I
Chip Select (active low) - This function selects channel A or B in accor-
dance with the logical state of the CHSEL pin. This allows data to be
transferred between the user CPU and the 2852. Bit-0 of the Alternate
Function Register (AFR) can temporary override CHSEL function, allowing
the user to write to both channel registers simultaneously with one write
cycle. It is specially useful in the initialization routine.
D0-D7
2-9
I/O
Data Bus (Bi-directional, tri-state) - These pins are the eight bit, three state
data bus for transferring information to or from the controlling external
CPU. D0 is the least significant bit and the first data bit in a transmit or
receive serial data stream.
GND
12,22
Pwr
Signal and power ground.
INT A-B
34,17
O
Interrupt A-B (active high) - This function is associated with individual
channel interrupts, INT A-B. Interrupts are enabled in the interrupt enable
register (IER), and becomes a logic 1 whenever an interrupt condition
exists. Interrupt conditions include: receive data buffer ready, receive data
time-out, receive errors, transmit buffer empty, or when a modem status
change is detected.
-IOR
24
I
Read strobe (active low ) - A logic 0 transition on this pin will load the
contents of an Internal register defined by address bits A0-A2 onto the data
bus (D0-D7) for access by user CPU.
-IOW
20
I
Write strobe (active low) - A logic 0 transition on this pin will transfer the
contents of the data bus (D0-D7) from the external CPU to an internal
register that is defined by address bits A0-A2.
-MF A-B
35,19
O
Multi-Function A-B - This function is associated with an individual channel
function, A or B. User programmable bits 1-2 of the Alternate Function
Symbol
Pin
Signal
Pin Description
44
type
XR16C2852
4
Rev. 1.00
Visit Exar at www.exar.com
SYMBOL DESCRIPTION
Register (AFR), selects a signal function for output on these pins. -OP2,
-BAUDOUT and -RXRDY are signal functions that may be selected by the
AFR register. These signal functions are described as follows:
1) -OP2 A-B - When -OP2 (active low) is selected, the -MF pin is a logic
0 when the MCR bit-3 bit is set to a logic 1 (see MCR bit-3). MCR bit-3
defaults to a logic 1 condition after a reset or power-up.
2) -BAUDOUT A-B - When -BAUDOUT function is selected, the 16X Baud
rate clock output is available at this pin.
3) -RXRDY A-B - -RXRDY (active low) is intended for monitoring DMA
mode 1 data transfers for receive data in the FIFO. A logic 0 indicates there
is receive data to read/unload, i.e., receive ready status with one or more
characters available in the FIFO/RHR. This pin is a logic 1 when the FIFO/
RHR is empty or when the programmed FIFO trigger level has not been
reached. This signal can also be used for single character transfers (DMA
mode 0).
RESET
21
I
Reset (active high) - A logic 1 on this pin will reset both UART's internal
registers and all the outputs. The UART transmitter output and the receiver
input will be disabled during reset time (see XR16C2852 External Reset
Conditions for initialization details).
-TXRDY A/B
1,32
O
Transmit Ready A-B (active low) - These outputs provide the transmit
FIFO/THR status for individual channels, A-B. -TXRDY is intended for
monitoring DMA mode 1 data transfers for the transmit data FIFO. An
individual channel's -TXRDY A-B buffer ready status is indicated by logic
0, i.e., at least one empty location is available in the FIFO or THR. This pin
goes to a logic 1 when there is no more empty location in the FIFO or THR.
This signal can also be used for single character transfers (DMA mode 0).
VCC
33,44
Pwr
Power supply input.
XTAL1
11
I
Crystal or External Clock Input - Functions as a crystal input or as an
external clock input. A crystal can be connected between this pin and
XTAL2 to form an internal oscillator circuit. An external 1 M
W
resistor is
required between the XTAL1 and XTAL2 pins. Alternatively, an external
clock can be connected to this pin to provide custom data rates (see Baud
Rate Generator Programming).
Symbol
Pin
Signal
Pin Description
44
type
XR16C2852
5
Rev. 1.00
Visit Exar at www.exar.com
SYMBOL DESCRIPTION
XTAL2
13
O
Output of the Crystal Oscillator or Buffered Clock - (see also XTAL1).
Crystal oscillator output or buffered clock output. Should be left open if an
external clock is connected to XTAL1.
-CD A-B
42,30
I
Carrier Detect (active low) - These inputs are associated with individual
UART channels A through B. A logic 0 on this pin indicates that a carrier has
been detected by the modem for that channel. This pin can be used as a
general purpose input when not connected to a modem.
-CTS A-B
40,28
I
Clear to Send (active low) - These inputs are associated with individual
UART channels, A-B. A logic 0 on the -CTS pin indicates the modem or data
set is ready to accept transmit data from the 2852. Status can be tested by
reading MSR bit-4. This pin controls the transmitter when auto CTS
function is enabled otherwise it has no effect on the UART's operation. This
pin can be used as a general purpose input when not connected to a
modem.
-DSR A-B
41,29
I
Data Set Ready (active low) - These inputs are associated with individual
UART channels, A-B. A logic 0 on this pin indicates the modem or data set
is powered-on and is ready for data exchange with the UART. This pin has
no effect on the UART's operation. This pin can be used as a general
purpose input when not connected to a modem.
-DTR A-B
37,27
O
Data Terminal Ready (active low) - These outputs are associated with
individual UART channels, A-B. A logic 0 on this pin indicates that the 2852
is powered-on and ready. This pin can be controlled via the modem control
register. Writing a logic 1 to MCR bit-0 will set the -DTR output to logic 0,
enabling the modem. This pin will be a logic 1 after writing a logic 0 to MCR
bit-0, or after a reset. This pin has no effect on the UART's transmit or
receive operation. This pin can be used as a general purpose output when
not connected to a modem.
-RI A-B
43,31
I
Ring Indicator (active low) - These inputs are associated with individual
UART channels, A-B. A logic 0 on this pin indicates the modem has
received a ringing signal from the telephone line. A logic 1 transition on this
input pin will generate an interrupt. This pin can be used as a general
purpose input when not connected to a modem .
-RTS A-B
36,23
O
Request to Send (active low) - These outputs are associated with individual
UART channels, A-B. A logic 0 on the -RTS pin indicates the transmitter has
data ready and waiting to send. Writing a logic 1 in the modem control
register (MCR bit-1) will set this pin to a logic 0 indicating data is available.
Symbol
Pin
Signal
Pin Description
44
type
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