MP7611

Rev. 3.01

EXAR Corporation, 48720 Kato Road, Fremont, CA 94538 z (510) 668-7000 z (510) 668-7017

1998

FEATURES

· Eight Independent Channel 14-Bit DACs with

Output Amplifiers

· Low Power 320 mW (typ.)
· Parallel Digital Data and Address Port
· Double Buffered Data Interface
· Readback of DAC Latches
· Zero Volt Output Preset (Data = 10 .. 00)
· 14-Bit Resolution, 12-Bit Accuracy
· Extremely Well Matched DACs
· Extremely Low Analog Ground Current (<60mA/Channel)
· +10 V Output Swing with +11.4 V Supplies

Octal 14-Bit DAC Array

D/A Converter with Output Amplifier

and Parallel Data/Address mP Control Logic

· Rugged Construction -- Latch-Up Free
· Serial Version: MP7610

APPLICATIONS

· Data Acquisition Systems
· ATE
· Process Control
· Self-Diagnostic Systems
· Logic Analyzers
· Digital Storage Scopes
· PC Based Controller/DAS

June 1998-3

GENERAL DESCRIPTION

The MP7611 provides eight independent 14-bit resolution
Digital-to-Analog Converters with voltage output
amplifiers and a parallel digital address and data port.

Built using an advanced linear BiCMOS, these devices
offer rugged solutions that are latch-up free, and take
advantage of EXAR's patented thin-film resistor process
which exhibits excellent long term stability and reliability.

A standard m-processor and TTL/CMOS compatible

14-bit input data port loads the data into the pre-selected
DACS.

This device can easily be interfaced to a data bus, and
digital readback of each channel is available.

Typical DAC matching for C grade versions is 1.5 LSB
across all codes. The output amplifier is capable of
sinking and sourcing 5mA, and the output voltage settles
to 12-bits in less than 30ms (typ.).

ORDERING INFORMATION

Package

Type

Temperature

Range

INL

(LSB)

Part No.

PQFP

--40 to +85

MP7611AE

¦8

PQFP

--40 to +85

MP7611BE

¦4

Res.

(Bits)

DNL

(LSB)

¦4

¦3

FSE

(LSB)

¦32

¦24

PLCC

--40 to +85

MP7611AP

¦8

PLCC

--40 to +85

MP7611BP

¦4

¦3

¦32

¦24

PQFP

0 to +70

MP7611CE

¦2

¦16

PLCC

0 to +70

MP7611CP

¦2

¦16

MP7611

Rev. 3.01

PIN OUT DEFINITIONS

N/C

No Connection

VO3

DAC 3 Output

Analog Negative Power Supply (--12 V)

Analog Positive Power Supply (+12 V)

N/C

No Connection or DV

REF

Analog Voltage Reference Input (+5 V)

REFN

Analog Negative Voltage Reference

Output (--2.5 V)

Analog Positive Power Supply (+12 V)

Analog Negative Power Supply (--12 V)

VO4

DAC 4 Output

N/C

No Connection

VO5

DAC 5 Output

VO6

DAC 6 Output

VO7

DAC 7 Output

AGND

Analog Ground ( 0 V)

Chip Select Enable

Read Back Enable

Second--Latch-Bank Reset Enable

First--Latch-Bank Reset Enable

LD2

Second--Latch-Bank Load Enable

LD1

First--Latch-Bank Load Enable

Digital Address Bit 2

Digital Address Bit 1

Digital Address Bit 0

DB0

Digital Input Data Bit 0

DB1

Digital Input Data Bit 1

DB2

Digital Input Data Bit 2

DB3

Digital Input Data Bit 3

DB4

Digital Input Data Bit 4

DB5

Digital Input Data Bit 5

DB6

Digital Input Data Bit 6

DB7

Digital Input Data Bit 7

DB8

Digital Input Data Bit 8

DB9

Digital Input Data Bit 9

DB10

Digital Input Data Bit 10

DB11

Digital Input Data Bit 11

DB12

Digital Input Data Bit 12

DB13

Digital Input Data Bit 13 (MSB)

Digital Positive Power Supply (+5 V)

DGND

Digital Ground (0 V)

AGND

Analog Ground (0 V)

VO0

DAC 0 Output

VO1

DAC 1 Output

VO2

DAC 2 Output

PLCC

PIN NO.

DESCRIPTION

NAME

PQFP

PIN NO.

MP7611

Rev. 3.01

Tmin to Tmax

ELECTRICAL CHARACTERISTICS

= +12 V, V

= --12 V, V

REF

= 5 V, DV

= 5.0 V, T = 25°C, Output Load = 5kW (unless otherwise noted)

Parameter

Symbol

Min

Typ

Max

Min

Max

Units

Test Conditions/Comments

STATIC PERFORMANCE

Resolution (All Grades)

Bits

Integral Non-Linearity

INL

LSB

End Point Linearity Spec

(Relative Accuracy)

¦8

¦4

¦2

¦2.5

Differential Non-Linearity

DNL

LSB

¦4

¦3

¦2

¦2.5

Positive Full Scale Error

+FSE

LSB

¦32

¦24

¦16

Positive Full Scale Error

+FSE/

ppm/°C

0°C to 85°C

Temperature Coefficient

Negative Full Scale Error

--FSE

LSB

¦32

¦24

¦16

Negative Full Scale Error

--FSE/

ppm/°C

0°C to 85°C

Temperature Coefficient

Bipolar Zero Offset

ZOFS

LSB

¦16

¦12

Bipolar Zero Offset

ZOFS/

ppm/°C

0°C to 85°C

Temperature Coefficient

INL Matching

INL

LSB

¦8

¦6

All Channels Maximum Error

LSB

with DAC 0 adjusted to
minimum error
A

¦16

¦8

¦6

Bipolar Zero Matching

ZOFS

LSB

¦16

¦12

Full Scale Error Matching

FSE

LSB

¦16

¦12

MP7611

Rev. 3.01

Tmin to Tmax

ELECTRICAL CHARACTERISTICS (CONT'D)

Parameter

Symbol

Min

Typ

Max

Min

Max

Units

Test Conditions/Comments

DYNAMIC PERFORMANCE
Voltage Settling from LD

ZS to FS (20 V Step)

to VDAC Out

5k, 50pF load

Channel-to-Channel Crosstalk

0.04

LSB

Digital Feedthrough

1, 6

--70

CLK and Data to V

OUTi

Power Supply Rejection Ratio

PSRR

ppm/%

& DV

= +5%, ppm of FS

REFERENCE INPUTS
Impedance of V

REF

350

700

1.05k

350

1.05k

See Application Hints for driving
the reference input

REF

Voltage1,

REF

3.5

DIGITAL INPUTS

Logic High

2.4

Logic Low

0.8

Input Current

+10

Input Capacitance

ANALOG OUTPUTS
Output Swing

--V

+1.4 V

--1.4

Output Drive Current

--5

REFN

Output Drive Current

--10

+10

For test purposes only

Output Impedance

Output Short Circuit Current

+FS to AGND

+FS to V

--FS to AGND

--FS to V

DIGITAL OUTPUTS
Output High Voltage

4.5

Output Low Voltage

0.5

POWER SUPPLIES
V

Voltage

REF

+1.5 12

12.75

REF

+1.5 12.75

Voltage

--12.75

--12

--5

--12.75

--5

Voltage

4.5

5.5

4.5

5.5

Positive Supply Current

Bipolar zero

Negative Supply Current

Bipolar zero

Digital Supply Current

Bipolar zero

Power Dissipation

ISS

320

420

450

Bipolar zero

ANALOG GROUND CURRENT
Per Channel

AGND

±60

See Application Notes

DIGITAL TIMING
SPECIFICATIONS

1,4

= 0 V, V

= 5 V, C

= 20 pF

Data Setup Time

Data Hold Time

Address Set-up Time

100

Address Hold Time

Chip Select to LD1 Set-up Time

CS1

Chip Select to LD1 Hold Time

CH1

LD1 Pulse Width

LD1W

LD1 Negative Edge to LD2

LD1LD2

Positive Edge

LD2 Pulse Width

LD2W

Chip Select to RD Set-Up Time

CS2

Chip Select to RD Hold Time

CH2

MP7611

Rev. 3.01

Tmin to Tmax

ELECTRICAL CHARACTERISTICS (CONT'D)

Specifications are subject to change without notice

NOTES:

Parameter

Symbol

Min

Typ

Max

Min

Max

Units

Test Conditions/Comments

DIGITAL TIMING
SPECIFICATIONS

1, 4

(CONT'D)

RD Pulse Width

600

High Z to Data Valid for Readback

600

Data Valid for Readback to High Z

200

R1 Pulse Width

R1W

100

R2 Pulse Width

R2W

100

Guaranteed; not tested.

Specified values guarantee functionality.

Digital inputs should not go below digital GND or exceed DV

supply voltage.

See Figures 1, 2 and 3. All digital input signals are specified with t

= t

= 10 ns 10% to 90% and timed from a 50% voltage level.

For power supply values < ¦2£V

REF

, the output swing is limited as specified in Analog Outputs.

Digital feedthrough and channel-to-channel crosstalk are heavily dependent on the board layout and environment.

ABSOLUTE MAXIMUM RATINGS (TA = +25

C unless otherwise noted)

1, 2

to AGND

+16.5 V

. . . . . . . . . . . . . . . . . . . . . . . . . . .

to AGND

--16.5 V

. . . . . . . . . . . . . . . . . . . . . . . . . . .

to DGND

+6.5 V

. . . . . . . . . . . . . . . . . . . . . . . . . .

VREF to DGND

+7.0 V

. . . . . . . . . . . . . . . . . . . . . . . . . .

Analog Outputs & Inputs

Infinite Shorts to V

, V

, DV

, AGND and DGND

(provided that power dissipation of the package spec is

not exceeded)

AGND to DGND

+1 V

. . . . . . . . . . . . . . . . . . . . . . . . . . . .

(Functionality guaranteed for ¦0.5 V only)

Digital Input & Digital Output Voltage to:

+.5 V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

DGND

--.5 V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Operating Temperature Range

Extended Industrial

--40°C to +85°C

. . . . . . . . . . . . . . .

Military

--55°C to +125°C

. . . . . . . . . . . . . . . . . . . . . . . . .

Maximum Junction Temperature

150°C

. . . . . . . . . . . .

Storage Temperature Range

--65°C to +150°C

. . . . . .

Lead Temperature (Soldering, 10 sec)

+300°C

. . . . .

Package Power Dissipation Rating to 75°C

PQFP, PGA, PLCC

800mW

. . . . . . . . . . . . . . . . . .

Derates above 75°C

11mW/°C

. . . . . . . . . . . . . . . .

NOTES:

Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a

stress rating only and functional operation at or above this specification is not implied. Exposure to maximum rating

conditions for extended periods may affect device reliability.

Any input pin which can see a value outside the absolute maximum ratings should be protected by Schottky diode clamps

(HP5082-2835) from input pin to the supplies. All inputs have protection diodes which will protect the device from short

transients outside the supplies of less than 100mA for less than 100

APPLICATION NOTES

NOTE: When using these DACs to drive remote devices, the accuracy of the output can be improved by utilizing a remote analog
ground connection. The difference between the DGND and AGND should be limited to ¦300 mV to assure normal operation. If there
is any chance that the AGND to DGND can be greater than ¦1 V, we recommend two back-to-back diodes be used between DGND
and AGND to clamp the voltage and prevent damage to the DAC. Using a buffer between the remote ground location and AGND may
help reduce noise induced from long lead or trace lengths.

MP7611

Rev. 3.01

Data

Input/Output

Bus

Address

A0-A2

Chip Select

Load Latch A

LD1

Load Latch B

LD2

1
0

+FS
--FS

Analog Output

CH1

CS1

LD1W

LD1LD2

LD2W

don't care

Notes:
(1)

Chip Select (CS) and Load LATCHA (LD1) Signals follow the same timing constraints and are interchangeable

in the above diagram.

(2)

R1 = R2 = 1.

(3)

For the case where LD2 is in the low state, analog output would respond to the falling edge of LD1 (transparent mode).

Address

A0-A2

Chip Select

Data Readback

Digital Output Data

D0 to D113

don't care

CS2

CH2

don't care

HIGH-Z

1
0

1
0
1
0

Notes:
(1)

Chip Select (CS) and Data Readback (RD) Signals follow the same timing constraints and are interchangeable

in the above diagram.

(2)

R1 = R2 = 1.

Reset first latch bank to

1000 . . . . .0000

R1W

R2W

Reset second latch bank to 1000 . . . . .0000 and analog

output to zero volt.

1
0

Figure 1. Loading Latch A and Updating Latch B

Figure 2. Read Back First Latch Bank of One DAC

Figure 3. Reset Operations

MP7611

Rev. 3.01

A standard

-processor and TTL/CMOS compatible input

data port loads the data into the pre-selected DACS. If CS = 0,
the chip accesses digital data on the bus. Then address bits A0
to A2 select the appropriate DAC and LD1 loads the data into the
first-latch-bank. When all 8-channels first-latch-banks are
loaded, then LD2 enables the second-latch-bank and updates

all 8-channels simultaneously. The selected DAC becomes
transparent (activity on the digital inputs appear at the analog
output) when both LD1 = LD2 = 0.

R1 = 0 resets the first-latch-bank. R2 = 0 resets the second-

latch-bank which sets the analog output to zero volts (data =
100...00), regardless of digital inputs.

Function

A1 A0

Table 1. Octal Parallel Data Input 14-Bit DAC Truth Table

Load Latch 1 of DAC1
Load Latch 1 of DAC2
Load Latch 1 of DAC3
Load Latch 1 of DAC4
Load Latch 1 of DAC5
Load Latch 1 of DAC6
Load Latch 1 of DAC7
Load Latch 1 of DAC8

1
1
1
1
1
1
1
1

0
0
0
0
0
0
0
0

Load Latch 2 of DAC1

Read Latch 1 of DAC1
Read Latch 1 of DAC2
Read Latch 1 of DAC3
Read Latch 1 of DAC4
Read Latch 1 of DAC5
Read Latch 1 of DAC6
Read Latch 1 of DAC7
Read Latch 1 of DAC8

1
1
1
1
1
1
1
1

0
0
0
0
0
0
0
0

1
1
1
1
1
1
1
1

Reset Latch 1 of DAC1

Reset Latch 2 of DAC1

X
X

0
1

1
0

X
X

Note: 1: High, 0: Low, X: Don't Care

LD1

LD2

Note: For timing information see Electrical Characterist

ics

MP7611

Rev. 3.01

Figure 4. Simplified Parallel Logic Port

3-8

Decoder

To first latch bank enable

To switches across the first latch

bank for readback enable

To second latch bank enable

To reset all first latch bank

To reset all second latch bank

A0 to A2

LD1

LD2

Table 2. MP7611

Ideal DAC Output vs. Input Code

Hex Code

Output Voltage = 2

Vr (--1 +

O O O O

(--1 + 0) = --10

1 F F F

(--1 +

) = --1.22 mV

Binary Code

16384

)

(Vr = +5 V)

00000000000000

01111111111111

16382
16384

10000000000000

16384
16384

2 O O O

(--1 +

) = 0

10000000000001

16386
16384

2 O O 1

(--1 +

) = 1.22 mV

11111111111111

32766
16384

3 F F F

(--1 +

) = 9.99878

Note: See Electrical Characteristics for real system accuracy

MP7611

Rev. 3.01

44 LEAD PLASTIC LEADED CHIP CARRIER

(PLCC)

Rev. 1.00

0.165

0.180

4.19

4.57

0.090

0.120

2.29

3.05

0.020

------.

0.51

------

0.013

0.021

0.33

0.53

0.026

0.032

0.66

0.81

0.008

0.013

0.19

0.32

0.685

0.695

17.40

17.65

0.650

0.656

16.51

16.66

0.590

0.630

14.99

16.00

0.500 typ.

12.70 typ.

0.050 BSC

1.27 BSC

0.042

0.056

1.07

1.42

0.042

0.048

1.07

1.22

0.025

0.045

0.64

1.14

SYMBOL

MIN

MAX

MIN

MAX

INCHES

MILLIMETERS

Seating Plane

Note: The control dimension is the inch column

45° x H2

45° x H1

MP7611

Rev. 3.01

NOTICE

EXAR Corporation reserves the right to make changes to the products contained in this publication in order to im-
prove design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits de-
scribed herein, conveys no license under any patent or other right, and makes no representation that the circuits are
free of patent infringement. Charts and schedules contained here in are only for illustration purposes and may vary
depending upon a user's specific application. While the information in this publication has been carefully checked;
no responsibility, however, is assumed for inaccuracies.

EXAR Corporation does not recommend the use of any of its products in life support applications where the failure or
malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly
affect its safety or effectiveness. Products are not authorized for use in such applications unless EXAR Corporation
receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the
user assumes all such risks; (c) potential liability of EXAR Corporation is adequately protected under the circum-
stances.

Copyright 1998 EXAR Corporation
Datasheet June 1998
Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited.

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