EXAR Corporation, 48720 Kato Road, Fremont, CA 94538
(510) 668-7000
FAX (510) 668-7017
ST49C101A-XX
High Frequency Clock Multiplier
January 1999 -3
Rev. 2.20
FEATURES
Mask Programmable Analog Phase Locked
Loop
Up to 200MHz Operation
Preprogrammed Multiplication Factors of 2, 3, 4, 5,
6, 8, 10 and 12X
Low Output Jitter
Replace Expensive High Frequency Oscillator
Crystal Oscillator Circuit On Chip
Low Power Single Supply 5V or 3.3V CMOS
Technology
Small 8 Lead SOIC Package
GENERAL DESCRIPTION
The ST49C101A-XX is a mask programmable mono-
lithic analog phase locked loop device, designed to
replace existing high frequency crystal oscillator with
a low frequency crystal. The high performance
APPLICATIONS
Voltage Controlled Crystal Oscillator (VCXO)
System Clock Multiplication in:
Computer Systems
Telecommunications Systems
Set-top Boxes
ST49C101A-XX provides low jitter clock output and
operates up to 180 MHz. at 3.3 volts power supply. The
ST49C101A-XX supports preprogrammed multiplica-
tion factors of 2,3,4,5,6,8,10 and 12X.
ORDERING INFORMATION
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ST49C101A-XX
2
Rev. 2.20
Oscillator
Circuit
Programmable
Counter
B
Phase
Detector
Charge
Pump
Loop
Filter
Voltage
Controlled
Oscillator
Programmable
Counter
C
Voltage
Reference
Circuit
Output
Buffer
Programmable
Counter
A
CLOCK
XTAL1
XTAL2
OE
VCC
Figure 1. Block Diagram
ST49C101A-XX
3
Rev. 2.20
PIN DESCRIPTION
Pin #
Symbol
Type
Description
1
XTAL1
I
Crystal or External Clock Input. A crystal can be connected to this pin
and XTAL2 pin to generate internal phase locked loop reference clock.
For external clock, XTAL2 is left open or used as buffered clock output.
2
1
OE
I
Clock Output Enable (Active high). CLOCK output is three stated when
this pin is low. Connect to DVCC for normal operation.
3
AGND
O
Analog Ground.
4
DGND
O
Digital Ground.
5
CLOCK
O
Programmed Output Clock.
6
DV
CC
I
Positive Supply Voltage. Single +5 or 3.3 volts.
7
AV
CC
I
Analog Supply Voltage. Single +5 or 3.3 volts.
8
XTAL2
O
Crystal Output.
Note:
1
Has internal weak pull-up resistor
8
1
5
4
2
3
7
6
X T A L 2
A V C C
D V C C
C L O C K
X T A L 1
O E
A G N D
D G N D
8 Pin SOIC (Jedec, 0.150")
ST49C101A-XX
4
Rev. 2.20
MULTIPLICATION FACTOR AND OUTPUT FRE-
QUENCY SELECTION
The ST49C101A-XX contains an analog phase locked
loop (PLL) circuit with digital closed loop dividers and
a final output divider to achieve the desired dividing
ratios for the clock output. The preprogrammed multi-
plication factor and output frequency are shown on
Table 1. The accuracy of the output frequency pro-
duced by the ST49C101A-XX depends on its input
frequency and multiplication factor.
APPLICATIONS
Two application examples are shown in Figure 2 and 3.
Figure 2 shows a lower cost high frequency crystal
oscillator circuit using the ST49C101-xx to increase
the fundamental crystal frequency. The crystal Y1 is
connected to XTAL1 and XTAL2 pins to use the
internal oscillator circuit. The oscillator provides the
reference clock to the PLL circuit for clock rate multi-
plication. Figure 3 shows a similar circuit using
external clock input on XTAL1 pin instead.
If a sinewave is used for external clock, it may be
necessary to AC couple the signal with a 0.047uF
capacitor to XTAL1 pin so that the internal circuitry
can establish the proper bias. Also, keep the peak-to-
peak signal, at XTAL pin, above ground level (AGND)
and below AVCC.
As a general board layout rule, it is recommended to
use two 0.01
F bypass capacitors on DVCC and
AVCC power supply pins, and put them as closely as
possible to the chip.
Notes
1
See AC electrical characteristics for maximum operating
frequency.
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.
3
Table 1. Preprogrammed Options
ST49C101A-XX
5
Rev. 2.20
XTAL1
XTAL2
AGND DGND
CLOCK
OE
U1
ST49C101A-XX
C1
C2
Y1
DGND
AGND
AGND
DGND
CLOCK= Xtal Freq. x Option
1
8
3
4
7
6
5
2
Parallel Cut
Fundamental
Resonance
20-30pF Load
Crystal
0.01uF
0.01uF
DVCC
DVCC
AVCC
DVCC
AVCC
Figure 2. High Frequency Crystal Oscillator Using a Crystal for Reference.
CLKin
XTAL1
XTAL2
CLOCK
OE
C2
U1
ST49C101A-XX
CLOCK = CLKin x Option
AGND
DGND
1
8
3
4
7
6
5
2
0.01uF
DVCC
AVCC
DVCC
AGND
DGND
AGND
DGND
DVCC
AVCC
C1
0.01uF
Figure 3. High Frequency Clock Rate Multiplication Using External Clock.
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