Exar

Corporation 48720 Kato Road, Fremont CA, 94538

(510) 668-7000

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áç

XR16C854/854D

2.97V TO 5.5V QUAD UART WITH 128-BYTE FIFO

JANUARY 2004

REV. 3.0

GENERAL DESCRIPTION

The XR16C854/854D

(854) is an enhanced quad

Universal Asynchronous Receiver and Transmitter
(UART) each with 128 bytes of transmit and receive
FIFOs, transmit and receive FIFO counters and
trigger levels, automatic hardware and software flow
control, and data rates of up to 2 Mbps. Each UART
has a set of registers that provide the user with
operating status and control, receiver error
indications, and modem serial interface controls.
System interrupts may be tailored to meet design
requirements. An internal loopback capability allows
onboard diagnostics. The 854 is available in 64-pin
TQFP, 68-pin PLCC and 100-pin QFP packages.
The 64-pin package only offers the 16 mode
interface, but the 68 and 100 pin packages offer an
additional 68 mode interface which allows easy
integration with Motorola processors. The
XR16C854CV (64 pin) offers three state interrupt
outputs while the XR16C854DV provides continuous
interrupt outputs. The 100 pin package provides
additional FIFO status outputs (TXRDY# and
RXRDY# A-D), separate infrared transmit data
outputs (IRTX A-D) and channel C external clock
input (CHCCLK). The XR16C854/854D is compatible
with the industry standard ST16C554/554D and
ST16C654/654D.

OTE

1 Covered by U.S. Patent #5,649,122 and #5,949,787.

FEATURES

Added feature in devices with top mark date code of
"F2 YYWW" and newer:

5 volt tolerant inputs

2.97 to 5.5 Volt Operation

Pin-to-pin compatible with the industry standard
ST16C554 and ST16C654 and TI's TL16C554N
and TL16C754BFN

Intel or Motorola Data Bus Interface select

Four independent UART channels

Data rates of up to 2 Mbps

Transmit and Receive FIFOs of 128 bytes

Programmable TX and RX FIFO Trigger Levels

Transmit and Receive FIFO Level Counters

Automatic Hardware (RTS/CTS) Flow Control

Selectable Auto RTS Flow Control Hysteresis

Automatic Software (Xon/Xoff) Flow Control

Wireless Infrared (IrDA 1.0) Encoder/Decoder

Sleep Mode (200 uA typical)

Crystal oscillator or external clock input

APPLICATIONS

Portable Appliances

Telecommunication Network Routers

Ethernet Network Routers

Cellular Data Devices

Factory Automation and Process Controls

IGURE

1. XR16C854 B

LOCK

IAGRAM

XTAL1
XTAL2

Crystal Osc/Buffer

Data Bus

Interface

UART Channel A

128 Byte TX FIFO

128 Byte RX FIFO

BRG

ENDEC

TX & RX

UART

Regs

2.97V to 5.5V V CC

GND

854 BLK

TXB, RXB, IRTXB , DTRB#,
D SR B#, R TS B#, C TSB #,
C DB #, R IB#, OP2 B#

UART Channel B

(sam e as Channel A )

A2:A0

D7:D0

CSA#

16/68#

CSB#

INTA

INTB

IOW #

IOR#

Reset

INTSEL

CHCCLK

TXRDY# A-D

R XR DY # A-D

UART Channel C

(sam e as Channel A )

TXA, RXA, IRTXA , DTRA#,
D SR A#, R TS A#, C TSA #,
C DA #, R IA#, OP2 A#

TXC , RX C, IR TXC , D TRC #,
D SR C#, RTSC#, C TS C#,
C DC #, R IC#, OP 2C#

UART Channel D

(sam e as Channel A )

TXD, RX D, IRTXD, DTRD#,
DSRD#, RTSD#, CTSD#,
CDD#, RID#, OP 2D#

CSC#

CSD#

INTC

INTD

XR16C854/854D

áç

2.97V TO 5.5V QUAD UART WITH 128-BYTE FIFO

REV. 3.0

IGURE

2. P

SSIGNMENT

100-

PIN

QFP P

ACKAGES

AND

68 M

ODE

XR16C854

100-pin QFP

16 Mode

Connect 16/68# pin to VCC

100

RDYA

TXA

DSRA

CTSA

VCC

RTSA

CSA

TXA

TXB

CSB

RTSB

CTSB

DSRB

TXB

RDYB

RXRDYB#

CDB#

RIB#

RXB

CLKSEL

16/68#

XTAL1

XTAL2

CHCCLK

RESET

RXRDY#

TXRDY#

GND

RXC

RIC#

CDC#

RXRDYC#

FSR

TXD

DSRD#

CTSD#

RTSD#

CSD#

TXD

TXC

CSC#

RTSC#

VCC

CTSC#

DSRC#

TXC

RDYC#

RXRDYA#

CDA#

RIA#

RXA

GND

INTSEL

VCC

RXD

RID#

CDD#

RXRDYD#

TXRDYD#

XR16C854

100-pin QFP

68 Mode

Connect 16/68# pin to GND

100

RDY

RXRDYB#

CDB#

RIB#

RXB

CLKSEL

16/68#

XTAL1

XTAL2

CHCCLK

RESET#

RXRDY#

TXRDY#

GND

RXC

RIC#

CDC#

RXRDYC#

RDY

RXRDYA#

CDA#

RIA#

RXA

GND

VCC

RXD

RID#

CDD#

RXRDYD#

TXRDYD#

áç

XR16C854/854D

REV. 3.0

2.97V TO 5.5V QUAD UART WITH 128-BYTE FIFO

IGURE

3. P

SSIGNMENT

PLCC P

ACKAGES

AND

68 M

ODE

AND

TQFP P

ACKAGES

ORDERING INFORMATION

ART

UMBER

ACKAGE

PERATING

EMPERATURE

ANGE

EVICE

TATUS

XR16C854CJ

68-Lead PLCC

0°C to +70°C

Active

XR16C854IJ

68-Lead PLCC

-40°C to +85°C

Active

XR16C854CV

64-Lead TQFP

0°C to +70°C

Active

XR16C854IV

64-Lead TQFP

-40°C to +85°C

Active

XR16C854DCV

64-Lead TQFP

0°C to +70°C

Active

XR16C854DIV

64-Lead TQFP

-40°C to +85°C

Active

XR16C854CQ

100-Lead QFP

0°C to +70°C

Active

XR16C854IQ

100-Lead QFP

-40°C to +85°C

Active

DSRA#

CTSA#

DTRA#

VCC

RTSA#

INTA

CSA#

TXA

IOW#

TXB

CSB#

INTB

RTSB#

GND

DTRB#

CTSB#

DSRB#

CDB#

RXB

CLKSE

XTAL

RESET

GND

RXC

CDC#

DSRC#

DSRD#

CTSD#

DTRD#

GND

RTSD#

INTD

CSD#

TXD

IOR#

CSC#

INTC

RTSC#

VCC

DTRC#

CTSC#

CDA#

RXA

GND

VCC

RXD

CDD#

XR16C854

XR16C854D

64-pin TQFP

16 Mode Only

DSRA#

CTSA#

DTRA#

VCC

RTSA#

INTA

CSA#

TXA

IOW#

TXB

CSB#

INTB

RTSB#

GND

DTRB#

CTSB#

DSRB#

16/

68#

RDY

DSRD#

CTSD#

DTRD#

GND

RTSD#

INTD

CSD#

TXD

IOR#

TXC

CSC#

INTC

RTSC#

VCC

DTRC#

CTSC#

DSRC#

XR16C854

68-pin PLCC

16 Mode

(16/68# pin connected to VCC)

DSRA#

CTSA#

DTRA#

VCC

RTSA#

IRQ#

CS#

TXA

R/W#

TXB

N.C.

RTSB#

GND

DTRB#

CTSB#

DSRB#

CDB#

RXB

KSEL

16/

68#

XTAL

RESET#

RXRDY#

RDY#

GND

RXC

CDC#

DSRD#

CTSD#

DTRD#

GND

RTSD#

N.C.

TXD

N.C.

TXC

N.C.

RTSC#

VCC

DTRC#

CTSC#

DSRC#

CDA#

RXA

GND

VCC

RXD

CDD#

XR16C854

68-pin PLCC

68 Mode

(16/68# pin connected to GND)

XR16C854/854D

áç

2.97V TO 5.5V QUAD UART WITH 128-BYTE FIFO

REV. 3.0

PIN DESCRIPTIONS

Pin Description

AME

64-TQFP

68-PLCC

100-QFP

YPE

ESCRIPTION

DATA BUS INTERFACE

Address data lines [2:0]. These 3 address lines select one of the
internal registers in UART channel A-D during a data bus transac-
tion.

I/O

Data bus lines [7:0] (bidirectional).

IOR#

(N.C.)

When 16/68# pin is at logic 1, the Intel bus interface is selected
and this input becomes read strobe (active low). The falling edge
instigates an internal read cycle and retrieves the data byte from
an internal register pointed by the address lines [A2:A0], puts the
data byte on the data bus to allow the host processor to read it on
the rising edge.

When 16/68# pin is at logic 0, the Motorola bus interface is
selected and this input is not used.

IOW#

(R/W#)

When 16/68# pin is at logic 1, it selects Intel bus interface and this
input becomes write strobe (active low). The falling edge instigates
the internal write cycle and the rising edge transfers the data byte
on the data bus to an internal register pointed by the address lines.

When 16/68# pin is at logic 0, the Motorola bus interface is
selected and this input becomes read (logic 1) and write (logic 0)
signal. Motorola bus interface is not available on the 64 pin pack-
age.

CSA#

(CS#)

When 16/68# pin is at logic 1, this input is chip select A (active low)
to enable channel A in the device.

When 16/68# pin is at logic 0, this input becomes the chip select
(active low) for the Motorola bus interface.

Motorola bus interface is not available on the 64 pin package.

CSB#

(A3)

When 16/68# pin is at logic 1, this input is chip select B (active low)
to enable channel B in the device.

When 16/68# pin is at logic 0, this input becomes address line A3
which is used for channel selection in the Motorola bus interface.

Motorola bus interface is not available on the 64 pin package.

CSC#

(A4)

When 16/68# pin is at logic 1, this input is chip select C (active low)
to enable channel C in the device.

When 16/68# pin is at logic 0, this input becomes address line A4
which is used for channel selection in the Motorola bus interface.

Motorola bus interface is not available on the 64 pin package.

áç

XR16C854/854D

REV. 3.0

2.97V TO 5.5V QUAD UART WITH 128-BYTE FIFO

CSD#

(N.C.)

When 16/68# pin is at logic 1, this input is chip select D (active low)
to enable channel D in the device.

When 16/68# pin is at logic 0, this input is not used.

Motorola bus interface is not available on the 64 pin package.

INTA

(IRQ#)

(OD)

When 16/68# pin is at logic 1 for Intel bus interface, this ouput
becomes channel A interrupt output. The output state is defined
by the user and through the software setting of MCR[3]. INTA is set
to the active mode when MCR[3] is set to a logic 1. INTA is set to
the three state mode when MCR[3] is set to a logic 0 (default). See
MCR[3].

When 16/68# pin is at logic 0 for Motorola bus interface, this output
becomes device interrupt output (active low, open drain). An exter-
nal pull-up resistor is required for proper operation.

Motorola bus interface is not available on the 64 pin package.

INTB

INTC

INTD

(N.C.)

When 16/68# pin is at logic 1 for Intel bus interface, these ouputs
become the interrupt outputs for channels B, C, and D. The output
state is defined by the user through the software setting of MCR[3].
The interrupt outputs are set to the active mode when MCR[3] is
set to a logic 1 and are set to the three state mode when MCR[3] is
set to a logic 0 (default). See MCR[3].

When 16/68# pin is at logic 0 for Motorola bus interface, these out-
puts are unused and will stay at logic zero level. Leave these out-
puts unconnected.

Motorola bus interface is not available on the 64 pin package.

INTSEL

Interrupt Select (active high, input with internal pull-down).

When 16/68# pin is at logic 1 for Intel bus interface, this pin can be
used in conjunction with MCR bit-3 to enable or disable the INT A-
D pins or override MCR bit-3 and enable the interrupt outputs.
Interrupt outputs are enabled continuously by making this pin a
logic 1. Making this pin a logic 0 allows MCR bit-3 to enable and
disable the interrupt output pins. In this mode, MCR bit-3 is set to a
logic 1 to enable the continuous output. See MCR bit-3 description
for full detail. This pin must be at logic 0 in the Motorola bus inter-
face mode. Due to pin limitations on 64 pin packages, this pin is
not available. To cover this limitation, two 64 pin TQFP packages
versions are offered. The XR16C854D operates in the continuous
interrupt enable mode by bonding this pin to VCC internally.

TXRDYA#

TXRDYB#

TXRDYC#

TXRDYD#

UART channels A-D Transmitter Ready (active low). The outputs
provide the TX FIFO/THR status for transmit channels A-D. See

Table 5 on page 13

. If these outputs are unused, leave them

unconnected.

RXRDYA#

RXRDYB#

RXRDYC#

RXRDYD#

100

UART channels A-D Receiver Ready (active low). This output pro-
vides the RX FIFO/RHR status for receive channels A-D. See

Table 5 on page 13

. If these outputs are unused, leave them

unconnected.

TXRDY#

Transmitter Ready (active low). This output is a logically wire-
ORed status of TXRDY# A-D. See

Table 5 on page 13

. If this out-

put is unused, leave it unconnected.

Pin Description

AME

64-TQFP

68-PLCC

100-QFP

YPE

ESCRIPTION

XR16C854/854D

áç

2.97V TO 5.5V QUAD UART WITH 128-BYTE FIFO

REV. 3.0

RXRDY#

Receiver Ready (active low). This output is a logically wire-ORed
status of RXRDY# A-D. See

Table 5 on page 13

. If this output is

unused, leave it unconnected.

FSRS#

FIFO Status Register Select (active low input with internal pull-up).

The content of the FSTAT register is placed on the data bus when
this pin becomes active. However it should be noted, D0-D3 con-
tain the inverted logic states of TXRDY# A-D pins, and D4-D7 the
logic states (un-inverted) of RXRDY# A-D pins. Address line is not
required when reading this status register.

MODEM OR SERIAL I/O INTERFACE

TXA

TXB

TXC

TXD

UART channels A-D Transmit Data and infrared transmit data.
Standard transmit and receive interface is enabled when MCR[6] =
0. In this mode, the TX signal will be a logic 1 during reset, or idle
(no data). Infrared IrDA transmit and receive interface is enabled
when MCR[6] = 1. In the Infrared mode, the inactive state (no
data) for the Infrared encoder/decoder interface is a logic 0.

IRTXA

IRTXB

IRTXC

IRTXD

UART channel A-D Infrared Transmit Data. The inactive state (no
data) for the Infrared encoder/decoder interface is a logic 0.
Regardless of the logic state of MCR bit-6, this pin will be operating
in the Infrared mode.

RXA

RXB

RXC

RXD

UART channel A-D Receive Data or infrared receive data. Normal
receive data input must idle at logic 1 condition. The infrared
receiver pulses typically idles at logic 0 but can be inverted by soft-
ware control prior going in to the decoder, see FCTR[2].

RTSA#

RTSB#

RTSC#

RTSD#

UART channels A-D Request-to-Send (active low) or general pur-
pose output. This output must be asserted prior to using auto RTS
flow control, see EFR[6], MCR[1], FCTR[1:0], EMSR[5:4] and
IER[6]. Also see

Figure 11

. If these outputs are not used, leave

them unconnected.

CTSA#

CTSB#

CTSC#

CTSD#

UART channels A-D Clear-to-Send (active low) or general purpose
input. It can be used for auto CTS flow control, see EFR[7], and
IER[7]. Also see

Figure 11

. These inputs should be connected to

VCC when not used.

DTRA#

DTRB#

DTRC#

DTRD#

UART channels A-D Data-Terminal-Ready (active low) or general
purpose output. If these outputs are not used, leave them uncon-
nected.

DSRA#

DSRB#

DSRC#

DSRD#

UART channels A-D Data-Set-Ready (active low) or general pur-
pose input. This input should be connected to VCC when not used.

Pin Description

AME

64-TQFP

68-PLCC

100-QFP

YPE

ESCRIPTION

áç

XR16C854/854D

REV. 3.0

2.97V TO 5.5V QUAD UART WITH 128-BYTE FIFO

CDA#

CDB#

CDC#

CDD#

UART channels A-D Carrier-Detect (active low) or general purpose
input. This input should be connected to VCC when not used.

RIA#

RIB#

RIC#

RID#

UART channels A-D Ring-Indicator (active low) or general purpose
input. This input should be connected to VCC when not used.

ANCILLARY SIGNALS

XTAL1

Crystal or external clock input. This input is not 5V tolerant.

XTAL2

Crystal or buffered clock output.

16/68#

Intel or Motorola Bus Select (input with internal pull-up).

When 16/68# pin is at logic 1, 16 or Intel Mode, the device will
operate in the Intel bus type of interface.

When 16/68# pin is at logic 0, 68 or Motorola mode, the device will
operate in the Motorola bus type of interface.

Motorola bus interface is not available on the 64 pin package.

CLKSEL

Baud-Rate-Generator Input Clock Prescaler Select for channels A-
D. This input is only sampled during power up or a reset. Connect
to VCC for divide by 1 and GND for divide by 4. MCR[7] can over-
ride the state of this pin following a reset or initialization. See MCR
bit-7 and

Figure 6

in the Baud Rate Generator section.

CHCCLK

This input provides the clock for UART channel C. An external 16X
baud clock or the crystal oscillator's output, XTAL2, must be con-
nected to this pin for normal operation. This input may also be
used with MIDI (Musical Instrument Digital Interface) applications
when an external MIDI clock is provided.

RESET

(RESET#)

When 16/68# pin is at logic 1 for Intel bus interface, this input
becomes the Reset pin (active high). In this case, a 40 ns mini-
mum logic 1 pulse on this pin will reset the internal registers and all
outputs. The UART transmitter output will be held at logic 1, the
receiver input will be ignored and outputs are reset during reset
period (

Table 18 on page 40

). When 16/68# pin is at a logic 0 for

Motorola bus interface, this input becomes Reset# pin (active low).
This pin functions similarly, but instead of a logic 1 pulse, a 40 ns
minimum logic 0 pulse will reset the internal registers and outputs.

Motorola bus interface is not available on the 64 pin package.

VCC

4, 35, 52

13, 47,

10, 61,

Pwr

2.97V to 5.5V power supply. All input pins, except XTAL1, are 5V
tolerant.

GND

14, 28,

45, 61

6, 23, 40,

20, 46,

71, 96

Pwr

Power supply common, ground.

Pin Description

AME

64-TQFP

68-PLCC

100-QFP

YPE

ESCRIPTION

áç

XR16C854/854D

REV. 3.0

2.97V TO 5.5V QUAD UART WITH 128-BYTE FIFO

1.0

PRODUCT DESCRIPTION

The XR16C854 (854) integrates the functions of 4 enhanced 16C550 Universal Asynchronous Receiver and
Transmitter (UART). Each UART is independently controlled having its own set of device configuration
registers. The configuration registers set is 16550 UART compatible for control, status and data transfer.
Additionally, each UART channel has 128-bytes of transmit and receive FIFOs, automatic RTS/CTS hardware
flow control with hysteresis control, automatic Xon/Xoff and special character software flow control,
programmable transmit and receive FIFO trigger levels, FIFO level counters, infrared encoder and decoder
(IrDA ver 1.0), programmable baud rate generator with a prescaler of divide by 1 or 4, and data rate up to 2
Mbps. The XR16C854 can operate at 3.3 or 5 volts. The 854 is fabricated with an advanced CMOS process.

Enhanced FIFO

The 854 QUART provides a solution that supports 128 bytes of transmit and receive FIFO memory, instead of
64 bytes provided in the ST16C654 and 16 bytes in the ST16C554, or one byte in the ST16C454. The 854 is
designed to work with high performance data communication systems, that require fast data processing time.
Increased performance is realized in the 854 by the larger transmit and receive FIFOs, FIFO trigger level
control, FIFO level counters and automatic flow control mechanism. This allows the external processor to
handle more networking tasks within a given time. For example, the ST16C554 with a 16 byte FIFO, unloads
16 bytes of receive data in 1.53 ms (This example uses a character length of 11 bits, including start/stop bits at
115.2Kbps). This means the external CPU will have to service the receive FIFO at 1.53 ms intervals. However
with the 128 byte FIFO in the 854, the data buffer will not require unloading/loading for 12.2 ms. This increases
the service interval giving the external CPU additional time for other applications and reducing the overall
UART interrupt servicing time. In addition, the programmable FIFO level trigger interrupt and automatic
hardware/software flow control is uniquely provided for maximum data throughput performance especially
when operating in a multi-channel system. The combination of the above greatly reduces the CPU's bandwidth
requirement, increases performance, and reduces power consumption.

Data Rate

The 854 is capable of operation up to 2 Mbps at 5V with 16x internal sampling clock rate. The device can
operate with a crystal oscillator of up to 24 MHz crystal on pins XTAL1 and XTAL2, or external clock source of
32 MHz on XTAL1 pin. With a typical crystal of 14.74128 MHz and through a software option, the user can set
the prescaler bit for data rates of up to 921.6 kbps.

Enhanced Features

The rich feature set of the 854 is available through the internal registers. Automatic hardware/software flow
control, selectable transmit and receive FIFO trigger levels, selectable baud rates, infrared encoder/decoder
interface, modem interface controls, and a sleep mode are all standard features. MCR bit-5 provides a facility
for turning off software flow control with any incoming (RX) character. In the 16 mode INTSEL and MCR bit-3
can be configured to provide a software controlled or continuous interrupt capability. Due to pin limitations for
the 64 pin package of the 854, this feature is offered in two different TQFP packages. The XR16C854DCV
operates in the continuous interrupt enable mode by internally bonding INTSEL to VCC. The XR16C854CV
operates in conjunction with MCR bit-3 by internally bonding INTSEL to GND.

The 68 and 100 pin XR16C854 packages offer a clock prescaler select pin to allow system/board designers to
preset the default baud rate table on power up. The CLKSEL pin selects the div-by-1 or div-by-4 prescaler for
the baud rate generator. It can then be overridden following initializatioin by MCR bit-7.

The 100 pin package offer several other enhanced features. These features include a CHCCLK clock input,
FSTAT register and separate IrDA TX outputs. The CHCCLK must be connected to the XTAL2 pin for normal
operation or to external MIDI (Music Instrument Digital Interface) oscillator for MIDI applications. A separate
register (FSTAT) is provided for monitoring the real time status of the FIFO signals TXRDY# and RXRDY# for
each of the four UART channels (A-D). This reduces polling time involved in accessing individual channels.
The 100 pin QFP package also offers four separate IrDA (Infrared Data Association Standard) TX outputs for
Infrared applications. These outputs are provided in addition to the standard asynchronous modem data
outputs.

XR16C854/854D

áç

2.97V TO 5.5V QUAD UART WITH 128-BYTE FIFO

REV. 3.0

2.0

FUNCTIONAL DESCRIPTIONS

2.1

CPU Interface

The CPU interface is 8 data bits wide with 3 address lines and control signals to execute data bus read and
write transactions. The 854 data interface supports the Intel compatible types of CPUs and it is compatible to
the industry standard 16C550 UART. No clock (oscillator nor external clock) is required to operate a data bus
transaction. Each bus cycle is asynchronous using CS# A-D, IOR# and IOW# or CS#, R/W#, A4 and A3 inputs.
All four UART channels share the same data bus for host operations. A typical data bus interconnection for Intel
and Motorola mode is shown in

Figure 4

IGURE

4. XR16C854/854D T

YPICAL

NTEL

OTOROLA

ATA

NTERCONNECTIONS

VCC

DSRA#

CTSA#

RTSA#

DTRA#

RXA

TXA

RIA#

CDA#

GND

A0
A1
A2

UART_CSA#

UART_CSB#

IOR#

IOW#

D0
D1
D2
D3
D4
D5
D6
D7

A0
A1

CSA#

CSB#

D0
D1
D2
D3
D4
D5
D6
D7

IOR#

IOW#

UART

Channel A

UART

Channel B

UART_INTB

UART_INTA

INTB

INTA

UART_RESET

RESET

Serial Interface of

RS-232

Serial Interface of

RS-232

Intel Data Bus (16 Mode) Interconnections

UART

Channel C

UART

Channel D

Similar

to Ch A

Similar

to Ch A

Similar

to Ch A

UART_INTD

UART_INTC

INTD

INTC

UART_CSC#

UART_CSD#

CSC#

CSD#

VCC

16/68#

VCC

GND

A0
A1
A2

UART_CS#

R/W#

D0
D1
D2
D3
D4
D5
D6
D7

A0
A1

CSA#

CSB#

D0
D1
D2
D3
D4
D5
D6
D7

IOR#

IOW#

UART_IRQ#

INTB

INTA

RESET#

Serial Interface of

RS-232

Serial Interface of

RS-232

Motorola Data Bus (68 Mode) Interconnections

VCC

UART_RESET#

(no connect)

DSRA#

CTSA#

RTSA#

DTRA#

RXA

TXA

RIA#

CDA#

UART

Channel A

UART

Channel B

UART

Channel C

Similar

to Ch A

Similar

to Ch A

Similar

to Ch A

INTC

(no connect)

INTD

(no connect)

CSC#

CSD#

VCC

16/68#

UART

Channel D

áç

XR16C854/854D

REV. 3.0

2.97V TO 5.5V QUAD UART WITH 128-BYTE FIFO

2.2

5-Volt Tolerant Inputs

For devices that have top mark date code "F2 YYWW" and newer, the 854 can accept a voltage of up to 5.5V
on any of its inputs (except XTAL1) when operating from 2.97V to 5.5V. XTAL1 is not 5 volt tolerant. Devices
that have top mark date code "DC YYWW" and older do not have 5V tolerant inputs.

2.3

Device Reset

The RESET input resets the internal registers and the serial interface outputs in all four channels to their
default state (see

Table 18 on page 40

). An active high pulse of longer than 40 ns duration will be required to

activate the reset function in the device. Following a power-on reset or an external reset, the 854 is software
compatible with previous generation of UARTs, 16C454 and 16C554 and 16C654.

2.4

Device Identification and Revision

The XR16C854 provides a Device Identification code and a Device Revision code to distinguish the part from
other devices and revisions. To read the identification code from the part, it is required to set the baud rate
generator registers DLL and DLM both to 0x00. Now reading the content of the DLM will provide 0x14 for the
XR16C854 and reading the content of DLL will provide the revision of the part; for example, a reading of 0x01
means revision A.

2.5

Channel Selection

The UART provides the user with the capability to bi-directionally transfer information between an external
CPU and an external serial communication device. During Intel Bus Mode (16/68# pin is connected to VCC), a
logic 0 on chip select pins, CSA#, CSB#, CSC# or CSD# allows the user to select UART channel A, B, C or D
to configure, send transmit data and/or unload receive data to/from the UART. Selecting all four UARTs can be
useful during power up initialization to write to the same internal registers, but do not attempt to read from all
four uarts simultaneously. Individual channel select functions are shown in

Table 1

below.

During Motorola Bus Mode (16/68# pin is connected to GND), the package interface pins are configured for
connection with Motorola, and other popular microprocessor bus types. In this mode the 854 decodes two
additional addresses, A3 and A4, to select one of the four UART ports. The A3 and A4 address decode
function is used only when in the Motorola Bus Mode.

See Table 2

below.

ABLE

1: C

HANNEL

A-D S

ELECT

16 M

ODE

CSA#

CSB#

CSC#

CSD#

UNCTION

UART de-selected

Channel A selected

Channel B selected

Channel C selected

Channel D selected

Channels A-D selected

ABLE

2: C

HANNEL

A-D S

ELECT

68 M

ODE

CS#

UNCTION

N/A

UART de-selected

Channel A selected

Channel B selected

Channel C selected

Channel D selected

XR16C854/854D

áç

2.97V TO 5.5V QUAD UART WITH 128-BYTE FIFO

REV. 3.0

2.6

Channels A-D Internal Registers

Each UART channel in the 854 has a set of enhanced registers for control, monitoring and data loading and
unloading. The configuration register set is compatible to those already available in the standard single
16C550. These registers function as data holding registers (THR/RHR), interrupt status and control registers
(ISR/IER), a FIFO control register (FCR), receive line status and control registers (LSR/LCR), modem status
and control registers (MSR/MCR), programmable data rate (clock) divisor registers (DLL/DLM), and a user
accessible scratchpad register (SPR).

Beyond the general 16C550 features and capabilities, the 854 offers enhanced feature registers (EMSR, FLVL,
EFR, Xon/Xoff 1, Xon/Xoff 2, FCTR, TRG, FC) that provide automatic RTS and CTS hardware flow control,
Xon/Xoff software flow control, automatic RS-485 half-duplex direction output enable/disable, FIFO trigger level
control, and FIFO level counters. All the register functions are discussed in full detail later in

"Section 3.0,

UART INTERNAL REGISTERS" on page 23

2.7

INT Ouputs for Channels A-D

The interrupt outputs change according to the operating mode and enhanced features setup.

Table 3

and 4

summarize the operating behavior for the transmitter and receiver. Also see

Figure 20

through

2.8

DMA Mode

The device does not support direct memory access. The DMA Mode (a legacy term) in this document doesn't
mean "direct memory access" but refers to data block transfer operation. The DMA mode affects the state of
the RXRDY# A-D and TXRDY# A-D output pins. The transmit and receive FIFO trigger levels provide additional
flexibility to the user for block mode operation. The LSR bits 5-6 provide an indication when the transmitter is
empty or has an empty location(s) for more data. The user can optionally operate the transmit and receive
FIFO in the DMA mode (FCR bit-3=1). When the transmit and receive FIFO are enabled and the DMA mode is
disabled (FCR bit-3 = 0), the 854 is placed in single-character mode for data transmit or receive operation.
When DMA mode is enabled (FCR bit-3 = 1), the user takes advantage of block mode operation by loading or
unloading the FIFO in a block sequence determined by the programmed trigger level. The following table show
their behavior. Also see

Figure 20

through

ABLE

3: INT P

INS

PERATION

FOR

RANSMITTER

FOR

HANNELS

A-D

FCTR

Bit-3

FCR B

-0 = 0

(FIFO D

ISABLED

)

FCR B

-0 = 1 (FIFO E

NABLED

)

FCR Bit-3 = 0

(DMA Mode Disabled)

FCR Bit-3 = 1

(DMA Mode Enabled)

INT Pin

0 = a byte in THR

1 = THR empty

0 = FIFO above trigger level
1 = FIFO below trigger level or FIFO
empty

INT Pin

0 = a byte in THR

1 = transmitter empty

0 = FIFO above trigger level
1 = FIFO below trigger level or
transmitter empty

ABLE

4: INT P

PERATION

FOR

ECEIVER

FOR

HANNELS

A-D

FCR B

-0 = 0

(FIFO D

ISABLED

)

FCR B

-0 = 1 (FIFO E

NABLED

)

FCR Bit-3 = 0

(DMA Mode Disabled)

FCR Bit-3 = 1

(DMA Mode Enabled)

INT Pin

0 = no data

1 = 1 byte

0 = FIFO below trigger level
1 = FIFO above trigger level

áç

XR16C854/854D

REV. 3.0

2.97V TO 5.5V QUAD UART WITH 128-BYTE FIFO

2.9

Crystal Oscillator or External Clock Input

The 854 includes an on-chip oscillator (XTAL1 and XTAL2) to produce a clock for all four UART sections in the
device. The CPU data bus does not require this clock for bus operation. The crystal oscillator provides a
system clock to the Baud Rate Generators (BRG) section found in each of the UART. XTAL1 is the input to the
oscillator or external clock buffer input with XTAL2 pin being the output. For programming details, see
"Programmable Baud Rate Generator."

IGURE

5. T

YPICAL

OSCILATOR

CONNECTIONSL

The on-chip oscillator is designed to use an industry standard microprocessor crystal (parallel resonant,
fundamental frequency with 10-22 pF capacitance load, ESR of 20-120 ohms and 100ppm frequency
tolerance) connected externally between the XTAL1 and XTAL2 pins (see

Figure 5

). Typical standard crystal

frequencies are: 1.8432, 3.6864, 7.3728, 14.7456, 18.432, and 22.1184 MHz. Alternatively, an external clock
can be connected to the XTAL1 pin to clock the internal baud rate generator for standard or custom rates.
Typical oscillator connections are shown in

Figure 5

. For further reading on oscillator circuit please see

application note DAN108 on EXAR's web site.

2.10

Programmable Baud Rate Generator

Each UART has its own Baud Rate Generator (BRG) with a prescaler. The prescaler is controlled by a software
bit in the MCR register. The MCR register bit-7 sets the prescaler to divide the input crystal or external clock by
1 or 4. The clock output of the prescaler goes to the BRG. The BRG further divides this clock by a

programmable divisor between 1 and (2

-1) to obtain a 16X sampling rate clock of the serial data rate. The

sampling rate clock is used by the transmitter for data bit shifting and

receiver for data sampling.

Table 6 shows the standard data rates available with a 14.7456 MHz crystal or external clock at 16X sampling
rate. When using a non-standard frequency crystal or external clock, the divisor value can be calculated for
DLL/DLM with the following equation.

ABLE

5: TXRDY#

AND

RXRDY# O

UTPUTS

FIFO

AND

DMA M

ODE

FOR

HANNELS

A-D

INS

FCR

BIT

-0=0

(FIFO D

ISABLED

)

FCR B

-0=1 (FIFO E

NABLED

)

FCR Bit-3 = 0

(DMA Mode Disabled)

FCR Bit-3 = 1

(DMA Mode Enabled)

RXRDY#

0 = 1 byte

1 = no data

0 = at least 1 byte in FIFO

1 = FIFO empty

1 to 0 transition when FIFO reaches the trigger
level, or timeout occurs.

0 to 1 transition when FIFO empties.

TXRDY#

0 = THR empty

1 = byte in THR

0 = FIFO empty

1 = at least 1 byte in FIFO

0 = FIFO has at least 1 empty location.

1 = FIFO is full.

divisor (decimal) = (XTAL1 clock frequency / prescaler) / (serial data rate x 16)

C 1

2 2-4 7 pF

C 2

2 2-4 7 pF

1 4.7 45 6

M H z

X T A L 1

X T A L 2

R = 3 0 0 K to 40 0 K

XR16C854/854D

áç

2.97V TO 5.5V QUAD UART WITH 128-BYTE FIFO

REV. 3.0

2.11

Transmitter

The transmitter section comprises of an 8-bit Transmit Shift Register (TSR) and 128 bytes of FIFO which
includes a byte-wide Transmit Holding Register (THR). TSR shifts out every data bit with the 16X internal clock.
A bit time is 16 clock periods. The transmitter sends the start-bit followed by the number of data bits, inserts the
proper parity-bit if enabled, and adds the stop-bit(s). The status of the TX FIFO and TSR are reported in the
Line Status Register (LSR bit-5 and bit-6).

2.11.1

Transmit Holding Register (THR) - Write Only

The transmit holding register is an 8-bit register providing a data interface to the host processor. The host
writes transmit data byte to the THR to be converted into a serial data stream including start-bit, data bits,
parity-bit and stop-bit(s). The least-significant-bit (Bit-0) becomes first data bit to go out. The THR is the input
register to the transmit FIFO of 128 bytes when FIFO operation is enabled by FCR bit-0. Every time a write
operation is made to the THR, the FIFO data pointer is automatically bumped to the next sequential data
location.

2.11.2

Transmitter Operation in non-FIFO Mode

The host loads transmit data to THR one character at a time. The THR empty flag (LSR bit-5) is set when the
data byte is transferred to TSR. THR flag can generate a transmit empty interrupt (ISR bit-1) when it is enabled
by IER bit-1. The TSR flag (LSR bit-6) is set when TSR becomes completely empty.

IGURE

6. B

AUD

ATE

ENERATOR

AND

RESCALER

ABLE

6: T

YPICAL

DATA

RATES

WITH

14.7456 MH

CRYSTAL

EXTERNAL

CLOCK

UTPUT

Data Rate

MCR Bit-7=1

UTPUT

Data Rate

MCR Bit-7=0

EFAULT

)

IVISOR

FOR

16x

Clock (Decimal)

IVISOR

FOR

16x

Clock (HEX)

DLM

ROGRAM

ALUE

(HEX)

DLL

ROGRAM

ALUE

(HEX)

ATA

ATE

RROR

(%)

100

600

1200

2400

4800

9600

19.2k

38.4k

57.6k

115.2k

230.4k

400

2400

4800

9600

19.2k

38.4k

76.8k

153.6k

230.4k

460.8k

921.6k

2304

384

192

900

180

X T A L 1

X T A L 2

C ry s ta l

O s c /

B u ffe r

M C R B it-7 = 0

(d e fa u lt)

M C R B it-7 = 1

D L L a n d D L M

R e g iste rs

P re s ca le r

D iv id e b y 1

P re s ca le r

D iv id e b y 4

1 6 X

S a m p lin g

R a te C lo c k to

T ra n sm itte r

B a u d R a te

G e n e ra to r

L o g ic

áç

XR16C854/854D

REV. 3.0

2.97V TO 5.5V QUAD UART WITH 128-BYTE FIFO

2.11.3

Transmitter Operation in FIFO Mode

The host may fill the transmit FIFO with up to 128 bytes of transmit data. The THR empty flag (LSR bit-5) is set
whenever the TX FIFO is empty. The THR empty flag can generate a transmit empty interrupt (ISR bit-1) when
the FIFO becomes empty. The transmit empty interrupt is enabled by IER bit-1. The TSR flag (LSR bit-6) is set
when TSR/TX FIFO becomes empty.

2.12

Receiver

The receiver section contains an 8-bit Receive Shift Register (RSR) and 128 bytes of FIFO which includes a
byte-wide Receive Holding Register (RHR). The RSR uses the 16X clock for timing. It verifies and validates
every bit on the incoming character in the middle of each data bit. On the falling edge of a start or false start bit,
an internal receiver counter starts counting at the 16X clock rate. After 8 clocks the start bit period should be at
the center of the start bit. At this time the start bit is sampled and if it is still a logic 0 it is validated. Evaluating
the start bit in this manner prevents the receiver from assembling a false character. The rest of the data bits
and stop bits are sampled and validated in this same manner to prevent false framing. If there were any
error(s), they are reported in the LSR register bits 2-4. Upon unloading the receive data byte from RHR, the
receive FIFO pointer is bumped and the error tags are immediately updated to reflect the status of the data
byte in RHR register. RHR can generate a receive data ready interrupt upon receiving a character or delay until
it reaches the FIFO trigger level. Furthermore, data delivery to the host is guaranteed by a receive data ready
time-out interrupt when data is not received for 4 word lengths as defined by LCR[1:0] plus 12 bits time. This is
equivalent to 3.7-4.6 character times. The RHR interrupt is enabled by IER bit-0.

IGURE

7. T

RANSMITTER

PERATION

NON

-FIFO M

ODE

IGURE

8. T

RANSMITTER

PERATION

FIFO

AND

LOW

ONTROL

ODE

Transm it

Holding

(THR)

Transm it S hift Register (TS R)

Data

B yte

L
S
B

M
S
B

THR Interrupt (IS R bit-1)

E nabled by IE R bit-1

T XN OF IF O 1

16X

Clock

Transm it Data Shift Register

(TSR)

Data B yte

THR Interrupt (IS R bit-1) falls
below the program m ed Trigger
Level and then when becom es
em pty. FIFO is Enabled by FCR
bit-0=1

RX FIFO

16X Clock

Auto CTS Flow Control (CTS# pin)

Auto Software Flow Control

Flow Control Characters

(Xoff1/2 and X on1/2 Reg.

T XF IF O 1

THR

XR16C854/854D

áç

2.97V TO 5.5V QUAD UART WITH 128-BYTE FIFO

REV. 3.0

2.12.1

Receive Holding Register (RHR) - Read-Only

The Receive Holding Register is an 8-bit register that holds a receive data byte from the Receive Shift Register.
It provides the receive data interface to the host processor. The RHR register is part of the receive FIFO of 128
bytes by 11-bits wide, the 3 extra bits are for the 3 error tags to be reported in LSR register. When the FIFO is
enabled by FCR bit-0, the RHR contains the first data character received by the FIFO. After the RHR is read,
the next character byte is loaded into the RHR and the errors associated with the current data byte are
immediately updated in the LSR bits 2-4.

OTE

: Table-B selected as Trigger Table for

Figure 10

(

Table 11 on page 29

IGURE

9. R

ECEIVER

PERATION

NON

-FIFO M

ODE

IGURE

10. R

ECEIVER

PERATION

FIFO

AND

UTO

RTS F

LOW

ONTROL

ODE

Receive Data Shift

Receive

Data Byte

and Errors

RHR Interrupt (ISR bit-2)

Receive Data

Holding Register

(RHR)

RXFIFO1

16X Clock

Receive Data Characters

Data Bit

Validation

Error

Tags in

LSR bits

4:2

Receive Data Shift

RXFIFO1

16X Clock

r
r
or Ta

-s

t
s

)

r
r
or Ta

i
n

:
2

128 bytes by 11-bit

wide FIFO

Receive Data Characters

FIFO

Trigger=16

Example

- RX FIFO trigger level selected at 16

bytes

(See Note Below)

Data fills to

Data falls to

Data Bit

Validation

Receive

Data FIFO

Receive

Data

Receive Data
Byte and Errors

RHR Interrupt (ISR bit-2) programmed for
desired FIFO trigger level.
FIFO is Enabled by FCR bit-0=1

RTS# de-asserts when data fills above the flow
control trigger level to suspend remote transmitter.
Enable by EFR bit-6=1, MCR bit-1.

RTS# re-asserts when data falls below the flow
control trigger level to restart remote transmitter.
Enable by EFR bit-6=1, MCR bit-1.

áç

XR16C854/854D

REV. 3.0

2.97V TO 5.5V QUAD UART WITH 128-BYTE FIFO

2.13

Auto RTS Hardware Flow Control

Automatic RTS hardware flow control is used to prevent data overrun to the local receiver FIFO. The RTS#
output is used to request remote unit to suspend/resume data transmission. The auto RTS flow control features
is enabled to fit specific application requirement (see

Figure 11

Enable auto RTS flow control using EFR bit-6.

The auto RTS function must be started by asserting RTS# output pin (MCR bit-1 to logic 1 after it is enabled).

If using the Auto RTS interrupt:

Enable RTS interrupt through IER bit-6 (after setting EFR bit-4). The UART issues an interrupt when the
RTS# pin makes a transition from low to high: ISR bit-5 will be set to logic 1.

2.14

Auto RTS Hysteresis

The 854 has a new feature that provides flow control trigger hysteresis while maintaining compatibility with the
XR16C850, ST16C650A and ST16C550 family of UARTs. With the Auto RTS function enabled, an interrupt is
generated when the receive FIFO reaches the programmed RX trigger level. The RTS# pin will not be forced
to a logic 1 (RTS off), until the receive FIFO reaches the upper limit of the hysteresis level. The RTS# pin will
return to a logic 0 after the RX FIFO is unloaded to the lower limit of the hysteresis level. Under the above
described conditions, the 854 will continue to accept data until the receive FIFO gets full. The Auto RTS
function is initiated when the RTS# output pin is asserted to a logic 0 (RTS On).

Table 15

shows the complete

details for the Auto RTS# Hysteresis levels. Please note that this table is for programmable trigger levels only
(Table D). The hysteresis values for Tables A-C are the next higher and next lower trigger levels in Tables A-C
(See

Table 11

2.15

Auto CTS Flow Control

Automatic CTS flow control is used to prevent data overrun to the remote receiver FIFO. The CTS# input is
monitored to suspend/restart the local transmitter. The auto CTS flow control feature is selected to fit specific
application requirement (see

Figure 11

Enable auto CTS flow control using EFR bit-7.

If using the Auto CTS interrupt:

Enable CTS interrupt through IER bit-7 (after setting EFR bit-4). The UART issues an interrupt when the
CTS# pin is de-asserted (logic 1): ISR bit-5 will be set to 1, and UART will suspend transmission as soon as
the stop bit of the character in process is shifted out. Transmission is resumed after the CTS# input is re-
asserted (logic 0), indicating more data may be sent.

XR16C854/854D

áç

2.97V TO 5.5V QUAD UART WITH 128-BYTE FIFO

REV. 3.0

IGURE

11. A

UTO

RTS

AND

CTS F

LOW

ONTROL

PERATION

The local UART (UARTA) starts data transfer by asserting RTSA# (1). RTSA# is normally connected to CTSB# (2) of

remote UART (UARTB). CTSB# allows its transmitter to send data (3). TXB data arrives and fills UARTA receive FIFO
(4). When RXA data fills up to its receive FIFO trigger level, UARTA activates its RXA data ready interrupt (5) and con-
tinues to receive and put data into its FIFO. If interrupt service latency is long and data is not being unloaded, UARTA
monitors its receive data fill level to match the upper threshold of RTS delay and de-assert RTSA# (6). CTSB# follows
(7) and request UARTB transmitter to suspend data transfer. UARTB stops or finishes sending the data bits in its trans-
mit shift register (8). When receive FIFO data in UARTA is unloaded to match the lower threshold of RTS delay (9),
UARTA re-asserts RTSA# (10), CTSB# recognizes the change (11) and restarts its transmitter and data flow again until
next receive FIFO trigger (12). This same event applies to the reverse direction when UARTA sends data to UARTB
with RTSB# and CTSA# controlling the data flow.

RTSA#

CTSB#

RXA

TXB

Transmitter

Receiver FIFO

Trigger Reached

Auto RTS

Trigger Level

Auto CTS

Monitor

RTSA#

TXB

RXA FIFO

CTSB#

Remote UART

UARTB

Local UART

UARTA

OFF

Suspend

Restart

RTS High

Threshold

Data Starts

OFF

Assert RTS# to Begin

Transmission

Receive

Data

RTS Low

Threshold

Receiver FIFO

Trigger Reached

Auto RTS

Trigger Level

Transmitter

Auto CTS

Monitor

RTSB#

CTSA#

RXB

TXA

INTA

(RXA FIFO

Interrupt)

RX FIFO

Trigger Level

RX FIFO

Trigger Level

R T S C T S 1

áç

XR16C854/854D

REV. 3.0

2.97V TO 5.5V QUAD UART WITH 128-BYTE FIFO

2.16

Auto Xon/Xoff (Software) Flow Control

When software flow control is enabled (

See Table 17

), the 854 compares one or two sequential receive data

characters with the programmed Xon or Xoff-1,2 character value(s). If receive character(s) match the
programmed values, the 854 will halt transmission as soon as the current character has completed
transmission. When a match occurs, the Xoff (if enabled via IER bit-5) flag will be set and the interrupt output
pin will be activated. Following a suspension due to a match of the Xoff character, the 854 will monitor the
receive data stream for a match to the Xon-1,2 character. If a match is found, the 854 will resume operation and
clear the flags (ISR bit-4).

Reset initially sets the contents of the Xon/Xoff 8-bit flow control registers to a logic 0. Following reset the user
can write any Xon/Xoff value desired for software flow control. Different conditions can be set to detect Xon/
Xoff characters (

See Table 17

) and suspend/resume transmissions. When double 8-bit Xon/Xoff characters are

selected, the 854 compares two consecutive receive characters with two software flow control 8-bit values
(Xon1, Xon2, Xoff1, Xoff2) and controls TX transmissions accordingly. Under the above described flow control
mechanisms, flow control characters are not placed (stacked) in the user accessible RX data buffer or FIFO.

In the event that the receive buffer is overfilling and flow control needs to be executed, the 854 automatically
sends an Xoff message (when enabled) via the serial TX output to the remote modem. The 854 sends the Xoff-
1,2 characters two-character-times (= time taken to send two characters at the programmed baud rate) after
the receive FIFO crosses the programmed trigger level (for all trigger tables A-D). To clear this condition, the
854 will transmit the programmed Xon-1,2 characters as soon as receive FIFO is less than one trigger level
below the programmed trigger level (for Trigger Tables A, B, and C) or when receive FIFO is less than the
trigger level minus the hysteresis value (for Trigger Table D). This hysteresis value is the same as the Auto RTS
Hysteresis value in

Table 15

Table 7

below explains this when Trigger Table-B (See

Table 11

) is selected.

After the trigger level is reached, an xoff character is sent after a short span of time (= time required to send 2

characters); for example, after 2.083ms has elapsed for 9600 baud and 10-bit word length setting.

2.17

Special Character Detect

A special character detect feature is provided to detect an 8-bit character when bit-5 is set in the Enhanced
Feature Register (EFR). When this character (Xoff2) is detected, it will be placed in the FIFO along with normal
incoming RX data.

The 854 compares each incoming receive character with Xoff-2 data. If a match exists, the received data will
be transferred to FIFO and ISR bit-4 will be set to indicate detection of special character. Although the Internal
Register Table shows Xon, Xoff Registers with eight bits of character information, the actual number of bits is
dependent on the programmed word length. Line Control Register (LCR) bits 0-1 defines the number of
character bits, i.e., either 5 bits, 6 bits, 7 bits, or 8 bits. The word length selected by LCR bits 0-1 also
determines the number of bits that will be used for the special character comparison. Bit-0 in the Xon, Xoff
Registers corresponds with the LSB bit for the receive character.

2.18

Infrared Mode

The 854 UART includes the infrared encoder and decoder compatible to the IrDA (Infrared Data Association)
version 1.0. The IrDA 1.0 standard that stipulates the infrared encoder sends out a

3/16 of a bit wide HIGH-

pulse for each "0" bit in the transmit data stream. This signal encoding reduces the on-time of the infrared LED,
hence reduces the power consumption. See

Figure 12

below.

ABLE

7: A

UTO

OFF

OFTWARE

) F

LOW

ONTROL

RX T

RIGGER

EVEL

INT P

CTIVATION

OFF

HARACTER

(

) S

ENT

(

CHARACTERS

FIFO

)

HARACTER

(

) S

ENT

(

CHARACTERS

FIFO

)

16*

24*

28*

XR16C854/854D

áç

2.97V TO 5.5V QUAD UART WITH 128-BYTE FIFO

REV. 3.0

The infrared encoder and decoder are enabled by setting MCR register bit-6 to a `1'. When the infrared feature
is enabled, the transmit data output, TX, idles at logic zero level. Likewise, the RX input assumes an idle level
of logic zero from a reset and power up, see

Figure 12

Typically, the wireless infrared decoder receives the input pulse from the infrared sensing diode on the RX pin.
Each time it senses a light pulse, it returns a logic 1 to the data bit stream. However, this is not true with some
infrared modules on the market which indicate a logic 0 by a light pulse. So the 854 has a provision to invert the
input polarity to accomodate this. In this case user can enable FCTR bit-2 to invert the input signal.

2.19

Sleep Mode with Auto Wake-Up

The 854 supports low voltage system designs, hence, a sleep mode is included to reduce its power
consumption when the chip is not actively used.

All of these conditions must be satisfied for the 854 to enter sleep mode:

no interrupts pending for all four channels of the 854 (ISR bit-0 = 1)

sleep mode of all four channels are enabled (IER bit-4 = 1)

modem inputs are not toggling (MSR bits 0-3 = 0)

RX input pins are idling at a logic 1

The 854 stops its crystal oscillator to conserve power in the sleep mode. User can check the XTAL2 pin for no
clock output as an indication that the device has entered the sleep mode.

IGURE

12. I

NFRARED

RANSMIT

ATA

NCODING

AND

ECEIVE

ATA

ECODING

Character

Data Bits

Start

Stop

Bit Time

1/16 Clock Delay

IRdecoder-1

RX Data

Receive
IR Pulse
(RX pin)

C h a ra cte r

D a ta B its

T X D a ta

T ra n sm it

IR P u lse
(T X P in )

B it T im e

1 /2 B it T im e

3 /1 6 B it T im e

IrE n co d e r-1

áç

XR16C854/854D

REV. 3.0

2.97V TO 5.5V QUAD UART WITH 128-BYTE FIFO

The 854 resumes normal operation by any of the following:

a receive data start bit transition (logic 1 to 0)

a data byte is loaded to the transmitter, THR or FIFO

a change of logic state on any of the modem or general purpose serial inputs: CTS#, DSR#, CD#, RI#

If the 854 is awakened by any one of the above conditions, it will return to the sleep mode automatically after all
interrupting conditions have been serviced and cleared. If the 854 is awakened by the modem inputs, a read to
the MSR is required to reset the modem inputs. In any case, the sleep mode will not be entered while an
interrupt is pending in any channel. The 854 will stay in the sleep mode of operation until it is disabled by
setting IER bit-4 to a logic 0.

If the address lines, data bus lines, IOW#, IOR#, CSA#, CSB#, CSC#, CSD# and modem input lines remain
steady when the 854 is in sleep mode, the maximum current will be in the microamp range as specified in the
DC Electrical Characteristics on

page 41

. If the input lines are floating or are toggling while the 854 is in sleep

mode, the current can be up to 100 times more. If any of those signals are toggling or floating, then an external
buffer would be required to keep the address, data and control lines steady to achieve the low current.

A word of caution: owing to the starting up delay of the crystal oscillator after waking up from sleep mode, the
first few receive characters may be lost. Also, make sure the RX input is idling at logic 1 or "marking" condition
during sleep mode. This may not occur when the external interface transceivers (RS-232, RS-485 or another
type) are also put to sleep mode and cannot maintain the "marking" condition. To avoid this, the system design
engineer can use a 47k ohm pull-up resistor on the RX A-D inputs.

2.20

Internal Loopback

The 854 UART provides an internal loopback capability for system diagnostic purposes. The internal loopback
mode

is enabled by setting MCR register bit-4 to logic 1. All regular UART functions operate normally.

Figure 13

shows how the modem port signals are re-configured. Transmit data from the transmit shift register

output is internally routed to the receive shift register input allowing the system to receive the same data that it
was sending. The TX pin is held at logic 1 or mark condition while RTS# and DTR# are de-asserted, and
CTS#, DSR# CD# and RI# inputs are ignored. Caution: the RX input must be held to a logic 1 during loopback
test else upon exiting the loopback test the UART may detect and report a false "break" signal.

áç

XR16C854/854D

REV. 3.0

2.97V TO 5.5V QUAD UART WITH 128-BYTE FIFO

3.0

UART INTERNAL REGISTERS

Each UART channel in the 854 has its own set of configuration registers selected by address lines A0, A1 and
A2 with a specific channel selected (See

Table 1

and

Table 2

). The complete register set is shown on

Table 8

and

Table 9

ABLE

8: UART CHANNEL A AND B UART INTERNAL REGISTERS

A2,A1,A0 A

DDRESSES

EGISTER

EAD

RITE

OMMENTS

16C550 C

OMPATIBLE

EGISTERS

0 0 0

RHR - Receive Holding Register

THR - Transmit Holding Register

Read-only

Write-only

LCR[7] = 0

0 0 0

DLL - Div Latch Low Byte

Read/Write

LCR[7] = 1, LCR

0xBF

0 0 1

DLM - Div Latch High Byte

Read/Write

LCR[7] = 1, LCR

0xBF

0 0 0

DREV - Device Revision Code

Read-only

DLL, DLM

0x00,

LCR[7] = 1, LCR

0xBF

0 0 1

DVID - Device Identification Code

Read-only

DLL, DLM = 0x00,

LCR[7] = 1, LCR

0xBF

0 0 1

IER - Interrupt Enable Register

Read/Write

LCR[7] = 0

0 1 0

ISR - Interrupt Status Register

FCR - FIFO Control Register

Read-only

Write-only

LCR[7] = 0

0 1 1

LCR - Line Control Register

Read/Write

1 0 0

MCR - Modem Control Register

Read/Write

LCR[7] = 0

1 0 1

LSR - Line Status Register

Reserved

Read-only

Write-only

LCR[7] = 0

1 1 0

MSR - Modem Status Register

Reserved

Read-only

Write-only

LCR[7] = 0

1 1 1

SPR - Scratch Pad Register

Read/Write

LCR[7] = 0, FCTR[6] = 0

1 1 1

FLVL - TX/RX FIFO Level Counter Register

Read-only

LCR[7] = 0, FCTR[6] = 1

1 1 1

EMSR - Enhanced Mode Select Register

Write-only

LCR[7] = 0, FCTR[6] = 1

NHANCED

EGISTERS

0 0 0

TRG - TX/RX FIFO Trigger Level Reg

FC - TX/RX FIFO Level Counter Register

Write-only

Read-only

LCR = 0xBF

0 0 1

FCTR - Feature Control Reg

Read/Write

LCR = 0xBF

0 1 0

EFR - Enhanced Function Reg

Read/Write

LCR = 0xBF

1 0 0

Xon-1 - Xon Character 1

Read/Write

LCR = 0xBF

1 0 1

Xon-2 - Xon Character 2

Read/Write

LCR = 0xBF

1 1 0

Xoff-1 - Xoff Character 1

Read/Write

LCR = 0xBF

1 1 1

Xoff-2 - Xoff Character 2

Read/Write

LCR = 0xBF

X X X

FSTAT - FIFO Status Register

Read-only

FSRS# pin is logic 0

XR16C854/854D

áç

2.97V TO 5.5V QUAD UART WITH 128-BYTE FIFO

REV. 3.0

ABLE

9: INTERNAL REGISTERS DESCRIPTION.

HADED

BITS

ARE

ENABLED

WHEN

EFR B

-4=1

DDRESS

A2-A0

AME

EAD

RITE

-7

-6

-5

-4

-3

-2

-1

-0

OMMENT

16C550 Compatible Registers

0 0 0

RHR

Bit-7

Bit-6

Bit-5

Bit-4

Bit-3

Bit-2

Bit-1

Bit-0

LCR[7] = 0

0 0 0

THR

Bit-7

Bit-6

Bit-5

Bit-4

Bit-3

Bit-2

Bit-1

Bit-0

0 0 1

IER

RD/WR

Modem

Stat. Int.

Enable

RX Line

Stat.

Int.

Enable

Empty

Int

Enable

Data

Int.

Enable

CTS#

Int.

Enable

RTS#

Int.

Enable

Xoff Int.

Enable

Sleep

Mode

Enable

0 1 0

ISR

FIFOs

Enabled

FIFOs

Enabled

INT

Source

Bit-3

INT

Source

Bit-2

INT

Source

Bit-1

INT

Source

Bit-0

INT

Source

Bit-5

INT

Source

Bit-4

0 1 0

FCR

RX FIFO

Trigger

RX FIFO

Trigger

DMA

Mode

Enable

FIFO

Reset

FIFO

Reset

FIFOs

Enable

TX FIFO

Trigger

TX FIFO

Trigger

0 1 1

LCR

RD/WR

Divisor
Enable

Set TX

Break

Set Par-

ity

Even

Parity

Enable

Stop

Bits

Word

Length

Bit-1

Word

Length

Bit-0

1 0 0

MCR

RD/WR

Internal

Lopback

Enable

INT Out-

put

Enable

(OP2#)

Rsvd

(OP1#)

RTS#

Output

Control

DTR#

Output

Control

LCR[7] = 0

BRG

Pres-

caler

IR Mode

ENable

XonAny

1 0 1

LSR

RX FIFO

Global

Error

THR &

TSR

Empty

THR

Empty

Break

RX Fram-

ing Error

Parity

Error

Over-

run

Error

Data

Ready

1 1 0

MSR

CD#

Input

RI#

Input

DSR#

Input

CTS#

Input

Delta

CD#

Delta

RI#

Delta

DSR#

Delta

CTS#

1 1 1

SPR

RD/WR

Bit-7

Bit-6

Bit-5

Bit-4

Bit-3

Bit-2

Bit-1

Bit-0

LCR[7] = 0

FCTR[6]=0

1 1 1

EMSR

Rsvd

Auto

RTS

Hyst.

bit-3

Auto

RTS

Hyst.

bit-2

Rsvd

Rx/Tx

FIFO

Count

Rx/Tx

FIFO

Count

LCR[7] = 0

FCTR[6]=1

1 1 1

FLVL

Bit-7

Bit-6

Bit-5

Bit-4

Bit-3

Bit-2

Bit-1

Bit-0

áç

XR16C854/854D

REV. 3.0

2.97V TO 5.5V QUAD UART WITH 128-BYTE FIFO

Baud Rate Generator Divisor

0 0 0

DLL

RD/WR

Bit-7

Bit-6

Bit-5

Bit-4

Bit-3

Bit-2

Bit-1

Bit-0

LCR[7] = 1

LCR

0xBF

0 0 1

DLM

RD/WR

Bit-7

Bit-6

Bit-5

Bit-4

Bit-3

Bit-2

Bit-1

Bit-0

0 0 0

DREV

Bit-7

Bit-6

Bit-5

Bit-4

Bit-3

Bit-2

Bit-1

Bit-0

LCR[7] = 1

LCR

0xBF

DLL=0x00

DLM=0x00

0 0 1

DVID

Enhanced Registers

0 0 0

TRG

Bit-7

Bit-6

Bit-5

Bit-4

Bit-3

Bit-2

Bit-1

Bit-0

LCR=0

0 0 0

Bit-7

Bit-6

Bit-5

Bit-4

Bit-3

Bit-2

Bit-1

Bit-0

0 0 1

FCTR

RD/WR

RX/TX

Mode

SCPAD

Swap

Trig

Table

Bit-1

Trig

Table

Bit-0

Auto

RS485

Direction

Control

RX IR

Input

Inv.

Auto
RTS
Hyst
Bit-1

Auto
RTS
Hyst
Bit-0

0 1 0

EFR

RD/WR

Auto

CTS#

Enable

Auto

RTS#

Enable

Special

Char

Select

Enable

IER [7:4],
ISR [5:4],

FCR[5:4],

MCR[7:5]

Soft-

ware

Flow

Cntl

Bit-3

Soft-
ware
Flow

Cntl

Bit-2

Soft-
ware
Flow

Cntl

Bit-1

Soft-
ware
Flow

Cntl

Bit-0

1 0 0

XON1

RD/WR

Bit-7

Bit-6

Bit-5

Bit-4

Bit-3

Bit-2

Bit-1

Bit-0

1 0 1

XON2

RD/WR

Bit-7

Bit-6

Bit-5

Bit-4

Bit-3

Bit-2

Bit-1

Bit-0

1 1 0

XOFF1 RD/WR

Bit-7

Bit-6

Bit-5

Bit-4

Bit-3

Bit-2

Bit-1

Bit-0

1 1 1

XOFF2 RD/WR

Bit-7

Bit-6

Bit-5

Bit-4

Bit-3

Bit-2

Bit-1

Bit-0

X X X

FSTAT

RX-

RDYD#

RX-

RDYC#

RX-

RDYB#

RX-

RDYA#

TX-

RDYD#

TX-

RDYC#

TX-

RDYB#

TX-

RDYA#

FSRS# pin is
a logic 0. No
address lines

required.

ABLE

9: INTERNAL REGISTERS DESCRIPTION.

HADED

BITS

ARE

ENABLED

WHEN

EFR B

-4=1

DDRESS

A2-A0

AME

EAD

RITE

-7

-6

-5

-4

-3

-2

-1

-0

OMMENT

XR16C854/854D

áç

2.97V TO 5.5V QUAD UART WITH 128-BYTE FIFO

REV. 3.0

4.0

INTERNAL REGISTER DESCRIPTIONS

4.1

Receive Holding Register (RHR) - Read- Only

See "Receiver" on page 15.

4.2

Transmit Holding Register (THR) - Write-Only

See "Transmitter" on page 14.

4.3

Interrupt Enable Register (IER) - Read/Write

The Interrupt Enable Register (IER) masks the interrupts from receive data ready, transmit empty, line status
and modem status registers. These interrupts are reported in the Interrupt Status Register (ISR).

4.3.1

IER versus Receive FIFO Interrupt Mode Operation

When the receive FIFO (FCR BIT-0 = 1) and receive interrupts (IER BIT-0 = 1) are enabled, the RHR interrupts
(see ISR bits 2 and 3) status will reflect the following:

A. The receive data available interrupts are issued to the host when the FIFO has reached the programmed

trigger level. It will be cleared when the FIFO drops below the programmed trigger level.

B. FIFO level will be reflected in the ISR register when the FIFO trigger level is reached. Both the ISR register

status bit and the interrupt will be cleared when the FIFO drops below the trigger level.

C. The receive data ready bit (LSR BIT-0) is set as soon as a character is transferred from the shift register to

the receive FIFO. It is reset when the FIFO is empty.

4.3.2

IER versus Receive/Transmit FIFO Polled Mode Operation

When FCR BIT-0 equals a logic 1 for FIFO enable; resetting IER bits 0-3 enables the XR16C854 in the FIFO
polled mode of operation. Since the receiver and transmitter have separate bits in the LSR either or both can
be used in the polled mode by selecting respective transmit or receive control bit(s).

A. LSR BIT-0 indicates there is data in RHR

RX FIFO.

B. LSR BIT-1 indicates an overrun error has occurred and that data in the FIFO may not be valid.

C. LSR BIT 2-4 provides the type of receive data errors encountered for the data byte in RHR, if any.

D. LSR BIT-5 indicates THR is empty.

E. LSR BIT-6 indicates when both the transmit FIFO and TSR are empty.

LSR BIT-7 indicates a data error in at least one character in the RX FIFO.

IER[0]: RHR Interrupt Enable

The receive data ready interrupt will be issued when RHR has a data character in the non-FIFO mode

or when

the receive FIFO has reached the programmed trigger level in the FIFO mode.

Logic 0 = Disable the receive data ready interrupt (default).

Logic 1 = Enable the receiver data ready interrupt.

IER[1]: THR Interrupt Enable

This bit enables the Transmit Ready interrupt which is issued whenever the THR becomes empty in the non-
FIFO mode or when data in the FIFO falls below the programmed trigger level in the FIFO mode. If the THR is
empty when this bit is enabled, an interrupt will be generated.

Logic 0 = Disable Transmit Ready interrupt (default).

Logic 1 = Enable Transmit Ready interrupt.

IER[2]: Receive Line Status Interrupt Enable

If any of the LSR register bits 1, 2, 3 or 4 is a logic 1, it will generate an interrupt to inform the host controller
about the error status of the current data byte in FIFO. These LSR bits generate an interrupt immediately when
the character has been received.

Logic 0 = Disable the receiver line status interrupt (default).

Logic 1 = Enable the receiver line status interrupt.

áç

XR16C854/854D

REV. 3.0

2.97V TO 5.5V QUAD UART WITH 128-BYTE FIFO

IER[3]: Modem Status Interrupt Enable

Logic 0 = Disable the modem status register interrupt (default).

Logic 1 = Enable the modem status register interrupt.

IER[4]: Sleep Mode Enable (requires EFR[4] = 1)

Logic 0 = Disable Sleep Mode (default).

Logic 1 = Enable Sleep Mode.

See "Sleep Mode with Auto Wake-Up" on page 20.

IER[5]: Xoff Interrupt Enable (requires EFR[4]=1)0

Logic 0 = Disable the software flow control, receive Xoff interrupt (default).

Logic 1 = Enable the software flow control, receive Xoff interrupt. See Software Flow Control section for
details.

IER[6]: RTS# Output Interrupt Enable (requires EFR[4]=1)

Logic 0 = Disable the RTS# interrupt (default).

Logic 1 = Enable the RTS# interrupt. The UART issues an interrupt when the RTS# pin makes a transition
from low to high.

IER[7]: CTS# Input Interrupt Enable (requires EFR[4]=1)

Logic 0 = Disable the CTS# interrupt (default).

Logic 1 = Enable the CTS# interrupt. The UART issues an interrupt when CTS# pin makes a transition from
low to high.

4.4

Interrupt Status Register (ISR) - Read-Only

The UART provides multiple levels of prioritized interrupts to minimize external software interaction. The
Interrupt Status Register (ISR) provides the user with six interrupt status bits. Performing a read cycle on the
ISR will give the user the current highest pending interrupt level to be serviced, others are queued up to be
serviced next. No other interrupts are acknowledged until the pending interrupt is serviced. The Interrupt
Source Table,

Table 10

, shows the data values (bit 0-5) for the interrupt priority levels and the interrupt sources

associated with each of these interrupt levels.

4.4.1

Interrupt Generation:

LSR is by any of the LSR bits 1, 2, 3 and 4.

RXRDY is by RX trigger level.

RXRDY Time-out is by a 4-char plus 12 bits delay timer.

TXRDY is by TX trigger level or TX FIFO empty (or transmitter empty in auto RS-485 control).

MSR is by any of the MSR bits 0, 1, 2 and 3.

Receive Xoff/Special character is by detection of a Xoff or Special character.

CTS# is when its transmitter toggles the input pin (from low to high) during auto CTS flow control.

RTS# is when its receiver toggles the output pin (from low to high) during auto RTS flow control.

4.4.2

Interrupt Clearing:

LSR interrupt is cleared by a read to the LSR register.

RXRDY interrupt is cleared by reading data until FIFO falls below the trigger level.

RXRDY Time-out interrupt is cleared by reading RHR.

TXRDY interrupt is cleared by a read to the ISR register or writing to THR.

MSR interrupt is cleared by a read to the MSR register.

Xoff interrupt is cleared by a read to ISR or when Xon character(s) is received.

Special character interrupt is cleared by a read to ISR or after the next character is received.

RTS# and CTS# flow control interrupts are cleared by a read to the MSR register.

XR16C854/854D

áç

2.97V TO 5.5V QUAD UART WITH 128-BYTE FIFO

REV. 3.0

]

ISR[0]: Interrupt Status

Logic 0 = An interrupt is pending and the ISR contents may be used as a pointer to the appropriate interrupt
service routine.

Logic 1 = No interrupt pending (default condition).

ISR[3:1]: Interrupt Status

These bits indicate the source for a pending interrupt at interrupt priority levels (See Interrupt Source Table 10).

ISR[5:4]: Interrupt Status

These bits are enabled when EFR bit-4 is set to a logic 1. ISR bit-4 indicates that the receiver detected a data
match of the Xoff character(s). Note that once set to a logic 1, the ISR bit-4 will stay a logic 1 until a Xon
character is received. ISR bit-5 indicates that CTS# or RTS# has changed state.

ISR[7:6]: FIFO Enable Status

These bits are set to a logic 0 when the FIFOs are disabled. They are set to a logic 1 when the FIFOs are
enabled.

4.5

FIFO Control Register (FCR) - Write-Only

This register is used to enable the FIFOs, clear the FIFOs, set the transmit/receive FIFO trigger levels, and
select the DMA mode. The DMA and FIFO modes are defined as follows:

FCR[0]: TX and RX FIFO Enable

Logic 0 = Disable the transmit and receive FIFO (default).

Logic 1 = Enable the transmit and receive FIFOs. This bit must be set to logic 1 when other FCR bits are
written or they will not be programmed.

FCR[1]: RX FIFO Reset

This bit is only active when FCR bit-0 is a `1'.

Logic 0 = No receive

FIFO

reset (default)

Logic 1 = Reset the receive FIFO pointers and FIFO level counter logic (the receive shift register is not
cleared or altered). This bit will return to a logic 0 after resetting the FIFO.

ABLE

10: I

NTERRUPT

OURCE

AND

RIORITY

EVEL

RIORITY

ISR R

EGISTER

TATUS

ITS

OURCE

INTERRUPT

EVEL

-5

-4

-3

-2

-1

-0

LSR (Receiver Line Status Register)

RXRDY (Receive Data Time-out)

RXRDY (Received Data Ready)

TXRDY (Transmit Ready)

MSR (Modem Status Register)

RXRDY (Received Xoff or Special character)

CTS#, RTS# change of state

None (default)

áç

XR16C854/854D

REV. 3.0

2.97V TO 5.5V QUAD UART WITH 128-BYTE FIFO

FCR[2]: TX FIFO Reset

This bit is only active when FCR bit-0 is a `1'.

Logic 0 = No transmit FIFO reset (default).

Logic 1 = Reset the transmit FIFO pointers and FIFO level counter logic (the transmit shift register is not
cleared or altered). This bit will return to a logic 0 after resetting the FIFO.

FCR[3]: DMA Mode Select

Controls the behavior of the TXRDY# and RXRDY# pins. See DMA operation section for details.

Logic 0 = Normal Operation (default).

Logic 1 = DMA Mode.

FCR[5:4]: Transmit FIFO Trigger Select

(logic 0 = default, TX trigger level = one)

These 2 bits set the trigger level for the transmit FIFO. The UART will issue a transmit interrupt when the
number of characters in the FIFO falls below the selected trigger level, or when it gets empty in case that the
FIFO did not get filled over the trigger level on last re-load.

Table 11

below shows the selections. EFR bit-4

must be set to `1' before these bits can be accessed. Note that the receiver and the transmitter cannot use
different trigger tables. Whichever selection is made last applies to both the RX and TX side.

FCR[7:6]: Receive FIFO Trigger Select

(logic 0 = default, RX trigger level =1)

The FCTR Bits 5-4 are associated with these 2 bits. These 2 bits are used to set the trigger level for the receive
FIFO. The UART will issue a receive interrupt when the number of the characters in the FIFO crosses the
trigger level.

Table 11

shows the complete selections. Note that the receiver and the transmitter cannot use

different trigger tables. Whichever selection is made last applies to both the RX and TX side.

ABLE

11: T

RANSMIT

AND

ECEIVE

FIFO T

RIGGER

EVEL

ELECTION

FCTR

-5

FCTR

-4

FCR

-7

FCR

-6

FCR

-5

FCR

BIT

-4

ECEIVE

RIGGER

EVEL

RANSMIT

RIGGER

EVEL

OMPATIBILITY

1 (default)

Table-A. 16C550, 16C2550,
16C2552, 16C554, 16C580
compatible.

Table-B. 16C650A compatible.

áç

XR16C854/854D

REV. 3.0

2.97V TO 5.5V QUAD UART WITH 128-BYTE FIFO

LCR[3]: TX and RX Parity Select

Parity or no parity can be selected via this bit. The parity bit is a simple way used in communications for data
integrity check. See

Table 12

for parity selection summary below.

Logic 0 = No parity.

Logic 1 = A parity bit is generated during the transmission while the receiver checks for parity error of the
data character received.

LCR[4]: TX and RX Parity Select

If the parity bit is enabled with LCR bit-3 set to a logic 1, LCR BIT-4 selects the even or odd parity format.

Logic 0 = ODD Parity is generated by forcing an odd number of logic 1's in the transmitted character. The
receiver must be programmed to check the same format (default).

Logic 1 = EVEN Parity is generated by forcing an even number of logic 1's in the transmitted character. The
receiver must be programmed to check the same format.

LCR[5]: TX and RX Parity Select

If the parity bit is enabled, LCR BIT-5 selects the forced parity format.

LCR BIT-5 = logic 0, parity is not forced (default).

LCR BIT-5 = logic 1 and LCR BIT-4 = logic 0, parity bit is forced to a logical 1 for the transmit and receive
data.

LCR BIT-5 = logic 1 and LCR BIT-4 = logic 1, parity bit is forced to a logical 0 for the transmit and receive
data.

LCR[6]: Transmit Break Enable

When enabled, the Break control bit causes a break condition to be transmitted (the TX output is forced to a
"space', logic 0, state). This condition remains, until disabled by setting LCR bit-6 to a logic 0.

Logic 0 = No TX break condition (default).

Logic 1 = Forces the transmitter output (TX) to a "space", logic 0, for alerting the remote receiver of a line
break condition.

LCR[7]: Baud Rate Divisors Enable

Logic 0 = Data registers are selected (default).

Logic 1 = Divisor latch registers are selected.

ABLE

12: P

ARITY

SELECTION

LCR B

-5

LCR B

-4

LCR B

-3

ARITY

SELECTION

No parity

Odd parity

Even parity

Force parity to mark, "1"

Forced parity to space, "0"

XR16C854/854D

áç

2.97V TO 5.5V QUAD UART WITH 128-BYTE FIFO

REV. 3.0

4.7

Modem Control Register (MCR) or General Purpose Outputs Control - Read/Write

The MCR register is used for controlling the serial/modem interface signals or general purpose inputs/outputs.

MCR[0]: DTR# Output

The DTR# pin is a modem control output. If the modem interface is not used, this output may be used as a
general purpose output.

Logic 0 = Force DTR# output to a logic 1 (default).

Logic 1 = Force DTR# output to a logic 0.

MCR[1]: RTS# Output

The RTS# pin is a modem control output and may be used for automatic hardware flow control by enabled by
EFR bit-6. If the modem interface is not used, this output may be used as a general purpose output.

Logic 0 = Force RTS# output to a logic 1 (default).

Logic 1 = Force RTS# output to a logic 0.

MCR[2]: Reserved

OP1# is not available as an output pin on the 854. But it is available for use during Internal Loopback Mode. In
the Loopback Mode, this bit is used to write the state of the modem RI# interface signal. If OP1# output is
required for RS485 operation, use the XR16C864.

MCR[3]: INT Output Enable

Enable or disable INT outputs to become active or in three-state. This function is associated with the INTSEL
input, see below table for details. This bit is also used to control the OP2# signal during internal loopback
mode. INTSEL pin must be set to a logic zero during 68 mode.

Logic 0 = INT (A-D) outputs disabled (three state) in the 16 mode (default). During loopback mode, it sets
OP2# internally to a logic 1.

Logic 1 = INT (A-D) outputs enabled (active) in the 16 mode. During loopback mode, it sets OP2# internally
to a logic 0.

MCR[4]: Internal Loopback Enable

Logic 0 = Disable loopback mode (default).

Logic 1 = Enable local loopback mode, see loopback section and

Figure 13

MCR[5]: Xon-Any Enable

Logic 0 = Disable Xon-Any function (for 16C550 compatibility, default).

Logic 1 = Enable Xon-Any function. In this mode, any RX character received will resume transmit operation.
The RX character will be loaded into the RX FIFO , unless the RX character is an Xon or Xoff character and
the 854 is programmed to use the Xon/Xoff flow control.

ABLE

13: INT O

UTPUT

ODES

INTSEL

MCR
B

-3

INT A-D O

UTPUTS

16 M

ODE

Three-State

Active

áç

XR16C854/854D

REV. 3.0

2.97V TO 5.5V QUAD UART WITH 128-BYTE FIFO

MCR[6]: Infrared Encoder/Decoder Enable

Logic 0 = Enable the standard modem receive and transmit input/output interface (default).

Logic 1 = Enable infrared IrDA receive and transmit inputs/outputs. The TX/RX output/input are routed to the
infrared encoder/decoder. The data input and output levels conform to the IrDA infrared interface
requirement. The RX FIFO may need to be flushed upon enable. While in this mode, the infrared TX output
will be a logic 0 during idle data conditions.

MCR[7]: Clock Prescaler Select

The CLKSEL pin selects this function upon power up or reset. After the power up or reset, this register bit will
have control and can alter the logic state.

Logic 0 = Divide by one. The input clock from the crystal or external clock is fed directly to the Programmable
Baud Rate Generator without further modification, i.e., divide by one (default).

Logic 1 = Divide by four. The prescaler divides the input clock from the crystal or external clock by four and
feeds it to the Programmable Baud Rate Generator, hence, data rates become one forth.

4.8

Line Status Register (LSR) - Read Only

This register provides the status of data transfers between the UART and the host. If LSR bits 1-4 are
asserted, an interrupt will be generated immediately if IER bit-2 is enabled.

LSR[0]: Receive Data Ready Indicator

Logic 0 = No data in receive holding register or FIFO (default).

Logic 1 = Data has been received and is saved in the receive holding register or FIFO.

LSR[1]: Receiver Overrun Flag

Logic 0 = No overrun error (default).

Logic 1 = Overrun error. A data overrun error condition occurred in the receive shift register. This happens
when additional data arrives while the FIFO is full. In this case the previous data in the receive shift register is
overwritten. Note that under this condition the data byte in the receive shift register is not transferred into the
FIFO, therefore the data in the FIFO is not corrupted by the error.

LSR[2]: Receive Data Parity Error Tag

Logic 0 = No parity error (default).

Logic 1 = Parity error. The receive character in RHR does not have correct parity information and is suspect.
This error is associated with the character available for reading in RHR.

LSR[3]: Receive Data Framing Error Tag

Logic 0 = No framing error (default).

Logic 1 = Framing error. The receive character did not have a valid stop bit(s). This error is associated with
the character available for reading in RHR.

LSR[4]: Receive Break Tag

Logic 0 = No break condition (default).

Logic 1 = The receiver received a break signal (RX was a logic 0 for at least one character frame time). In the
FIFO mode, only one break character is loaded into the FIFO. The break indication remains until the RX input
returns to the idle condition, "mark" or logic 1.

LSR[5]: Transmit Holding Register Empty Flag

This bit is the Transmit Holding Register Empty indicator. The THR bit is set to a logic 1 when the last data byte
is transferred from the transmit holding register to the transmit shift register. The bit is reset to logic 0
concurrently with the data loading to the transmit holding register by the host. In the FIFO mode this bit is set
when the transmit FIFO is empty, it is cleared when the transmit FIFO contains at least 1 byte.

XR16C854/854D

áç

2.97V TO 5.5V QUAD UART WITH 128-BYTE FIFO

REV. 3.0

LSR[6]: THR and TSR Empty Flag

This bit is set to a logic 1 whenever the transmitter goes idle. It is set to logic 0 whenever either the THR or TSR
contains a data character. In the FIFO mode this bit is set to a logic 1 whenever the transmit FIFO and transmit
shift register are both empty.

LSR[7]: Receive FIFO Data Error Flag

Logic 0 = No FIFO error (default).

Logic 1 = A global indicator for the sum of all error bits in the RX FIFO. At least one parity error, framing error
or break indication is in the FIFO data. This bit clears when there is no more error(s) in any of the bytes in the
RX FIFO.

4.9

Modem Status Register (MSR) - Read Only

This register provides the current state of the modem interface input signals. Lower four bits of this register are
used to indicate the changed information. These bits are set to a logic 1 whenever a signal from the modem
changes state. These bits may be used for general purpose inputs when they are not used with modem
signals.

MSR[0]: Delta CTS# Input Flag

Logic 0 = No change on CTS# input (default).

Logic 1 = The CTS# input has changed state since the last time it was monitored. A modem status interrupt
will be generated if MSR interrupt is enabled (IER bit-3).

MSR[1]: Delta DSR# Input Flag

Logic 0 = No change on DSR# input (default).

Logic 1 = The DSR# input has changed state since the last time it was monitored. A modem status interrupt
will be generated if MSR interrupt is enabled (IER bit-3).

MSR[2]: Delta RI# Input Flag

Logic 0 = No change on RI# input (default).

Logic 1 = The RI# input has changed from a logic 0 to a logic 1, ending of the ringing signal. A modem status
interrupt will be generated if MSR interrupt is enabled (IER bit-3).

MSR[3]: Delta CD# Input Flag

Logic 0 = No change on CD# input (default).

Logic 1 = Indicates that the CD# input has changed state since the last time it was monitored. A modem
status interrupt will be generated if MSR interrupt is enabled (IER bit-3).

MSR[4]: CTS Input Status

CTS# pin may function as automatic hardware flow control signal input if it is enabled and selected by Auto
CTS (EFR bit-7). Auto CTS flow control allows starting and stopping of local data transmissions based on the
modem CTS# signal. A logic 1 on the CTS# pin will stop UART transmitter as soon as the current character
has finished transmission, and a logic 0 will resume data transmission. Normally MSR bit-4 bit is the
compliment of the CTS# input. However in the loopback mode, this bit is equivalent to the RTS# bit in the MCR
register. The CTS# input may be used as a general purpose input when the modem interface is not used.

MSR[5]: DSR Input Status

DSR#

(active high, logical 1). Normally this bit is the compliment of the DSR# input. In the loopback mode, this

bit is equivalent to the DTR# bit in the MCR register. The DSR# input may be used as a general purpose input
when the modem interface is not used.

MSR[6]: RI Input Status

RI# (active high, logical 1). Normally this bit is the compliment of the RI# input. In the loopback mode this bit is
equivalent to bit-2 in the MCR register. The RI# input may be used as a general purpose input when the
modem interface is not used.

XR16C854/854D

áç

2.97V TO 5.5V QUAD UART WITH 128-BYTE FIFO

REV. 3.0

EMSR[5:4]: Extended RTS Hysteresis

ABLE

15: A

UTO

RTS H

YSTERESIS

EMSR[7:6]: Reserved

4.12

FIFO Level Register (FLVL) - Read-Only

The FIFO Level Register replaces the Scratchpad Register (during a Read) when FCTR[6] = 1. Note that this
is not identical to the FIFO Data Count Register which can be accessed when LCR = 0xBF.

FLVL[7:0]: FIFO Level Register

This register provides the FIFO counter level for the RX FIFO or the TX FIFO or both depending on EMSR[1:0].

See Table 14

for details.

4.13

Baud Rate Generator Registers (DLL and DLM) - Read/Write

The concatenation of the contents of DLM and DLL gives the 16-bit divisor value which is used to calculate the
baud rate:

Baud Rate = (Clock Frequency / 16) / Divisor

See MCR bit-7 and the baud rate table also.

4.14

Device Identification Register (DVID) - Read Only

This register contains the device ID (0x14 for XR16C854). Prior to reading this register, DLL and DLM should
be set to 0x00.

4.15

Device Revision Register (DREV) - Read Only

This register contains the device revision information. For example, 0x01 means revision A. Prior to reading
this register, DLL and DLM should be set to 0x00.

4.16

Trigger Level (TRG) - Write-Only

User Programmable Transmit/Receive Trigger Level Register.

TRG[7:0]: Trigger Level Register

These bits are used to program desired trigger levels when trigger Table-D is selected. FCTR bit-7 selects
between programming the RX Trigger Level (a logic 0) and the TX Trigger Level (a logic 1).

EMSR

-5

EMSR

-4

FCTR

-1

FCTR

-0

RTS#

YSTERESIS

HARACTERS

)

±4

±6

±8

±16

±24

±32

±40

±44

±48

±52

±12

±20

±28

±36

áç

XR16C854/854D

REV. 3.0

2.97V TO 5.5V QUAD UART WITH 128-BYTE FIFO

4.17

FIFO Data Count Register (FC) - Read-Only

This register is accessible when LCR = 0xBF. Note that this register is not identical to the FIFO Level Count
Register which is located in the general register set when FCTR bit-6 = 1 (Scratchpad Register Swap). It is
suggested to read the FIFO Level Count Register at the Scratchpad Register location when FCTR bit-6 = 1.
See

Table 14

FC[7:0]: FIFO Data Count Register

Transmit/Receive FIFO Count. Number of characters in Transmit (FCTR[7] = 1) or Receive FIFO (FCTR[7] = 0)
can be read via this register.

4.18

Feature Control Register (FCTR) - Read/Write

This register controls the XR16C854 new functions that are not available in ST16C554 or ST16C654.

FCTR[1:0]: RTS Hysteresis

User selectable RTS# hysteresis levels for hardware flow control application. After reset, these bits are set to
"0" to select the next trigger level for hardware flow control. See

Table 15 on page 36

for more details.

FCTR[2]: IrDA RX Inversion

Logic 0 = Select RX input as encoded IrDA data (Idle state will be logic 0).

Logic 1 = Select RX input as inverted encoded IrDA data (Idle state will be logic 1).

FCTR[3]: Auto RS-485 Direction Control

The Auto RS-485 Direction Control is not available in the XR16C854. See XR16C864. However, this bit
changes the TX Ready Interrupt behavior. See

Table 3

FCTR[5:4]: Transmit/Receive Trigger Table Select

See

Table 11 on page 29

for more details.

FCTR[6]: Scratchpad Swap

Logic 0 = Scratch Pad register is selected as general read and write register. ST16C550 compatible mode.

Logic 1 = FIFO Count register (Read-Only), Enhanced Mode Select Register (Write-Only). Number of
characters in transmit or receive holding register can be read via scratch pad register when this bit is set.
Enhanced Mode Select Register is selected when it is written into.

FCTR[7]: Programmable Trigger Register Select

Logic 0 = Registers TRG and FC selected for RX.

Logic 1 = Registers TRG and FC selected for TX.

4.19

Enhanced Feature Register (EFR) - Read/Write

Enhanced features are enabled or disabled using this register. Bit 0-3 provide single or dual consecutive
character software flow control selection (see

Table 17

). When the Xon1 and Xon2 and Xoff1 and Xoff2 modes

are selected, the double 8-bit words are concatenated into two sequential characters. Caution: note that
whenever changing the TX or RX flow control bits, always reset all bits back to logic 0 (disable) before
programming a new setting.

ABLE

16: T

RIGGER

ABLE

ELECT

FCTR

-5

FCTR

-4

ABLE

Table-A (TX/RX)

Table-B (TX/RX)

Table-C (TX/RX)

Table-D (TX/RX)

XR16C854/854D

áç

2.97V TO 5.5V QUAD UART WITH 128-BYTE FIFO

REV. 3.0

EFR[3:0]: Software Flow Control Select

Single character and dual sequential characters software flow control is supported. Combinations of software
flow control can be selected by programming these bits.

EFR[4]: Enhanced Function Bits Enable

Enhanced function control bit. This bit enables IER bits 4-7, ISR bits 4-5, FCR bits 4-5, and MCR bits 5-7 to be
modified. After modifying any enhanced bits, EFR bit-4 can be set to a logic 0 to latch the new values. This
feature prevents legacy software from altering or overwriting the enhanced functions once set. Normally, it is
recommended to leave it enabled, logic 1.

Logic 0 = modification disable/latch enhanced features. IER bits 4-7, ISR bits 4-5, FCR bits 4-5, and MCR
bits 5-7 are saved to retain the user settings. After a reset, the IER bits 4-7, ISR bits 4-5, FCR bits 4-5, and
MCR bits 5-7are set to a logic 0 to be compatible with ST16C550 mode (default).

Logic 1 = Enables the above-mentioned register bits to be modified by the user.

EFR[5]: Special Character Detect Enable

Logic 0 = Special Character Detect Disabled (default).

Logic 1 = Special Character Detect Enabled. The UART compares each incoming receive character with
data in Xoff-2 register. If a match exists, the receive data will be transferred to FIFO and ISR bit-4 will be set
to indicate detection of the special character. Bit-0 corresponds with the LSB bit of the receive character. If
flow control is set for comparing Xon1, Xoff1 (EFR [1:0]= `10') then flow control and special character work
normally. However, if flow control is set for comparing Xon2, Xoff2 (EFR[1:0]= `01') then flow control works
normally, but Xoff2 will not go to the FIFO, and will generate an Xoff interrupt and a special character
interrupt, if enabled via IER bit-5.

ABLE

17: S

OFTWARE

LOW

ONTROL

UNCTIONS

EFR

BIT

-3

ONT

-3

EFR

BIT

-2

ONT

-2

EFR

BIT

-1

ONT

-1

EFR

BIT

-0

ONT

-0

RANSMIT

AND

ECEIVE

OFTWARE

LOW

ONTROL

No TX and RX flow control (default and reset)

No transmit flow control

Transmit Xon1, Xoff1

Transmit Xon2, Xoff2

Transmit Xon1 and Xon2, Xoff1 and Xoff2

No receive flow control

Receiver compares Xon1, Xoff1

Receiver compares Xon2, Xoff2

Transmit Xon1, Xoff1

Receiver compares Xon1 or Xon2, Xoff1 or Xoff2

Transmit Xon2, Xoff2

Receiver compares Xon1 or Xon2, Xoff1 or Xoff2

Transmit Xon1 and Xon2, Xoff1 and Xoff2,

Receiver compares Xon1 and Xon2, Xoff1 and Xoff2

No transmit flow control,

Receiver compares Xon1 and Xon2, Xoff1 and Xoff2

áç

XR16C854/854D

REV. 3.0

2.97V TO 5.5V QUAD UART WITH 128-BYTE FIFO

EFR[6]: Auto RTS Flow Control Enable

RTS# output may be used for hardware flow control by setting EFR bit-6 to logic 1. When Auto RTS is selected,
an interrupt will be generated when the receive FIFO is filled to the programmed trigger level and RTS de-
asserts to a logic 1 at the next upper trigger level/hysteresis level. RTS# will return to a logic 0 when FIFO data
falls below the next lower trigger level/hysteresis level. The RTS# output must be asserted (logic 0) before the
auto RTS can take effect. RTS# pin will function as a general purpose output when hardware flow control is
disabled.

Logic 0 = Automatic RTS flow control is disabled (default).

Logic 1 = Enable Automatic RTS flow control.

EFR[7]: Auto CTS Flow Control Enable

Automatic CTS Flow Control.

Logic 0 = Automatic CTS flow control is disabled (default).

Logic 1 = Enable Automatic CTS flow control. Data transmission stops when CTS# input de-asserts to logic
1. Data transmission resumes when CTS# returns to a logic 0.

4.20

Software Flow Control Registers (XOFF1, XOFF2, XON1, XON2) - Read/Write

These registers are used as the programmable software flow control characters xoff1, xoff2, xon1, and xon2.
For more details, see

Table 7 on page 19

4.21

FIFO Status Register (FSTAT) - Read/Write

This register is applicable only to the 100 pin QFP XR16C854. The FIFO Status Register provides a status
indication for each of the transmit and receive FIFO. These status bits contain the inverted logic states of the
TXRDY# A-D outputs and the (un-inverted) logic states of the RXRDY# A-D outputs. The contents of the FSTAT
register are placed on the data bus when the FSRS# pin (pin 76) is a logic 0. Also see FSRS# pin description.

FSTAT[3:0]: TXRDY# A-D Status Bits

Please see

Table 5 on page 13

for the interpretation of the TXRDY# signals.

FSTAT[7:4]: RXRDY# A-D Status Bits

Please see

Table 5 on page 13

for the interpretation of the RXRDY# signals.

áç

XR16C854/854D

REV. 3.0

2.97V TO 5.5V QUAD UART WITH 128-BYTE FIFO

Test 1: The following inputs remain steady at VCC or GND state to minimize Sleep current: A0-A2, D0-D7, IOR#, IOW#,
CSA#, CSB#, CSC#, and CSD#. Also, RXA, RXB, RXC, and RXD inputs idle at logic 1 state while asleep.

ELECTRICAL CHARACTERISTICS

ABSOLUTE MAXIMUM RATINGS

Power Supply Range

7 Volts

Voltage at Any Pin

GND-0.3 V to 7 V

Operating Temperature

-40

to +85

Storage Temperature

-65

to +150

Package Dissipation

500 mW

TYPICAL PACKAGE THERMAL RESISTANCE DATA (M

ARGIN

RROR

: = 15%)

Thermal Resistance (64-TQFP)

theta-ja = 49

C/W, theta-jc = 10

C/W

Thermal Resistance (68-PLCC)

theta-ja = 39

C/W, theta-jc = 17

C/W

Thermal Resistance (100-QFP)

theta-ja = 45

C/W, theta-jc = 12

C/W

DC ELECTRICAL CHARACTERISTICS

TA=0

C (-40

+85

FOR

INDUSTRIAL

GRADE

PACKAGE

), V

2.97

5.5V

YMBOL

ARAMETER

IMITS

3.3V

IMITS

5.0V

NITS

ONDITIONS

ILCK

Clock Input Low Level

-0.3

0.6

-0.5

0.6

IHCK

Clock Input High Level

2.4

VCC

3.0

VCC

Input Low Voltage

-0.3

0.8

-0.5

0.8

Input High Voltage

(For devices with top mark date code of "DC YYWW" and older)

2.0

VCC

2.2

VCC

Input High Voltage

(For devices with top mark date code of "F2 YYWW" and newer)

2.0

5.5

2.2

5.5

Output Low Voltage

0.4

= 6 mA

= 4 mA

Output High Voltage

2.0

2.4

= -6 mA

= -1 mA

Input Low Leakage Current

±10

Input High Leakage Current

±10

Input Pin Capacitance

Power Supply Current

SLEEP

Sleep Current

100

200

See Test 1

XR16C854/854D

áç

2.97V TO 5.5V QUAD UART WITH 128-BYTE FIFO

REV. 3.0

AC ELECTRICAL CHARACTERISTICS

TA=0

C (-40

+85

FOR

INDUSTRIAL

GRADE

PACKAGE

), V

2.97

5.5V

YMBOL

ARAMETER

IMITS

3.3

IMITS

5.0

NIT

ONDITIONS

CLK

Clock Pulse Duration

OSC

Oscillator Frequency

MHz

OSC

External Clock Frequency

MHz

TAS

Address Setup Time (16 Mode)

TAH

Address Hold Time (16 Mode)

TCS

Chip Select Width (16 Mode)

TRD

IOR# Strobe Width (16 Mode)

TDY

Read Cycle Delay (16 Mode)

TRDV

Data Access Time (16 Mode)

TDD

Data Disable Time (16 Mode)

TWR

IOW# Strobe Width (16 Mode)

TDY

Write Cycle Delay (16 Mode)

TDS

Data Setup Time (16 Mode)

TDH

Data Hold Time (16 Mode)

ADS

Address Setup (68 Mode)

ADH

Address Hold (68 Mode)

TRWS

R/W# Setup to CS# (68 Mode)

RDA

Read Data Access (68 mode)

TRDH

Read Data Hold (68 mode)

WDS

Write Data Setup (68 mode)

WDH

Write Data Hold (68 Mode)

TRWH

CS# De-asserted to R/W# De-asserted (68 Mode)

TCSL

CS# Strobe Width (68 Mode)

TCSD

CS# Cycle Delay (68 Mode)

TWDO

Delay From IOW# To Output

100 pF load

TMOD

Delay To Set Interrupt From MODEM Input

100 pF load

TRSI

Delay To Reset Interrupt From IOR#

100 pF load

TSSI

Delay From Stop To Set Interrupt

Bclk

TRRI

Delay From IOR# To Reset Interrupt

100 pF load

XR16C854/854D

áç

2.97V TO 5.5V QUAD UART WITH 128-BYTE FIFO

REV. 3.0

NOTICE

EXAR Corporation reserves the right to make changes to the products contained in this publication in order to
improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any
circuits described herein, conveys no license under any patent or other right, and makes no representation that
the circuits are free of patent infringement. Charts and schedules contained here in are only for illustration
purposes and may vary depending upon a user's specific application. While the information in this publication
has been carefully checked; no responsibility, however, is assumed for inaccuracies.

EXAR Corporation does not recommend the use of any of its products in life support applications where the
failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to
significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless
EXAR Corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has
been minimized; (b) the user assumes all such risks; (c) potential liability of EXAR Corporation is adequately
protected under the circumstances.

Datasheet January 2004.

Send your UART technical inquiry with technical details to hotline:

uarttechsupport@exar.com

Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited.

REVISION HISTORY

Date

Revision

Description

November 1999

Rev 1.0

Removed Preliminary designation.

February 2002

Rev 2.0

Changed to standard style format. Text descriptions were clarified and sim-
plified (eg. DMA operation, FIFO mode vs. Non-FIFO mode operations etc).
Corrected RTS Hysteresis character values in

Table 15

. Clarified timing dia-

grams. Renamed Rclk (Receive Clock) to Bclk (Baud Clock) and timing
symbols. Added T

, T

RWS

and T

RST

May 2003

Rev 2.1

Added patent number and updated Block Diagram.

June 2003

Rev 2.2

Added and updated device status in Ordering Information.

January 2004

Rev 3.0

Changed to standard style format. Clarified sleep mode conditions. Devices
with top mark date code of "F2 YYWW" and newer have 5V tolerant inputs
(except for XTAL1). Devices with top mark date code of "DC YYWW" and
older do not have 5V tolerant inputs.

áç

XR16C854/XR16C854D

3.3V AND 5V QUAD UART WITH 128-BYTE FIFO

REV. 2.0

TABLE OF CONTENTS

GENERAL DESCRIPTION................................................................................................. 1

EATURES

.................................................................................................................................................. 1

PPLICATIONS

............................................................................................................................................. 1

IGURE

1. XR16C854 B

LOCK

IAGRAM

.................................................................................................................................................. 1

IGURE

2. P

SSIGNMENT

100-

QFP P

ACKAGES

AND

68 M

ODE

............................................................................... 2

IGURE

3. P

SSIGNMENT

PLCC P

ACKAGES

AND

68 M

ODE

AND

TQFP P

ACKAGES

....................................................... 3

ORDERING

INFORMATION

............................................................................................................................. 3

PIN DESCRIPTIONS ......................................................................................................... 4

1.0 Product DESCRIPTION ........................................................................................................... 9
2.0 FUNCTIONAL DESCRIPTIONS ............................................................................................. 10

2.1 CPU I

NTERFACE

............................................................................................................................... 10

IGURE

4. XR16C854/854D T

YPICAL

NTEL

OTOROLA

ATA

NTERCONNECTIONS

........................................................................ 10

2.2 5-V

OLT

OLERANT

NPUTS

................................................................................................................ 11

2.3 D

EVICE

ESET

.................................................................................................................................. 11

2.4 D

EVICE

DENTIFICATION

AND

EVISION

.............................................................................................. 11

2.5 C

HANNEL

ELECTION

........................................................................................................................ 11

ABLE

1: C

HANNEL

A-D S

ELECT

16 M

ODE

........................................................................................................................................ 11

ABLE

2: C

HANNEL

A-D S

ELECT

68 M

ODE

........................................................................................................................................ 11

2.6 C

HANNELS

A-D I

NTERNAL

EGISTERS

............................................................................................... 12

2.7 INT O

UPUTS

FOR

HANNELS

A-D ..................................................................................................... 12

2.8 DMA M

ODE

...................................................................................................................................... 12

ABLE

3: INT P

INS

PERATION

FOR

RANSMITTER

FOR

HANNELS

A-D................................................................................................. 12

ABLE

4: INT P

PERATION

FOR

ECEIVER

FOR

HANNELS

A-D ........................................................................................................ 12

2.9 C

RYSTAL

SCILLATOR

XTERNAL

LOCK

NPUT

........................................................................... 13

IGURE

5. T

YPICAL

OSCILATOR

CONNECTIONSL

...................................................................................................................................... 13

2.10 P

ROGRAMMABLE

AUD

ATE

ENERATOR

....................................................................................... 13

ABLE

5: TXRDY#

AND

RXRDY# O

UTPUTS

FIFO

AND

DMA M

ODE

FOR

HANNELS

A-D................................................................... 13

2.11 T

RANSMITTER

................................................................................................................................. 14

2.11.1 Transmit Holding Register (THR) - Write Only ....................................................................................... 14
2.11.2 Transmitter Operation in non-FIFO Mode .............................................................................................. 14

IGURE

6. B

AUD

ATE

ENERATOR

AND

RESCALER

............................................................................................................................ 14

ABLE

6: T

YPICAL

DATA

RATES

WITH

14.7456 MH

CRYSTAL

EXTERNAL

CLOCK

.............................................................................. 14

2.11.3 Transmitter Operation in FIFO Mode ..................................................................................................... 15

2.12 R

ECEIVER

....................................................................................................................................... 15

IGURE

7. T

RANSMITTER

PERATION

NON

-FIFO M

ODE

...................................................................................................................... 15

IGURE

8. T

RANSMITTER

PERATION

FIFO

AND

LOW

ONTROL

ODE

............................................................................................. 15

2.12.1 Receive Holding Register (RHR) - Read-Only ....................................................................................... 16

IGURE

9. R

ECEIVER

PERATION

NON

-FIFO M

ODE

........................................................................................................................... 16

IGURE

10. R

ECEIVER

PERATION

FIFO

AND

UTO

RTS F

LOW

ONTROL

ODE

............................................................................... 16

2.13 A

UTO

RTS H

ARDWARE

LOW

ONTROL

.......................................................................................... 17

2.14 A

UTO

RTS H

YSTERESIS

................................................................................................................. 17

2.15 A

UTO

CTS F

LOW

ONTROL

........................................................................................................... 17

IGURE

11. A

UTO

RTS

AND

CTS F

LOW

ONTROL

PERATION

.............................................................................................................. 18

2.16 A

UTO

OFF

OFTWARE

) F

LOW

ONTROL

............................................................................... 19

2.17 S

PECIAL

HARACTER

ETECT

........................................................................................................ 19

2.18 I

NFRARED

ODE

............................................................................................................................. 19

ABLE

7: A

UTO

OFF

OFTWARE

) F

LOW

ONTROL

....................................................................................................................... 19

2.19 S

LEEP

ODE

WITH

UTO

AKE

-U

............................................................................................... 20

IGURE

12. I

NFRARED

RANSMIT

ATA

NCODING

AND

ECEIVE

ATA

ECODING

................................................................................. 20

2.20 I

NTERNAL

OOPBACK

..................................................................................................................... 21

IGURE

13. I

NTERNAL

OOP

ACK

HANNELS

A-D............................................................................................................................. 22

3.0 UART INTERNAL REGISTERS ............................................................................................. 23

ABLE

8: UART CHANNEL A AND B UART INTERNAL REGISTERS ............................................................................................. 23

ABLE

9: INTERNAL REGISTERS DESCRIPTION. S

HADED

BITS

ARE

ENABLED

WHEN

EFR B

-4=1 ................................................ 24

4.0 INTERNAL Register descriptions ........................................................................................ 26

4.1 R

ECEIVE

OLDING

EGISTER

(RHR) - R

EAD

- O

NLY

........................................................................... 26

XR16C854/XR16C854D

áç

3.3V AND 5V QUAD UART WITH 128-BYTE FIFO

REV. 2.0

4.2 T

RANSMIT

OLDING

EGISTER

(THR) - W

RITE

-O

NLY

......................................................................... 26

4.3 I

NTERRUPT

NABLE

EGISTER

(IER) - R

EAD

RITE

........................................................................... 26

4.3.1 IER versus Receive FIFO Interrupt Mode Operation................................................................................ 26
4.3.2 IER versus Receive/Transmit FIFO Polled Mode Operation .................................................................... 26

4.4 I

NTERRUPT

TATUS

EGISTER

(ISR) - R

EAD

-O

NLY

............................................................................ 27

4.4.1 Interrupt Generation: ................................................................................................................................ 27
4.4.2 Interrupt Clearing:..................................................................................................................................... 27

4.5 FIFO C

ONTROL

EGISTER

(FCR) - W

RITE

-O

NLY

............................................................................... 28

ABLE

10: I

NTERRUPT

OURCE

AND

RIORITY

EVEL

............................................................................................................................. 28

ABLE

11: T

RANSMIT

AND

ECEIVE

FIFO T

RIGGER

EVEL

ELECTION

.................................................................................................... 29

4.6 L

INE

ONTROL

EGISTER

(LCR) - R

EAD

RITE

................................................................................. 30

ABLE

12: P

ARITY

SELECTION

................................................................................................................................................................ 31

4.7 M

ODEM

ONTROL

EGISTER

(MCR)

ENERAL

URPOSE

UTPUTS

ONTROL

- R

EAD

RITE

........ 32

ABLE

13: INT O

UTPUT

ODES

............................................................................................................................................................ 32

4.8 L

INE

TATUS

EGISTER

(LSR) - R

EAD

NLY

..................................................................................... 33

4.9 M

ODEM

TATUS

EGISTER

(MSR) - R

EAD

NLY

............................................................................... 34

4.10 S

CRATCH

EGISTER

(SPR) - R

EAD

RITE

............................................................................... 35

4.11 E

NHANCED

ODE

ELECT

EGISTER

(EMSR) ................................................................................. 35

ABLE

14: S

CRATCHPAD

WAP

ELECTION

............................................................................................................................................ 35

ABLE

15: A

UTO

RTS H

YSTERESIS

...................................................................................................................................................... 36

4.12 FIFO L

EVEL

EGISTER

(FLVL) - R

EAD

-O

NLY

................................................................................... 36

4.13 B

AUD

ATE

ENERATOR

EGISTERS

(DLL

AND

DLM) - R

EAD

RITE

............................................... 36

4.14 D

EVICE

DENTIFICATION

EGISTER

(DVID) - R

EAD

NLY

.................................................................. 36

4.15 D

EVICE

EVISION

EGISTER

(DREV) - R

EAD

NLY

......................................................................... 36

4.16 T

RIGGER

EVEL

(TRG) - W

RITE

-O

NLY

............................................................................................. 36

4.17 FIFO D

ATA

OUNT

EGISTER

(FC) - R

EAD

-O

NLY

............................................................................ 37

4.18 F

EATURE

ONTROL

EGISTER

(FCTR) - R

EAD

RITE

.................................................................... 37

4.19 E

NHANCED

EATURE

EGISTER

(EFR) - R

EAD

RITE

...................................................................... 37

ABLE

16: T

RIGGER

ABLE

ELECT

....................................................................................................................................................... 37

ABLE

17: S

OFTWARE

LOW

ONTROL

UNCTIONS

............................................................................................................................... 38

4.20 S

OFTWARE

LOW

ONTROL

EGISTERS

(XOFF1, XOFF2, XON1, XON2) - R

EAD

RITE

............... 39

4.21 FIFO S

TATUS

EGISTER

(FSTAT) - R

EAD

RITE

............................................................................ 39

ABLE

18: UART RESET CONDITIONS FOR CHANNELS A-D ......................................................................................................... 40

ELECTRICAL CHARACTERISTICS ................................................................................41

BSOLUTE

AXIMUM

ATINGS

...................................................................................................................41

YPICAL

ACKAGE

HERMAL

ESISTANCE

ATA

ARGIN

RROR

: = 15%)............................................41

DC E

LECTRICAL

HARACTERISTICS

...........................................................................................................41

TA=0o to 70oC (-40o to +85oC for industrial grade package), Vcc is 2.97 to 5.5V........................................... 41

AC E

LECTRICAL

HARACTERISTICS

............................................................................................................42

TA=0

C (-40

+85

FOR

INDUSTRIAL

GRADE

PACKAGE

), V

2.97

5.5V ......................42

IGURE

14. C

LOCK

IMING

.................................................................................................................................................................... 43

IGURE

15. M

ODEM

NPUT

UTPUT

IMING

HANNELS

A-D............................................................................................................ 43

IGURE

16. 16 M

ODE

NTEL

) D

ATA

EAD

IMING

FOR

HANNELS

A-D ........................................................................................... 44

IGURE

17. 16 M

ODE

NTEL

) D

ATA

RITE

IMING

FOR

HANNELS

A-D.......................................................................................... 44

IGURE

18. 68 M

ODE

OTOROLA

) D

ATA

EAD

IMING

FOR

HANNELS

A-D .................................................................................. 45

IGURE

19. 68 M

ODE

OTOROLA

) D

ATA

RITE

IMING

FOR

HANNELS

A-D ................................................................................. 45

IGURE

20. R

ECEIVE

EADY

& I

NTERRUPT

IMING

-FIFO M

ODE

]

FOR

HANNELS

A-D .................................................................... 46

IGURE

21. T

RANSMIT

EADY

& I

NTERRUPT

IMING

-FIFO M

ODE

]

FOR

HANNELS

A-D .................................................................. 46

IGURE

22. R

ECEIVE

EADY

& I

NTERRUPT

IMING

[FIFO M

ODE

, DMA D

ISABLED

]

FOR

HANNELS

A-D .................................................. 47

IGURE

23. R

ECEIVE

EADY

& I

NTERRUPT

IMING

[FIFO M

ODE

, DMA E

NABLED

]

FOR

HANNELS

A-D ................................................... 47

IGURE

24. T

RANSMIT

EADY

& I

NTERRUPT

IMING

[FIFO M

ODE

, DMA M

ODE

ISABLED

]

FOR

HANNELS

A-D ...................................... 48

ACKAGE

IMENSIONS

..............................................................................................................................49

EVISION

ISTORY

....................................................................................................................................52

TABLE OF CONTENTS ................................................................................................................................. I

Document Outline

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: XR16C854D

Document Outline

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: XR16C854D