XRT4000

Universal Multiprotocol

Serial Interface

November 1998-2

Rev. 1.00

EXAR Corporation, 48720 Kato Road, Fremont, CA 95538

(510) 668-7000

FAX (510) 668-7017

FEATURES

Software-configurable multiprotocol serial
interface supporting:

V.35, V.36, EIA-530 (A), RS232
(V.28), X.21, RS449

One chip fully integrated solution (Internal
termination)

Contains 8 receivers and 8 transmitters for full
DTE and DCE support

Glitch filters on the control signals (Optional)

+5V, +12V, -6V power supplies required

Full support of loopbacks, data & clock inversion,
and echoed clock in DTE and DCE modes

Full support of most popular types of HDLC
controllers (single, double, and triple clocks
supported)

Internal oscillator for standalone DTE loopback
testing

Control signals can be registered and non-
registered

Control signals can be tri-stated for bus-based
designs

"Fail Safe" operation supported

ESD Protection Over + 2kV Range

APPLICATIONS

Data Service Units (DSU)

Routers

Access Multiplexers

GENERAL DESCRIPTION

The XRT4000 is a fully integrated multiprotocol serial
interface. It is a universal device because it supports
all of the popular serial physical interfaces such as
V.35, V.36, EIA-530 (A), RS232 (V.28), X.21 and
RS449. Furthermore it can easily be interfaced with
most common types of HDLC controllers. This
device contains 8 receivers and 8 transmitters. It is
a complete solution containing all of the required
source and load terminations in one 100 pin TQFP
package.

XRT4000 can be configured to operate in one of the
seven interfaces in either DTE and DCE modes of

operation and power down mode. It fully supports
echoed clock as well as clock and data inversion. An
elaborate set of loopbacks are supported in DTE and
DCE modes of operation. This eliminates the need
for external circuitry for loopback implementation.
The control signals such as RI, RL, DCD, DTR, DSR
are protected against glitches by internal filters.
These filters can be disabled. XRT4000 has an
internal oscillator which is used to create a clock
signal needed to conduct standalone diagnostics of
DTE equipment.

ORDER INFORMATION

Part No.

Package

Operating

Temperature Range

XRT4000CV

100 Pin TQFP

C to +70

XRT4000

Rev. 1.00

- 5 -

PIN CONFIGURATION

V D D

G N D

M 0

M 2

E N _ F L T R

E N _ T E R M

L A T C H *

V S S

G N D

C L K F S

M 1

T X 4 D

V D D

T X 4 B

T X 5 A

T X 4 A

T X 5 B

T X 8 D

G N D

T X 5 D

T X 8 O

V S S

L P *

V D D

T X 1 D

G N D

V S S

V D D

G N D

V S S

D T I N V *

C K I N V *

E N _ O S C *

2 C K / 3 C K *

R E G _ C L K

V D D

V R

V P P

N C

E _ 2 3 2 H *

V P P

V D D

N / C

G N D

V S S

N / C

EN_OUT*

VSS

VDD

RX8D

GND

RX8I

TR7

VSS

TX76D

TR6A

TR6B

DCE/DTE*

RX67D

RX5D

EC*

RX5B

RX5A

RX4A

RX4B

SLEW_CNTL

RX4D

GND

N/C

REG

RX1D

VDD

RX1B

RX1A

RX2A

RX2B

VSS

RX2D

VDD

GND

RX3D

GND

TR3B

TR3A

CM_TR3

VSS

TX3D

VDD

TX2D

CM_TX2

TX2B

TX2A

TX1A

TX1B

CM_TX1

6 0

1 0

2 0

7 0

100-Pin

T Q F P

X R T 4 0 0 0

XRT4000

Rev. 1.00

- 6 -

PIN DESCRIPTION

Pin

Symbol

DTE

Mode

DCE

Mode

Type

Function

VDD

Digital VDD for Receiver 1 - Connect to +5V

GND

Digital GND for Receiver 1

Mode Control - Mode Select Input 0; Internal 20K

pull-up

Mode Control - Mode Select Input 1; Internal 20K

pull-up

Mode Control - Mode Select Input 2; Internal 20K

pull-up

EN_FLTR

Enable Glitch Filter on Receiver 4, 5, 6, 7, 8 inputs.
Internal 20K

pull-down

EN_TERM

Enable input termination for Receiver 1, 2, 3 in V.11 Mode.
Internal 20K

pull-down

LATCH*

Mode Control Input Latch Enable - Logic 0: Changes on
M0, 1, 2, EN_FLTR, and EN_TERM pins cause mode
changes (input latches in transparent state).
Logic 1: Changes on these input pins do not cause mode
changes (input latches in latched state). Internal 20K

pull-

down

VSS

Digital VSS for Transmitter 4, 5, 6. Connect to -6V

VSS

Analog VSS for bias generation Connect to -6V

GND

Digital GND for Transmitter 7, 8

CLKFS

Internal Clock Generated - 500kHz

TX4D

D_RTS

D_CTS

Transmitter 4 - Digital Data Input from equipment

VDD

Digital VDD for Transmitter 4, 5, 6; Connect to +5V

TX4B

RTSB

CTSB

Transmitter 4 - Positive Data Differential Output to line

TX4A

RTSA

CTSA

Transmitter 4 - Negative Data Differential Output to line

TX5A

DTRA

DSRA

Transmitter 5 - Negative Data Differential Output to line

TX5B

DTRB

DSRB

Transmitter 5 - Positive Data Differential Output to line

GND

Digital GND for Transmitter 4, 5, 6

TX5D

D_DTR

D_DSR

Transmitter 5 - Digital Data Input from equipment

TX8D

D_RL

D_RI

Transmitter 8 - Digital Data Input from equipment

LP*

Loopback Enable - Active low; Logic 0: Loopback
enabled.
Logic 1: Loopback disabled. Internal 20K

pull-up

TX8O

RLA

RIA

Transmitter 8 - Single Ended Data Output to line

VSS

Digital VSS for Transmitter 7, 8; Connect to -6V

VDD

Digital VDD for Transmitter 7, 8; Connect to +5V

EN_OUT*

Output Enable for Receiver 5, 8; Internal 20K

pull-down

REG

Register Control - Logic 1: TX5D, TX8D signal values will
be latched on the positive edge of REG_CLK, Logic 0: The
Register flip-flop is bypassed therefore REG_CLK has no
effect on these signals. Internal 20K

pull-down

VSS

Analog VSS for Receiver 4, 5, 6; Connect to -6V

VDD

Analog VDD for Receiver 4, 5, 6; Connect to +5V

VDD

Analog VDD for Receiver 7, 8; Connect to +5V

RX8D

D_RI

D_RL

Receiver 8 - Digital Data Output to equipment

GND

Analog GND for Receiver 7, 8

RX8I

RIA

RLA

Receiver 8 - Single Ended Data Input from line

VSS

Analog VSS for Receiver 7, 8; Connect to -6V

Note: An asterisk (*) following a pin symbol indicates that the pin is active low.

Names begining with D_ are digital signals.

Names ending with B and A are the positive and negative polarities of differential signals respectively.

XRT4000

Rev. 1.00

- 7 -

PIN DESCRIPTION (CONT'D)

Pin

Symbol

DTE

Mode

DCE

Mode

Type

Function

TR7

LLA

I/O

DTE Mode - Transmitter 7 - Single Ended Data Output to line
DCE Mode - Receiver 7 - Single Ended Data Input from line

TX76D

D_LL

D_DCD

Digital Input - Refer to Mode Control Table

TR6A

DCDA

I/O

DTE Mode - Receiver 6 - Negative Data Differential Input
from line
DCE Mode - Transmitter 6 - Negative Data Differential
Output to line

TR6B

DCDB

I/O

DTE Mode - Receiver 6 - Positive Data Differential Input from
line
DCE Mode - Transmitter 6 - Positive Data Differential Output
to line

DCE/DTE*

LOW

HIGH

DCE/DTE Select - Selects operating mode. Logic 0: DTE
Mode. Logic 1: DCE Mode. Internal 20K

pull-up

RX67D

D_DCD

D_LL

Digital Output - Refer to Mode Control Table

RX5D

D_DSR

D_DTR

Receiver 5 - Digital Data Output to equipment

EC*

Enable Clock Mode - Active Low, Logic 0: Echoed Mode.
Logic 1: Normal Mode. Internal 20K

pull-up

RX5B

DSRB

DTRB

Receiver 5 - Positive Data Differential Input from line

RX5A

DSRA

DTRA

Receiver 5 - Negative Data Differential Input from line

RX4A

CTSA

RTSA

Receiver 4 - Negative Data Differential Input from line

RX4B

CTSB

RTSB

Receiver 4 - Positive Data Differential Input from line

SLEW_

CNTL

Analog Output - Resistor connected between this pin and
Ground controls transmitter output pulse rise and fall time in
V.10 or V.28 mode as specified in Figures 15 and 16
respectively.

RX4D

D_CTS

D_RTS

Receiver 4 - Digital Data Output to equipment

GND

Digital GND for Receiver 4, 5, 6

GND

Analog GND for bias generator.

VSS

Analog Substrate - Connect to -6V

E_232H*

High Speed RS-232 Enable - Logic 0: Enables high speed
RS-232 mode (drives 3K

in parallel with 1000pF at 256KHz).

Internal 20K

pull-up

VDD

Analog VDD for bias generation circuit; Connect to +5V

VPP

VPP - Connect to +12V supply

VPP

VPP - Connect to +12V supply

VR - Internally generated +2.2V Reference (Sources 20

maximum)

Note: An asterisk (*) following a pin symbol indicates that the pin is active low.

Names begining with D_ are digital signals.
Names ending with B and A are the positive and negative polarities of differential signals respectively

XRT4000

Rev. 1.00

- 8 -

Pin

Symbol

DTE

Mode

DCE

Mode

Type

Function

REG_CLK

Clock - For Transmitter 5, 8 input register. Internal 20K

pull-up

2CK/3CK*

2 or 3 Clock Select - Internal 20K

pull-up

Logic Don't Care: 1 Clock When Mode = X.21 (M2, M1, M0= 011)
Logic 0: 3 Clocks When Mode

X.21 (M2, M1, M0

011)

Logic 1: 2 Clocks When Mode

X.21 (M2, M1, M0

011)

EN_OSC*

Test Oscillator Enable - Active Low; Logic 0: Oscillator Enabled.
Logic 1: Oscillator Disabled. Internal 20K

pull-up

CKINV*

Invert Clock - Active Low; Logic 0: Clock Inverted.
Logic 1: Clock not Inverted. Internal 20K

pull-up

DTINV*

Invert Data - Active Low; Logic 0: Data Inverted.
Logic 1: Data not Inverted. Internal 20K

pull-up

VSS

Digital VSS for Transmitter 1, 2, 3 Output Drivers;
Connect to -6V

GND

Digital GND for Transmitter 1, 2, 3 Output Drivers

VDD

Digital VDD for Transmitter 1, 2, 3 Output Drivers;
Connect to +5V

VDD

Analog VDD for Transmitter 1, 2; Connect to +5V

VSS

Analog VSS for Transmitter 1, 2; Connect to -6V

GND

Analog GND for Transmitter 1, 2 "T" termination

TX1D

D_TXD

D_RXD

Transmitter 1- Digital Data Input from equipment

CM_TX1

AC GND - Transmitter 1 Output Termination center tap in V.35 mode

TX1B

TXDB

RXDB

Transmitter 1 - Positive Data Differential Output to line

TX1A

TXDA

RXDA

Transmitter 1 - Negative Data Differential Output to line

TX2A

SCTEA

RXCA

Transmitter 2 - Negative Data Differential Output to line

TX2B

SCTEB

RXCB

Transmitter 2 - Positive Data Differential Output to line

CM_TX2

AC GND - Transmitter 2 Output Termination center tap in V.35 mode

TX2D

D_SCTE

D_RXC

Transmitter 2 - Digital Data Input from equipment

VDD

Digital VDD for Receiver and Transmitter 1, 2, 3; Connect to +5V

TX3D

D_X

D_TXC

DTE Mode - Input not used
DCE Mode - Transmitter 3 - Digital Data Input from equipment

VSS

Digital VSS for Receiver and Transmitter 1, 2, 3; Connect to -6V

CM_TR3

DTE Mode - AC GND - Transmitter 3 Output Termination center tap
in V.35 mode
DCE Mode - AC GND - Receiver 3 Input Termination center tap in
V.35 mode

TR3A

TXCA

I/O

DTE Mode - Receiver 3 - Negative Data Differential Input from line.
DCE Mode - Transmitter 3 - Negative Data Differential Output to
line.

Note: An asterisk (*) following a pin symbol indicates that the pin is active low.

Names begining with D_ are digital signals.
Names ending with B and A are the positive and negative polarities of differential signals respectively

XRT4000

Rev. 1.00

- 9 -

Pin

Symbol

DTE

Mode

DCE

Mode

Type

Function

TR3B

TXCB

I/O

DCE Mode - Transmitter 3 - Positive Data Differential
Output to line
DTE Mode - Receiver 3 - Positive Data Differential Input
from line

GND

Analog GND for Receiver 1, 2, 3

RX3D

D_TXC

D_X

DTE Mode - Receiver 3- Digital Data Output to equipment
DCE Mode - Not used

VDD

Digital VDD for Receiver 2, 3; Connect to +5V

GND

Digital GND for Receiver 2, 3

RX2D

D_RXC

D_SCTE

Receiver 2 - Digital Data Output to equipment

VSS

Analog VSS for Receiver 1, 2, 3; Connect to -6V

RX2B

RXCB

SCTEB

Receiver 2 - Positive Data Differential Input from line

RX2A

RXCA

SCTEA

Receiver 2 - Negative Data Differential Input from line

RX1A

RXDA

TXDA

Receiver 2 - Negative Data Differential Input from line

RX1B

RXDB

TXDB

Receiver 2 - Positive Data Differential Input from line

VDD

Analog VDD for Receiver 1, 2, 3; Connect to +5V

100

RX1D

D_RXD

D_TXD

Receiver 1 - Digital Data Output to equipment

Note: An asterisk (*) following a pin symbol indicates that the pin is active low.

Names begining with D_ are digital signals.
Names ending with B and A are the positive and negative polarities of differential signals respectively.

XRT4000

Rev. 1.00

- 10 -

ELECTRICAL CHARCTERISTICS
Test Conditions: VDD = 5V, VSS = -6V, VPP = 12V (all

5%), TA = 25

Sybol

Parameter

Min

Typ

Max

Unitd

Interface

Supply Currents

VDD

Supply

Current

V.10, No Load

(DCE

Mode,

V.10, Full Load

All Digital

Pins=GND

EIA-530A, No Load

or VDD)

160

EIA-530A, Full Load

V.35, No Load on V.28 Drivers

V.35, Full Load on V.28
Drivers

RS232, No Load

RS232, Full Load

Power Down Mode

VSS

Supply

Current

V.10, No Load

(DCE

Mode,

V.10, Full Load

All Digital

Pins=GND

EIA-530A, No Load

or VDD)

EIA-530A, Full Load

V.35, No Load on V.28 Drivers

V.35, Full Load on V.28
Drivers

RS232, No Load

RS232, Full Load

Power Down Mode

VPP

Supply

Current

V.10, No Load

(DCE

Mode,

V.10, Full Load

All Digital

Pins =

GND

EIA-530A, No Load

or VDD)

EIA-530A, Full Load

V.35, No Load on V.28 Drivers

V.35, Full Load on V.28
Drivers

RS232, No Load

RS232, Full Load

Power Down Mode

Note 1: Absolute Maximum Ratings are those beyond which the safety of a device may be impaired.
Note 2: All currents into device pins are positive; all currents out of device are negative. All voltages are

referenced to device ground unless otherwise specified.

XRT4000

Rev. 1.00

- 11 -

ELECTRICAL CHARCTERISTICS (CONT'D)
Test Conditions: VDD = 5V, VSS = -6V, VPP = 12V (all

5%), TA = 25

Symbol

Parameter

Min

Typ

Max

Units

Conditions

Logic Inputs and Outputs

Logic Input High
Voltage

Logic Input Low
Voltage

0.8

Logic Input
Current

±250

With 20k

internal pull-up/down resistor

Output High
Voltage

4.5

IO = -4mA

Output Low
Voltage

0.3

0.8

IO = 4mA

OSR

Output Short-
Circuit Current

-60

VDD

OZR

Three-State
Output Current

±1

M0 = Ml = M2 = VDD 0V

VDD

V.11 Driver

Differential Output
Voltage

±2

Open Circuit
RL = 50

(Figure 6)

Change in
Magnitude of
Differential Output
Voltage

0.2

RL = 50

(Figure 6)

Common Mode
Output Voltage

3.0

RL = 50

(Figure 6)

Change in
Magnitude of
Common Mode
Output Voltage

0.2

RL = 50

(Figure 6)

Short-Circuit
Current

±150

VO = GND

Output Leakage
Current

±0.01

±100

-0.25V

0.25V, Power Off or

Driver Disabled

, t

Rise or Fall Time

(Figures 7, 11)

PLH

Input to Output

110

(Figures 7, 11)

PHL

Input to Output

110

(Figures 7, 11)

Inp. to Out.
Difference, |TPLH
- TPHL|

(Figures 7, 11)

SKEW

Output to Output
Skew

(Figures 7, 11)

referenced to device ground unless otherwise specified.

XRT4000

Rev. 1.00

- 12 -

ELECTRICAL CHARCTERISTICS (CONT'D)
Test Conditions: VDD = 5V, VSS = -6V, VPP = 12V (all

5%), TA = 25

Symbol

Parameter

Min

Typ

Max

Units

Conditions

V.11 Receiver

Input Threshold
Voltage

-0.2

0.2

-7V

VCM

VTH

Input Hysteresis

-7V

VCM

Input Current (A,
B)

±1

±1.5

-10V

VA,B

10V

Input Impedance

-10V

VA,B

10V

, t

Rise or Fall Time

(Figures 7, 12)

PLH

Input to Output

120

(Figures 7, 12)

PHL

Input to Output

120

(Figures 7, 12)

Inp. to Out.
Difference, |TPLH
- TPHL|

(Figures 7, 12)

V.35 Driver

Differential Output
Voltage

±0.44

±0.55

±0.66

With Load, (Figure 12)

Transmitter
Output High
Current

-12

-11

-10

VA, B = 0V

Transmitter
Output Low
Current

VA, B = 0V

Transmiter Output
Leakage Current

±0.01

±100

-0.25

VA,B

0.25V

, t

Rise or Fall Time

(Figures 8, 11)

PLH

Input to Output

(Figures 8, 11)

PHL

Input to Output

(Figures 8, 11)

Inp. to Out.
Difference, |TPLH
- TPHL|

(Figures 8, 11)

SKEW

Output to Output
Skew

(Figures 8, 11)

V.35 Receiver

Differential Input
Threshold Volt.

-0.2

0.2

-2V

(VA + VB)/2

2V (Figure 8)

Input Hysteresis

-2V

(VA + VB)/2

2V (Figure 8)

Input Current
(A,B)

±60

-10V

VA, B

10V

Input Impedance
(A, B)

175

-10V

VA, B

10V

, t

Rise or Fall Time

(Figures 8, 12)

PLH

Input to Output

120

(Figures 8, 12)

PHL

Input to Output

100

120

(Figures 8, 12)

Input to Output

Difference, ITPLH

- TPHLI

(Figures 8, 12)

referenced to device ground unless otherwise specified.

XRT4000

Rev. 1.00

- 13 -

ELECTRICAL CHARCTERISTICS (CONT'D)
Test Conditions: VDD = 5V, VSS = -6V, VPP = 12V (all

5%), TA = 25

Symbol

Parameter

Min

Typ

Max

Units

Conditions

V.10 Driver

Output Voltage

±4.0
±3.6

±6.0

V
V

Open Circuit, RL = 3.9k
RL = 450

(Figure 9)

Short-Circuit
Current

±100

VO = GND

Input Leakage
Current

±0.1

±100

-0.25

0.25V, Power Off or

Driver Disabled

, t

Rise or Fall Time

(Figures 9, 13), RL = 450

, CL = 100pF

RSLEW_CNTL = 10k

PLH

Input to output

(Figures 9, 13), RL = 450

, CL = 100pF

RSLEW_CNTL = 10k

PHL

Input to output

(Figures 9, 13), RL = 450

, CL = 100pF

RSLEW_CNTL = 10k

V.10 Receiver

Receiver Input
Threshold Voltage

-0.2

0.2

Receiver Input
Hysteresis

Receiver Input
Current

±1

±1.5

-10

10V

Receiver Input
Impedance

-10

10V

, t

Rise or Fall Time

(Figures 10, 14)

PLH

Input to Output

100

(Figures 10, 14)

PHL

Input to Output

100

(Figures 10, 14)

V.28 Driver

Output Voltage

±5

±5.5

±6

Open Circuit
RL = 3k (Figure 9)

Short-Circuit
Current

±100

VO = GND

Input Leakage
Current

±0.01

±100

-0.25

VCM

0.25V, Power Off or

Driver Disabled

Slew Rate

4.0

30.0

(Figures 9, 13), RL = 3k, CL = 2500pF

PLH

Input to output

(Figures 9, 13), RL = 3k, CL = 2500pF

PHL

Input to output

(Figures 9, 13), RL = 3k, CL = 2500pF

V.28 Receiver

THL

Input Low
Threshold Voltage

1.4

0.8

TLH

Input High
Threshold Voltage

2.0

1.4

Receiver Input
Hysteresis

0.1

0.4

1.0

Receiver Input
Impedance

-15

15V

, t

Rise or Fall Time

(Figures 10, 14)

PLH

Input to Output

120

(Figures 10, 14)

PHL

Input to Output

180

(Figures 10, 14)

XRT4000

Rev. 1.00

- 16 -

SYSTEM DESCRIPTION

It is important to describe the difference
between an electrical specification and a
physical interface specification. An electrical
specification defines the electrical characteristics
of a transmitter or receiver. These include
voltage, current, impedance levels, rise/fall
times and other similar parameters. Popular
electrical interfaces are V.10, V.11, V.35 and
V.28. A serial physical interface specification,
however, describes an interface in its entirety.
This description includes the names and
functions of all involved signals, the electrical
parameters of each of the signals, and the
connector type. Popular serial interface types
include V.35, RS232 (V.28), RS449, EIA-530(A),
X.21, and V.36. The XRT4000 contains a
sufficient number of receivers, transmitters and
transceivers to transport all of the signals
required for a physical serial interface. It has
control circuitry that can configure each driver
and receiver to the appropriate electrical levels
required by the specification for the selected
serial interface.

Figure 1 is a top level block diagram that shows
how the eight receivers and eight transmitters
present in the XRT4000 are grouped in three
modules named RTMOD1, RTMOD2, and
RTMOD3. A forth module labeled CONTROL
programs these receivers and transmitters with
the appropriate electrical levels for operation
with most popular standard serial interfaces
such as V.35, RS232, RS449, EIA-530(A), X.21,
and V.36. These interfaces are fully compliant
with international NET1 and NET2
specifications.

Figures 2, 3, 4, and 5 are a set of functional
block diagrams that give more detailed
information about the four modules shown in the
top-level diagram. The eight receivers and
transmitters are grouped in three different
categories according to the type of signals
transmitted or received. The categories are
denoted as RTMOD1 (Figure 2), RTMOD2
(Figure 3), RTMOD3 (Figure 4), and CONTROL
(Figure 5).

RTMOD1 Block

RTMOD1 is intended for the high speed data
and clock signals of a selected interface. This
block contains receivers RX1 and RX2,
transmitters TX1 and TX2, and bi-directional
transceiver TR3 which is composed of TX3 and
RX3. All of these devices may be programmed
with the electrical levels required for V.35, V.11,
V.10, or V.28 operating modes. In V.35 mode,
each transmitter has a common mode pin that is
connected to the center of the internal
termination. This pin should be bypassed to
ground with an external capacitor in order to
provide the best possible driver output stage
balance. In a system application, the TX1-RX1
pair and TX2-RX2 pair handle the TXD-RXD and
TXC-RXC high-speed interface signals
respectively. Transceiver TR3 is dedicated to
the SCTE signal for both DCE and DTE modes
of operation. It functions as a receiver for the
DTE mode and as a transmitter during the DCE
mode.

RTMOD2 Block

RTMOD2 contains receivers RX4 and RX5,
transmitters TX4 and TX5, and transceiver TR6
which is composed of TX6 and RX6. These
devices may be programmed with the electrical
levels required for V.11, V.10, or V.28 operating
modes. The RX4-TX4 pair are dedicated for
RTS and CTS signals while RX5-TX5 are
intended for DTR and DSR signals. Transceiver
TR3 handles the DCD signal which requires a
transmitter in the DCE and a receiver

in-the-

DTE mode.

RTMOD3 Block

RTMOD3 contains transceiver TR7, which is
composed of TX7 and RX7, receiver RX8 and
transmitter TX8. These devices, which may be
programmed with the electrical levels required
for V.10, or V.28 operating modes, are intended
for the LL, RL and RI signals.

XRT4000

Rev. 1.00

- 17 -

CONTROL Block

The CONTROL block contains the configuration
and bias generation circuitry required by
RTMOD1, RTMOD2, and RTMOD3. It includes
TTL to CMOS level shifters for the control signal
inputs which have either an internal 20 k

pull-

up or pull-down resistor as shown in Figure 5
and as described in the pin description. This
block also includes a reference voltage source,
bias voltage and current generators, and a slew
rate control circuit that is used in the V.10 and
V.28 modes. The physical interface
configuration is done by three control pins called
M0, M1 and M2. The logic levels present on
these three inputs are internally latched during a
positive transition of the LATCH* signal. The
functions of the eight possible combinations of
M0, M1 and M2 are described in Tables 1 and 2.

Power Requirements

Table 3, which contains the maximum and
minimum peak supply currents for each of the 3
supply voltages, provides the information
necessary for determining a system power
budget. Notice that maximum current is
required in the V.11 mode when TX1, TX2, and
TX3 are terminated with 100

. Minimum current

consumption occurs when none of the
transmitters are terminated and the device is not
in the V.35 mode.

Receiver and Transmitter Specifications

Tables 4 and 5, which are for the XRT4000
receiver and transmitter sections respectively,
summarize the electrical requirements for V.35,
V.11, V.10, and RS232 interfaces. These tables
provide virtually all of the electrical information
necessary to describe these 4 interfaces in a
concise form.

XRT4000

Rev. 1.00

- 18 -

CONTROL

DRIVER/RECEIVER PAIR AND CORRESPONDING SIGNAL NAME - DTE MODE

INTERFACE

INPUTS

TX1

RX1

TX2

RX2 TX3 RX3

TX4

RX4

TX5

RX5

TX6

RX6

TX7

RX7

TX8 RX8 STANDARD

TXD

RXD SCTE

RXC

TXC

RTS

CTS

DTR

DSR

DCD

Off

V.10

Off

EIA-530-A

Off

EIA-530, RS449, V.36

Off

Off X.21

Off

V.35

Off

RESERVED

Off

RS232

Off

Off POWER DOWN

Table 1. DTE Mode - Control Programming for Driver and Receiver Mode Selection

CONTROL

DRIVER/RECEIVER PAIR AND CORRESPONDING SIGNAL NAME - DCE MODE

INTERFACE

INPUTS

TX1

RX1

TX2

RX2

TX3

RX3

TX4

RX4

TX5

RX5

TX6

RX6

TX7

RX7

TX8

RX8

STANDARD

M1 M0 RXD TXD RXC SCTE TXC

CTS

RTS

DSR

DTR

DCD

Off

V.10

Off

EIA-530-A

Off

EIA-530, RS449, V.36

Off

OFF

Off

X.21

Off

V.35

Off

RESERVED

Off

RS232

Off

POWER DOWN

Table 2. DCE Mode - Control Programming for Driver and Receiver Mode Selection

Note: For the above tables:

Table

Representation

Corresponding

Electrical Level

Type

Signal

V.35

Differential

V.11

Differential

V.10

Single Ended

V.28/RS232

Single Ended

XRT4000

Rev. 1.00

- 19 -

Supply

Maximum Current

TX1-TX3 Drivers Terminated

with 100

in V.11 Mode

Minimum Current

None of the Drivers Terminated

(Non-V.35 Mode)

VDD (+5V)

160 mA

15 mA

VSS (-6V)

120 mA

20 mA

VPP (+12V)

40 mA

10 mA

Table 3. Maximum and Minimum Peak Supply Currents

V.35

V.11

V.10

RS232

Single-Ended or Differential

DIFF

Single-Ended

Max Signal Level

660 mV

6 V

15 V

Min Signal Level

440 mV

300 mV

3 V

Common-Mode Voltage

2 V

7 V

Note 1

N/A

Max Signal Peak Operation

2.66 V

10 V

15 V

Max Signal Peak no Damage

N/A

12 V

25 V

Rin Differential

100

10%

Note 2

N/A

Rin Common-Mode

150

15%

N/A

DC Rin Each Input to Ground

> 8K

< DC Rin < 7 K

Clock Frequency

20 MHz

20MHz

120KHz

256KHz

Table 4. Receiver Specifications

Note 1:

7 V on Receivers 1-6, not applicable for Receivers 7-8

Note 2: 100 to 150 Ohms terminated.

XRT4000

Rev. 1.00

- 20 -

V.35

V.11

V.10

RS232

Single-Ended or Differential

DIFF

Single-Ended

Max Signal Level

660 mV

RL= 100

< 6 V

RL=3900

4 <

< 6 V

RL=3900

6 V

3000

< RL <

7000

Min Signal Level

440 mV

RL= 100

2V <

>0.5 V0

RL=100

> 0.9 V0

RL= 450

5 V

3000

< RL <

7000

Offset Voltage

N/A

Vos

< 3V

N/A

Rout Differential

100

10%

100

N/A

Rout Common-Mode

150

15%

N/A

Rout Power Off

N/A

> 300

Output Slew Rate/Tr,Tf

20 ns

1ms

< 30 V/

Clock Frequency

20 MHz

120 KHz

256 KHz

Table 5. Transmitter Specification

V.10\V.28 Output Pulse Rise and Fall Time

SLEW_CNTL (pin 47) is an analog output that
controls transmitter pulse rise and fall time for
the V.10 and V.28 modes. Connecting a
resistor, RSLEW, having a value between 0 and
200 k

from this pin to ground controls the

rise/fall times for V.10 and the slew rate for V.28
as shown in Figures 15 and 16 respectively.

High-Speed RS232 Mode

When E_232H* (pin 55) is set to logic 0 in
RS232 mode, the transmitters are put is a
special high-speed RS232 mode that can drive
loads of 3000

in parallel with 1000pF at

speeds up to 256 KHz.

Power Down Mode

All transmitters and receivers may be powered
down by either setting the pins for control bits
M0, M1 and M2 to logic 1 or by leaving them
open.

Internal Cable Terminations

XRT4000 has fully integrated receiver and
transmitter cable terminations for high speed
signals (RXD, TXD, RXC, TXC, SCTE).

Therefore, no external resistors and/or switches
are necessary to implement the proper line
termination. The schematic diagrams given in
Figures 17 and 18 show the effective receiver
and transmitter terminations respectively for
each mode of operation. When a specific
electrical interface is selected by M0, M1 and
M2, the termination required for that interface is
also automatically chosen. The XRT4000
eliminates double termination problems and
makes point to multipoint operation possible in
the V.11 mode by providing the option for
disabling the internal input termination on high
speed receivers.

Glitch Filters

Occasional extraneous glitches on
control/handshake signal inputs such as CTS,
RTS, DTR and DSR can have damaging effects
on the integrity of a connection. The XRT4000
is equipped with lowpass filters on the input of
each of the receivers for the control and
handshake signals. These filters eliminate
glitches which are narrower than 10

s. The

user may disable these filters by setting
EN_FLTR to logic 0.

XRT4000

Rev. 1.00

- 21 -

Clock Inversion

Transmit Clock signal, TXC, has an inversion
option for both DTE and DCE modes of
operation. The user can invert the polarity of the
TXC by setting CKINV* to logic 0. In the DTE
mode, the incoming TXC signal from the line will
be inverted before it is routed to the system. In
DCE mode, the incoming TXC signal from the
system will be inverted before it is sent over the
line toward the remote DTE. This feature allows
a phase correction when there is a long cable
delay between the DTE and DCE. This
correction may be necessary in order to obtain
the desired clock-to-data phase relationship.

Data Inversion

Similar to TXC, there is a provision in the
XRT4000 to invert the TXD and RXD signals.
Once the Setting the DTINV* input to logic 0
enables an inverter at the output of RX1 and
input of TX1.

Registered Mode of Operation

The XRT4000 has integrated registers allowing
users the option of clocking the values of
DSR/DTR and RL/RI signals. This can be done
if the registered mode of operation is selected
(REG=1). In this case, the values of these
signals will be latched on the positive edge of
the REG_CLK signal. In the normal mode (REG
= 0), the registers on the path of the DSR/DTR
and RL/RI are bypassed and REG_CLK will
have no effect.

Similarly, the outputs of the receivers (RX5 and
RX8) can be disabled by setting the EN_OUT*
input high. This allows these drivers to be
connected directly to a microcontroller bus since
they can be enabled during read cycles and
disabled in other times.

This feature eliminates the need for external
registers when a microcontroller is used to
control (reading and writing) DSR/DTR and
RL/RI signals.

Loopbacks

XRT4000 contains internal logic to place the
interface in a loopback mode for test purposes.
The loopback feature is supported in both DTE
and DCE modes of operation and it can be
invoked by setting the LP* input at logic 0.
Possible loopback implementations are depicted
in the scenarios located at the end of this
document.

XRT4000

Rev. 1.00

- 23 -

Echoed Clock

The XRT4000 can interface with serial
controllers which have two or three clock pins.
Furthermore, it can handle interfaces (e.g. X.21)
which have only one clock. Information
contained in the Pin Description for the EC* and
2CK/3CK* pins shows how the user can select
the number of available clocks by applying the
appropriate logic levels to these inputs.

Self-contained DTE Loopback Testing

Equipment having a DTE interface obtains
timing information from another interface (DCE).
RXC and TXC are clocks which are sourced by
the DCE. A DTE device uses them to clock
data in/out of the interface. The SCTE clock is
generated by DTE using TXC or RXC which are
originated in the DCE. In summary, a DTE
equipment is a timing slave.

Occasionally it is beneficial to conduct testing of
a DTE interface without connecting it to its DCE
counterpart. Lack of a synchronization source
will make the standalone testing of DTE
equipment not possible. The XRT4000 has an
on-board oscillator which can be used as a
timing source while the DCE connection is
missing. This feature allows users to conduct
loopback testing on isolated equipment with a
DTE interface.

This mode is invoked if EN_OSC* is set to logic
0. This connects an internally generated clock
signal (32 kHz - 64 kHz) to the RX2D/RX3D
output. A standalone system test may be
performed by combining this feature with the
appropriate loopback mode.

Operational Scenarios

Visualizing features such as clock/data
inversion, echoed clock, and loopbacks, in DTE
and DCE modes makes configuring the
XRT4000 a non-trivial task. A series of 48
system level application diagrams located at the
end of the data sheet called "Scenarios" assist
users in understanding the benefits of these
different features. The internal XRT4000
connections required for a particular scenario
are made through MUX1 and MUX2 that are
shown on the block diagrams given in Figures 2
and 3 respectively. Table 6 contains the signal
routing information versus control input logic
level for MUX1 and Table 7 contains similar
information for MUX2.

XRT4000

Rev. 1.00

- 24 -

APPLICATIONS INFORMATION

Traditional interfaces either require different
transmitters and receivers for each electrical
standard, or use complicated termination
switching methods to change modes of
operation. Mechanical switching schemes,
which are expensive and inconvenient, include
relays, and custom cables with the terminations
located in the connectors. Electrical switching
circuits using FETs are difficult to implement
because the FET must remain off when the
signal voltage exceeds the supply voltage and
when the interface power is off.

The XRT4000 uses innovative, patented circuit
design techniques to solve the termination
switching problem. This device includes internal
circuitry that may be controlled by software to
provide the correct terminations for V.10
(RS423), V.11 (RS422), V.28 (RS232), and V.35
electrical interfaces. The schematic diagrams
given in Figures 17 and 18 conceptually show
the switching options for the high-speed receiver
input and transmitter output terminations
respectively. Additionally, Tables 4 and 5
provide a summary of receiver and transmitter
specifications respectively for the different
electrical modes of operation.

V.10 (RS423) Interface

Figure 19 shows a typical V.10 (RS423)
interface. This configuration uses an
unbalanced cable to connect the transmitter
TXA output to the receiver RXA input. The "B"
outputs and inputs that are present on the
differential transmitters and receivers contained
in the XRT4000 are not used. The system
ground provides the signal return path. The
receiver input resistance is 10 k

nominal and

no other cable termination is normally used for
the V.10 mode.

V.11 (RS422) Interface

Figure 11 shows a typical V.11 (RS422)
interface. This configuration uses a balanced
cable to connect the transmitter TXA and TXB
outputs to the receiver RXA and RXB inputs
respectively. The XRT4000 includes provisions
for adding a 125

terminating resistor for the

V.11 mode. Although this resistor is optional in

the V.11 specification, it is necessary to prevent
reflections that would corrupt signals on high-
speed clock and data lines. The differential
receiver input resistance without the optional
termination is 20 k

nominal.

V.28 (RS232) Interface

Figure 19 shows a typical V.28 (RS232)
interface. This configuration uses an
unbalanced cable to connect the transmitter
TXA output to the receiver RXA input. The "B"
outputs and inputs that are present on the
differential transmitters and receivers contained
in the XRT4000 are not used. The system
ground provides the signal return path. The
receiver "B" input is internally connected to a 1.4
V reference source to provide a 1.4 V threshold.
The receiver input resistance is 5 k

nominal

and no other cable termination is normally used
for the V.28 mode.

V.35 Interface

Figure 21 shows a typical V.35 interface. This
configuration uses a balanced cable to connect
the transmitter TXA and TXB outputs to the
receiver RXA and RXB inputs respectively. The
XRT4000 internal terminations meets the
following V.35 requirements. The receiver
differential input resistance is 100

and

the shorted-terminal resistance (RXA and RXB
connected together) to ground is 150

The transmitter differential output resistance is
100

and the shorted-terminal

resistance (TXA and TXB connected together)
to ground is 150

15.

The junction of the 3 resistors (CMTX) on the
transmit termination is brought out to pins 76
and 81 for TX1 and TX2 respectively. Figure 21
shows how capacitor C having a value of 100 to
1000 pF bypasses this point to ground to reduce
common mode noise. This capacitor shorts
current caused by differential driver rise and fall
time or propagation delay miss-match directly to
ground. If it was not present, the flow of this
current through the 125

resistor to ground

would cause common mode voltage spikes at
the TXA and TXB outputs.

XRT4000

Rev. 1.00

- 27 -

Scenario Number

Logic Level Applied to

Control Input Name/Pin Number

Signal Source for

Output Name/Pin Number

DCE/
DTE*

EC*

2CK/

3CK*

LP*

INV*

_OSC*

RX1D

TX1B-TX1A

RX2D

TX2B-TX2A

RX3D

TR3B-TR3A

100

77,78

80,79

88,87

RX1B-RX1A

TX1D

RX2B-RX2A

TX2D

TR3B-TR3A

RX1B-RX1A

TX1D

RX2B-RX2A

TX2D

TX3D

TX1D

RX1B-RX1A

TX2D

RX2B-RX2A

TR3B-TR3A

TX1D

RX1B-RX1A

TX2D

RX2B-RX2A

TX3D

RX1B-RX1A

TX1D

RX2B-RX2A

TX2D

(TR3B-TR3A)*

RX1B-RX1A

TX1D

RX2B-RX2A

TX2D

(TX3D)*

TX1D

RX1B-RX1A

TX2D

RX2B-RX2A

(TR3B-TR3A)*

TX1D

RX1B-RX1A

TX2D

RX2B-RX2A

(TX3D)*

RX1B-RX1A

TX1D

RX2B-RX2A

TR3B-TR3A

RX1B-RX1A

TX1D

TX3D

TX2D

TX3D

TX1D

RX1B-RX1A

TX2D

TR3B-TR3A

TX1D

RX1B-RX1A

TX2D

TX3D

RX1B-RX1A

TX1D

RX2B-RX2A

(TR3B-TR3A)*

RX1B-RX1A

TX1D

TX3D

TX2D

(TX3D)*

TX1D

RX1B-RX1A

TX2D

(TR3B-TR3A)*

TX1D

RX1B-RX1A

TX2D

TX3D

(TX3D)*

RX1B-RX1A

TX1D

RX2B-RX2A

RX1B-RX1A

TX1D

TX2D

TX1D

RX1B-RX1A

TX2D

TR3B-TR3A

TX1D

RX1B-RX1A

TX2D

RX2B-RX2A

RX1B-RX1A

TX1D

RX2B-RX2A

(RX2B-RX2A)*

RX1B-RX1A

TX1D

(TX2D)*

TX2D

TX1D

RX1B-RX1A

TX2D

(RX2B-RX2A)*

TX1D

NOTE 1

TX2D

RX1B-RX1A

TX1D

RX2B-RX2A

TR3B-TR3A

RX1B-RX1A

TX1D

RX2B-RX2A

TX3D

TX1D

RX1B-RX1A

TR3B-TR3A

RX2B-RX2A

TR3B-TR3A

TX1D

RX1B-RX1A

TX3D

RX2B-RX2A

TX3D

RX1B-RX1A

TX1D

RX2B-RX2A

(TR3B-TR3A)*

RX1B-RX1A

TX1D

RX2B-RX2A

TX3D

(TX3D)*

TX1D

RX1B-RX1A

(TR3B-TR3A)*

RX2B-RX2A

(TR3B-TR3A)*

TX1D

RX1B-RX1A

TX3D

RX2B-RX2A

(TX3D)*

RX1B-RX1A

TX1D

RX2B-RX2A

TR3B-TR3A

RX1B-RX1A

TX1D

TX3D

TX1D

RX1B-RX1A

TR3B-TR3A

TX1D

RX1B-RX1A

TX3D

RX1B-RX1A

TX1D

RX2B-RX2A

(TR3B-TR3A)*

RX1B-RX1A

TX1D

TX3D

(TX3D)*

TX1D

RX1B-RX1A

(TR3B-TR3A)*

TX1D

RX1B-RX1A

TX3D

(TX3D)*

RX1B-RX1A

TX1D

RX2B-RX2A

RX1B-RX1A

TX1D

TX3D

TX1D

RX1B-RX1A

RX2B-RX2A

TX1D

RX1B-RX1A

TX3D

RX1B-RX1A

TX1D

RX2B-RX2A

(RX2B-RX2A)*

RX1B-RX1A

TX1D

(TX3D)*

TX3D

TX1D

RX1B-RX1A

RX2B-RX2A

TX1D

NOTE 1

TX3D

INVERT

UNCHANGED

32-64 kHz

UNCHANGED

32-64 kHz

UNCHANGED

32-64 kHz

UNCHANGED

Table 6. MUX1 Connection Table

Table entries are inputs to MUX1.
Column headings are outputs.
Signal names ending with A or B are analog inputs or outputs.

XRT4000

Rev. 1.00

- 28 -

Signal names ending with D are digital inputs or outputs. * Indicates signal complement. X is don't care.
Note 1: Refer to Figure 22 located on the next page for signal definition.

Figure 22. Signal Definition for Scenario Number 48

Scenario

Number

Control Input/

Pin Number

Signal Source for

Output Name/Pin Number

DCE/
DTE*

LP*

RX4D

TX4B-TX4A

RX5D

TX5B-TX5A

RX67D

TR6B-TR6A

TR7

15,16

18,17

38,37

TX4D

RX4B-RX4A

TX5D

TR6B-TR6A

TX5D

TX76D

RX4B-RX4A

TX4D

RX5B-RX5A

TX5D

TR6B-TR6A

TX76D

TX4D

RX4B-RX4A

TX76D

RX5B-RX5A

TR7

RX5B-RX5A

RX4B-RX4A

TX4D

RX5B-RX5A

TX5D

TR7

TX76D

Table 7. MUX2 Connection Table

Table entries are inputs to MUX2. Column headings are outputs.

Signal names ending with A or B are analog inputs or outputs. Signal names ending with D are digital
inputs or outputs.

XRT4000

Rev. 1.00

- 29 -

Operating Modes for the XRT4000 Device

The XRT4000 Multiprotocol Serial Interface
device can be configured to operate in a
wide variety of modes or "scenarios". This
document illustrates some of these
"scenarios" and provides the reader with the
following information associated with each of
these scenarios.

Which pins (on the "DCE Mode" XRT4000
and "DTE Mode" XRT4000 devices) are
used to propagate various data or clock
signals.

Which signals are to be used when
operating the XRT4000 devices in the
"differential" or "single-ended" modes.

How does one configure the "DCE Mode"
and "DTE Mode" XRT4000 device to
operate in these scenarios.

Notes:
1. The "line" signals are drawn with both a

"solid" line and a "dashed" line. Both lines
are used to transmit and receive "differential"
mode signals. However, the "solid" line
indentifies the signal that should be used,
when operating the Transmitter in the
"Single-Ended" mode.

2. Each scenarios includes a table that indicates

how to configure the XRT4000 device into
each of these modes, by specifying the
appropriate logic states for EC*, 2CK/3CK*,
LP*, CKINV*, DTINV*, and EN_OSC*.

3. In all, 48 scenarios have been defined for the

XRT4000 device. Currently, this document
only lists a subset of these scenarios.
Further versions of the XRT4000 data sheet
will include this information for all 48
scenarios.

XRT4000

Rev. 1.00

- 30 -

Scenarios 1 & 2

HDLC (R)

HDLC (L)

T4000 (DTE)

T4000 (DCE)

RX1

TX1

RX2

TX2

RX3

TX3

RX2

TX2

RX1

TX1

TXD

SCTE

TXC

RXC

RXD

TXD

SCTE

TXC

RXC

RXD

100

TXD

SCTE

TXC

RXC

RXD

Options

DTE

Normal

3 Clocks

No Loopback

No Invert

DCE

Echo Mode

2 Clocks

Loopback

Invert

1 Clock (X.21)

Input Pin Settings (Scenarios 1 & 2)

T4000 (DTE)

T4000 (DCE)

Pin Number

Name

State

Pin Number

Name

State

DCE/DTE*

EC*

2CK/3CK*

LP*

CKINV*

DTINV*

EN_OSC*

XRT4000

Rev. 1.00

- 31 -

Scenario 3

HDLC (R)

HDLC (L)

T4000 (DTE)

T4000 (DCE)

RX1

TX1

RX2

TX2

RX3

TX3

RX2

TX2

RX1

TX1

TXD

SCTE

TXC

RXC

RXD

TXD

SCTE

TXC

RXC

RXD

100

TXD

SCTE

TXC

RXC

RXD

Options

DTE

Normal

3 Clocks

No Loopback

No Invert

DCE

Echo Mode

2 Clocks

Loopback

Invert

1 Clock (X.21)

Input Pin Settings (Scenario 3)

T4000 (DTE)

T4000 (DCE)

Pin Number

Name

State

Pin Number

Name

State

DCE/DTE*

EC*

2CK/3CK*

LP*

CKINV*

DTINV*

EN_OSC*

XRT4000

Rev. 1.00

- 32 -

Scenario 4

HDLC (R)

HDLC (L)

T4000 (DTE)

T4000 (DCE)

RX1

TX1

RX2

TX2

RX3

TX3

RX2

TX2

RX1

TX1

TXD

SCTE

TXC

RXC

RXD

TXD

SCTE

TXC

RXC

RXD

100

TXD

SCTE

TXC

RXC

RXD

Options

DTE

Normal

3 Clocks

No Loopback

No Invert

DCE

Echo Mode

2 Clocks

Loopback

Invert

1 Clock (X.21)

Input Pin Settings (Scenario 4)

T4000 (DTE)

T4000 (DCE)

Pin Number

Name

State

Pin Number

Name

State

DCE/DTE*

EC*

2CK/3CK*

LP*

CKINV*

DTINV*

EN_OSC*

XRT4000

Rev. 1.00

- 33 -

Scenario 5

HDLC (R)

HDLC (L)

T4000 (DTE)

T4000 (DCE)

RX1

TX1

RX2

TX2

RX3

TX3

RX2

TX2

RX1

TX1

TXD

SCTE

TXC

RXC

RXD

TXD

SCTE

TXC

RXC

RXD

100

TXD

SCTE

TXC

RXC

RXD

Options

DTE

Normal

3 Clocks

No Loopback

No Invert

DCE

Echo Mode

2 Clocks

Loopback

Invert

1 Clock (X.21)

Input Pin Settings (Scenario 5)

T4000 (DTE)

T4000 (DCE)

Pin Number

Name

State

Pin Number

Name

State

DCE/DTE*

EC*

2CK/3CK*

LP*

CKINV*

DTINV*

EN_OSC*

XRT4000

Rev. 1.00

- 34 -

Scenario 6

HDLC (R)

HDLC (L)

T4000 (DTE)

T4000 (DCE)

RX1

TX1

RX2

TX2

RX3

TX3

RX2

TX2

RX1

TX1

TXD

SCTE

TXC

RXC

RXD

TXD

SCTE

TXC

RXC

RXD

100

TXD

SCTE

TXC

RXC

RXD

Options

DTE

Normal

3 Clocks

No Loopback

No Invert

DCE

Echo Mode

2 Clocks

Loopback

Invert

1 Clock (X.21)

Input Pin Settings (Scenarios 1 & 2)

T4000 (DTE)

T4000 (DCE)

Pin Number

Name

State

Pin Number

Name

State

DCE/DTE*

EC*

2CK/3CK*

LP*

CKINV*

DTINV*

EN_OSC*

XRT4000

Rev. 1.00

- 35 -

Scenario 7

HDLC (R)

HDLC (L)

T4000 (DTE)

T4000 (DCE)

RX1

TX1

RX2

TX2

RX3

TX3

RX2

TX2

RX1

TX1

TXD

SCTE

TXC

RXC

RXD

TXD

SCTE

TXC

RXC

RXD

100

TXD

SCTE

TXC

RXC

RXD

Options

DTE

Normal

3 Clocks

No Loopback

No Invert

DCE

Echo Mode

2 Clocks

Loopback

Invert

1 Clock (X.21)

Input Pin Settings (Scenarios 7)

T4000 (DTE)

T4000 (DCE)

Pin Number

Name

State

Pin Number

Name

State

DCE/DTE*

EC*

2CK/3CK*

LP*

CKINV*

DTINV*

EN_OSC*

XRT4000

Rev. 1.00

- 36 -

Scenario 8

HDLC (R)

HDLC (L)

T4000 (DTE)

T4000 (DCE)

RX1

TX1

RX2

TX2

RX3

TX3

RX2

TX2

RX1

TX1

TXD

SCTE

TXC

RXC

RXD

TXD

SCTE

TXC

RXC

RXD

100

TXD

SCTE

TXC

RXC

RXD

Options

DTE

Normal

3 Clocks

No Loopback

No Invert

DCE

Echo Mode

2 Clocks

Loopback

Invert

1 Clock (X.21)

Input Pin Settings (Scenario 8)

T4000 (DTE)

T4000 (DCE)

Pin Number

Name

State

Pin Number

Name

State

DCE/DTE*

EC*

2CK/3CK*

LP*

CKINV*

DTINV*

EN_OSC*

XRT4000

Rev. 1.00

- 37 -

Scenarios 9 & 10

HDLC (R)

HDLC (L)

T4000 (DTE)

T4000 (DCE)

RX1

TX1

RX2

TX2

RX3

TX3

RX2

TX2

RX1

TX1

TXD

SCTE

TXC

RXC

RXD

TXD

SCTE

TXC

RXC

RXD

100

TXD

TXC

RXC

RXD

Options

DTE

Normal

3 Clocks

No Loopback

No Invert

DCE

Echo Mode

2 Clocks

Loopback

Invert

1 Clock (X.21)

Input Pin Settings (Scenarios 9 & 10)

T4000 (DTE)

T4000 (DCE)

Pin Number

Name

State

Pin Number

Name

State

DCE/DTE*

EC*

2CK/3CK*

LP*

CKINV*

DTINV*

EN_OSC*

XRT4000

Rev. 1.00

- 38 -

Scenario 12

HDLC (R)

HDLC (L)

T4000 (DTE)

T4000 (DCE)

RX1

TX1

RX2

TX2

RX3

TX3

RX2

TX2

RX1

TX1

TXD

SCTE

TXC

RXC

RXD

TXD

SCTE

TXC

RXC

RXD

100

TXD

TXC

RXC

RXD

Options

DTE

Normal

3 Clocks

No Loopback

No Invert

DCE

Echo Mode

2 Clocks

Loopback

Invert

1 Clock (X.21)

Input Pin Settings (Scenario 12)

T4000 (DTE)

T4000 (DCE)

Pin Number

Name

State

Pin Number

Name

State

DCE/DTE*

EC*

2CK/3CK*

LP*

CKINV*

DTINV*

EN_OSC*

XRT4000

Rev. 1.00

- 39 -

Scenario 13

HDLC (R)

HDLC (L)

T4000 (DTE)

T4000 (DCE)

RX1

TX1

RX2

TX2

RX3

TX3

RX2

TX2

RX1

TX1

TXD

SCTE

TXC

RXC

RXD

TXD

SCTE

TXC

RXC

RXD

100

TXD

TXC

RXC

RXD

Options

DTE

Normal

3 Clocks

No Loopback

No Invert

DCE

Echo Mode

2 Clocks

Loopback

Invert

1 Clock (X.21)

Input Pin Settings (Scenario 13)

T4000 (DTE)

T4000 (DCE)

Pin Number

Name

State

Pin Number

Name

State

DCE/DTE*

EC*

2CK/3CK*

LP*

CKINV*

DTINV*

EN_OSC*

XRT4000

Rev. 1.00

- 40 -

Scenario 14

HDLC (R)

HDLC (L)

T4000 (DTE)

T4000 (DCE)

RX1

TX1

RX2

TX2

RX3

TX3

RX2

TX2

RX1

TX1

TXD

SCTE

TXC

RXC

RXD

TXD

SCTE

TXC

RXC

RXD

100

TXD

TXC

RXC

RXD

Options

DTE

Normal

3 Clocks

No Loopback

No Invert

DCE

Echo Mode

2 Clocks

Loopback

Invert

1 Clock (X.21)

Input Pin Settings (Scenario 14)

T4000 (DTE)

T4000 (DCE)

Pin Number

Name

State

Pin Number

Name

State

DCE/DTE*

EC*

2CK/3CK*

LP*

CKINV*

DTINV*

EN_OSC*

XRT4000

Rev. 1.00

- 41 -

Scenario 16

HDLC (R)

HDLC (L)

T4000 (DTE)

T4000 (DCE)

RX1

TX1

RX2

TX2

RX3

TX3

RX2

TX2

RX1

TX1

TXD

SCTE

TXC

RXC

RXD

TXD

SCTE

TXC

RXC

RXD

100

TXD

TXC

RXC

RXD

Options

DTE

Normal

3 Clocks

No Loopback

No Invert

DCE

Echo Mode

2 Clocks

Loopback

Invert

1 Clock (X.21)

Input Pin Settings (Scenario 16)

T4000 (DTE)

T4000 (DCE)

Pin Number

Name

State

Pin Number

Name

State

DCE/DTE*

EC*

2CK/3CK*

LP*

CKINV*

DTINV*

EN_OSC*

XRT4000

Rev. 1.00

- 42 -

Scenario 17 & 18

HDLC (R)

HDLC (L)

T4000 (DTE)

T4000 (DCE)

RX1

TX1

RX2

TX2

RX3

TX3

RX2

TX2

RX1

TX1

TXD

SCTE

TXC

RXC

RXD

TXD

SCTE

TXC

RXC

RXD

100

TXD

RXC

RXD

Options

DTE

Normal

3 Clocks

No Loopback

No Invert

DCE

Echo Mode

2 Clocks

Loopback

Invert

1 Clock (X.21)

Input Pin Settings (Scenario 17 & 18)

T4000 (DTE)

T4000 (DCE)

Pin Number

Name

State

Pin Number

Name

State

DCE/DTE*

EC*

2CK/3CK*

LP*

CKINV*

DTINV*

EN_OSC*

XRT4000

Rev. 1.00

- 43 -

Scenario 20

HDLC (R)

HDLC (L)

T4000 (DTE)

T4000 (DCE)

RX1

TX1

RX2

TX2

RX3

TX3

RX2

TX2

RX1

TX1

TXD

SCTE

TXC

RXC

RXD

TXD

SCTE

TXC

RXC

RXD

100

TXD

RXC

RXD

Options

DTE

Normal

3 Clocks

No Loopback

No Invert

DCE

Echo Mode

2 Clocks

Loopback

Invert

1 Clock (X.21)

Input Pin Settings (Scenario 20)

T4000 (DTE)

T4000 (DCE)

Pin Number

Name

State

Pin Number

Name

State

DCE/DTE*

EC*

2CK/3CK*

LP*

CKINV*

DTINV*

EN_OSC*

XRT4000

Rev. 1.00

- 44 -

Scenario 21

HDLC (R)

HDLC (L)

T4000 (DTE)

T4000 (DCE)

RX1

TX1

RX2

TX2

RX3

TX3

RX2

TX2

RX1

TX1

TXD

SCTE

TXC

RXC

RXD

TXD

SCTE

TXC

RXC

RXD

100

TXD

RXC

RXD

Options

DTE

Normal

3 Clocks

No Loopback

No Invert

DCE

Echo Mode

2 Clocks

Loopback

Invert

1 Clock (X.21)

Input Pin Settings (Scenario 21)

T4000 (DTE)

T4000 (DCE)

Pin Number

Name

State

Pin Number

Name

State

DCE/DTE*

EC*

2CK/3CK*

LP*

CKINV*

DTINV*

EN_OSC*

XRT4000

Rev. 1.00

- 45 -

Scenario 22

HDLC (R)

HDLC (L)

T4000 (DTE)

T4000 (DCE)

RX1

TX1

RX2

TX2

RX3

TX3

RX2

TX2

RX1

TX1

TXD

SCTE

TXC

RXC

RXD

TXD

SCTE

TXC

RXC

RXD

100

TXD

RXC

RXD

Options

DTE

Normal

3 Clocks

No Loopback

No Invert

DCE

Echo Mode

2 Clocks

Loopback

Invert

1 Clock (X.21)

Input Pin Settings (Scenario 22)

T4000 (DTE)

T4000 (DCE)

Pin Number

Name

State

Pin Number

Name

State

DCE/DTE*

EC*

2CK/3CK*

LP*

CKINV*

DTINV*

EN_OSC*

XRT4000

Rev. 1.00

- 46 -

Scenario 23

HDLC (R)

HDLC (L)

T4000 (DTE)

T4000 (DCE)

RX1

TX1

RX2

TX2

RX3

TX3

RX2

TX2

RX1

TX1

TXD

SCTE

TXC

RXC

RXD

TXD

SCTE

TXC

RXC

RXD

100

TXD

RXC

RXD

Options

DTE

Normal

3 Clocks

No Loopback

No Invert

DCE

Echo Mode

2 Clocks

Loopback

Invert

1 Clock (X.21)

Input Pin Settings (Scenario 23)

T4000 (DTE)

T4000 (DCE)

Pin Number

Name

State

Pin Number

Name

State

DCE/DTE*

EC*

2CK/3CK*

LP*

CKINV*

DTINV*

EN_OSC*

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: XRT4000

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: XRT4000