XR-T6166

...the analog plus company

Codirectional Digital Data

Processor

Rev. 2.02

1990

EXAR Corporation, 48720 Kato Road, Fremont, CA 94538

(510) 668-7000

(510) 668-7010

June 19973

FEATURES

Low Power CMOS Technology

All Receiver and Transmitter Inputs and Outputs are
TTL Compatible

Transmitter Inhibits Bipolar Violation Insertion for
Transmission of Alarm Conditions

Alarm Output Indicates Loss of Received Bipolar
Violations

Tolerance of 125

s Variance of Data Transfer

Timing in Both Transmit and Receive Paths
Allows Operation in Plesiochronous Networks

Both Receiver and Transmitter Perform Byte
Insertion or Deletion in Response to Local Clock
Slips and Provide Outputs Indicating Slip Logic
Activity

APPLICATIONS

CCITT G.703 Compliant 64kbps Codirectional
Interface

Performs the Digital and Analog Functions for
a Complete 64kbps Data Adaption Unit (DAU) When
Used With the XR-T6164

GENERAL DESCRIPTION

The XR-T6166 is a CMOS device which contains the
digital circuitry necessary to interface both directions of a
64kbps data stream to 2.048Mbps transmit and receive
PCM time-slots. The XR-T6166 and the companion
XR-T6164 line interface chip together form a CCITT
G.703 compliant 64kbps codirectional interface.

The XR-T6166 contains separate transmit and receive
sections. The transmitter transforms 8 bit serial data from
a 2.048Mbps time-slot into an encoded 64kbps data

stream. The receiver, which performs the reverse
operation, decodes the 64kbps data, extracts a clock
signal, and then outputs the data to a 2.048Mbps
time-slot. The XR-T6166 provides features which allow
the repetitions and deletions of both received and
transmitted data as clock skews and transients occur.
These slip occurrences are indicated by byte insertion
and deletion flags. Outputs are also provided for
extracted receive clock and clock recovery circuit loss of
lock.

ORDERING INFORMATION

Part No.

Package

Operating

Temperature Range

XR-T6166CP

28 Lead 600 Mil PDIP

C to +70

XR-T6166IP

28 Lead 600 Mil PDIP

C to 85

XR-T6166CD

28 Lead 300 Mil JEDEC SOIC

C to +70

XR-T6166ID

28 Lead 300 Mil JEDEC SOIC

C to 85

XR-T6166

Rev. 2.02

PIN CONFIGURATION

PCMOUT
RTSEL
BIR
BDR
TS2R

TS1R
CS
V

ALARM

S+R

S-R

BLS

RX2MHz

BLANK

RXCKOUT

TX2MHz

RXCK2MHz

PCMIN

TS1T

BIT

BDT

TX256kHz

TS2T

ALARMIN

T+R

TTSEL

T-R

28 Lead PDIP (0.600")

PCMOUT
RTSEL
BIR
BDR
TS2R

TS1R
CS
V

ALARM

S+R

S-R

BLS

RX2MHz

BLANK

RXCKOUT

TX2MHz

RXCK2MHz

PCMIN

TS1T

BIT

BDT

TX256kHz

TS2T

ALARMIN

T+R

TTSEL

T-R

28 Lead SOIC (Jedec, 0.300")

PIN DESCRIPTION

Pin #

Symbol

Type

Description

ALARM

Octet Timing Alarm. When active, indicates loss of received bipolar violations that are used
for octet timing. Active high.

S+R

Positive AMI Data to Receiver. Positive data from the XR-T6164 receive-side. Active low.

S-R

Negative AMI Data to Receiver. Negative data from the XR-T6164 receive-side. Active low.

BLS

Byte Locking Supervision. When active, causes blanking of PCMOUT under received
alarm conditions. Active low.

RX2MHz

Receiver 2.048MHz Clock. Used to clock out PCM data.

BLANK

PCMOUT Data Blanking. When active, forces PCMOUT data to all ones (AIS). Active high.

RXCKOUT

128kHz Extracted Clock. Clock recovered from received data.

+5V

10% Power Source.

RXCK2MHz

2.048MHz Clock. Used by receiver clock recovery circuit.

TS1T

Transmitter Time-slot 1 Input.

BDT

Transmitter Byte Deletion Flag. Active when a transmit byte is deleted. Active high.

TS2T

Transmitter Time-slot 2 Input.

T+R

Transmit Positive AMI Data Output. Data to XR-T6164 positive transmitter input. Active low.

T-R

Transmit Negative AMI Data Output. Data to XR-T6164 negative transmitter input. Active
low.

TTSEL

Transmit Time-slot Select. When high, pin 10 is selected; when low, pin 12 is selected.

ALARMIN

Alarm Input. When active, inhibits insertion of violations used for octet timing in transmitter
output. Active high.

XR-T6166

Rev. 2.02

PIN DESCRIPTION (CONT'D)

Pin #

Symbol

Type

Description

TX256kHz

Transmitter 256kHz Clock. Used to output 64kbps encoded data.

BIT

Transmitter Byte Insertion Flag. Active when a transmit byte is repeated. Active high.

PCMIN

Transmitter PCM Input. Data read from the system PCM bus.

TX2MHz

Transmitter 2.048MHz Clock. Clocks PCM data in PCMIN.

Ground.

Clock Seek. Indicates that clock recovery circuit has loss of lock with received data. Active
high.

TS1R

Receiver Time-slot 1 Input.

TS2R

Receiver Time-slot 2 Input.

BDR

Receiver Byte Deletion Flag. Active when received data byte is deleted. Active high.

BIR

Receiver Byte Insertion Flag. Active when a received data byte is repeated. Active high.

RTSEL

Receive Time-slot Select. When high, pin 23 is selected; when low, pin 24 is selected.

PCMOUT

Received PCM Output Data. Data sent to the system PCM bus.

XR-T6166

Rev. 2.02

ELECTRICAL CHARACTERISTICS
Test Conditions: V

= 5V

10%, T

= 25

C, Unless Otherwise Specified

Symbol

Parameter

Min.

Typ.

Max.

Unit

Conditions

DC Electrical Characteristics

Logic 1

2.4

Logic 0

0.4

Supply

4.5

5.5

Supply Current

500

Dynamic Supply Current

Input Leakage

0.4

At 1.6mA

2.4

At 0.4mA

AC Electrical Characteristics

General

tr, tf

Output Rise/Fall Time

All Outputs

Receiver

tRS

RX2MHz Rising Edge to TS
Rising Edge Set Up Time

tRXL-

100

Figure 3

tRH

RX2MHz Rising Edge to TS
Falling Edge Hold Time

tRXL-

100

Figure 3

tDRS

TS Rising Edge to Leading Edge
of PCMOUT D0 Bit Delay

Figure 3

tDRH

TS Falling Edge to Trailing Edge
of PCMOUT D7 Bit Hold Time

Figure 3

tRXD

RX2MHz Rising Egde to
PCMOUT Bits D1 Through D6
Rising Edge Delay

Figure 3

tPW

PCMOUT Pulse Width

488

Figure 3

tRXH

RX2MHz High Time

244

Figure 3

tRXL

RX2MHz Low Time

244

Figure 3

tRXCLK

RX2MHz Period

488

100ppm

Transmitter

tTS

TS Rising Edge to TX2MHz Set
Up Time

tTXL-

100

Figure 5

tTH

TS Falling Edge to TX2MHz Hold
Time

tTXL-

100

Figure 5

tDS

PCMIN Edge to TX2MHz Set Up
Time

100

Figure 5

tDH

PCMIN Edge to TX2MHz Hold
Time

100

Figure 5

tTXH

TX2MHz High Time

244

Figure 5

tTXL

TX2MHz Low Time

244

Figure 5

tTXCLK

TX2MHz Period

488

100ppm

XR-T6166

Rev. 2.02

ELECTRICAL CHARACTERISTICS (CONT'D)

Symbol

Parameter

Min.

Typ.

Max.

Unit

Conditions

AC Electrical Characteristics (Cont'd)

Transmitter (Cont'd)

tKXH

TX256kHz High Time

1.95

tKXL

TX256kHz Low Time

1.95

tKXCLK

TX256kHz Period

3.9063

tBDTH

BDT High Time

488

tBITH

BIT High Time

12.5

tALH

ALARMIN High Time

15.6

Specifications are subject to change without notice

ABSOLUTE MAXIMUM RATINGS

Supply Voltage

20V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Operating Temperature

C to +70

. . . . . . . . . . . . .

Storage Temperature

-65

C to +150

. . . . . . . . . . . .

Magnetic Supplier Information:

Pulse
Telecom Product Group
P.O. Box 12235
San Diego, CA 92112
Tel. (619) 674-8100
Fax. (619) 674-8262

Transpower Technologies, Inc.
24 Highway 28, Suite 202
Crystal Bay, NV 89402-0187
Tel. (702) 831-0140
Fax. (702) 831-3521

XR-T6166

Rev. 2.02

SYSTEM DESCRIPTION

Transmitter

Figure 1 shows the XR-T6166 transmitter section block
diagram. The transmitter converts eight bit bursts or
octets of 2.048Mbps serial data present in a PCM
time-slot to a coded continuous 64kbps data stream.
During operation, data input is controlled by external
clock and time-slot signals, and the 64kbps data output is
timed by an external 256kHz clock. Since the input and
output rates may not be exactly equal because of slight
clock rate differences, periodic slips can occur.
Therefore, circuitry is included to delete or repeat octets, if
necessary. Transmitter operation is as follows.

PCM data is applied to PCMIN (pin 19), a 2.048MHz local
clock is applied to TX2MHz (pin 20), and a time-slot signal
is applied through the time-slot multiplexer. This
multiplexer allows the transmitter to be hard wired to two
time-slot positions. A time-slot signal is applied to
multiplexer inputs TS1T (pin 10) or TS2T (pin 12), and a
time-slot select logic level is applied to TTSEL (pin 15). A
high level at TTSEL selects TS1T while a low level
enables TS2T. The time-slot is an envelope derived
externally from TX2MHz that covers eight clock pulses.
The rising edge of the time-slot signal should be made to
coincide with the falling edge of TX2MHz. Eight bits of
PCM data are clocked into the transmitter input register
on the rising edge of TX2MHz while the selected time-slot
signal is high. The input register data is then transferred
to a storage latch.

Transmission of 64kbps data is controlled by the 256kHz
local clock that is applied to TX256kHz (pin 17). It is not
necessary for this clock to be synchronized with any other
signals that are applied to the transmitter. The output
process begins by transferring data from the storage latch
to the output shift register after transmission of the
previous eight bits of data is complete. Four periods of
TX256kHz are required to encode each data bit. A "logic
0" applied to PCMIN is coded as 0101 while a "logic 1" is
coded as 0011. This data is output on either T+R (pin 13)
or T-R (pin 14) according to the AMI (alternate mark
inversion) coding rule. Note that the T+R and T-R outputs
as well as the corresponding XR-T6164 transmitter inputs
(TX+I/P, TX-I/P) are all active-low. Therefore, a "logic 0" is
coded as a 1010 and a "logic 1" as a 1100 at the bipolar
transmitter output as specified by CCITT G.703.
Transmission of octet timing is performed by feeding the

seventh and eighth data bits in each word to the same
transmitter output. This function may be inhibited by
setting ALARMIN (pin 16) high to transmit an alarm
condition.

Should skew occur between the TX2MHz and TX256kHz
clocks signals, or during an adjustment of the timing of the
time-slot signal, circuitry is included to delete or repeat
complete words of data. This could happen, for example,
when changing from one time-slot position to another.
Outputs are provided to indicate when a data byte is
inserted or deleted. A byte repetition or insertion occurs
once if no new PCM data is received. The BIT flag (pin 18)
is active during the transmission of inserted data. A byte
repetition just occurs once. If no new PCM data is
received, the T+R and T-R outputs stay high. A byte
deletion occurs when the transmitter receives a new byte
of data before the previous byte is transferred from the
storage latch to the output register. Under this condition,
the stored data is overwritten and the BDT flag (pin 11) is
active.

Receiver

Figure 2 shows the block diagram of the XR-T6166
receiver section. The receiver converts coded continuous
64kbps data to eight bit bursts of 2.048Mbps serial data
suitable for insertion in a PCM time-slot. During
operation, data input is timed by a clock that is extracted
from the input signal, while output is controlled by external
locally supplied clock and time-slot signals. Since the
data input and output rates may not be exactly equal,
circuitry is included to delete or repeat eight bit data
blocks, if necessary. Receiver operation is as follows.

A line interface chip such as the receive section of the
XR-T6164 converts the encoded bipolar 64kbps signal to
dual-rail active-low logic levels. These signals are
applied to the XR-T6166 receiver S+R (pin 2) and S-R
(pin 3) inputs. A 128kHz clock, which is derived from the
received signal, is used to decode this data, and then to
clock it into one of two storage registers. Two registers
are used so that one may be receiving continuous data at
64kbps while the other is sending eight bit bursts at a
2.048Mbps rate to PCMOUT (pin 28) while the receiver
time-slot signal is high. The time-slot is an envelope
derived externally from RX2MHz (pin 5) that covers eight
clock pulses. The rising edge of the time-slot signal
should be made to coincide with the rising edge of
RX2MHz. Eight bits of PCM data are clocked out of the
receiver register on the rising edge of RX2MHz while the

XR-T6166

Rev. 2.02

time-slot signal is high. A two input multiplexer at the
time-slot input allows the receiver to be hard wired to two
time-slot positions. time-slot signals are applied to TS1R
(pin 23) and TS2R (pin 24) and the active time-slot is
selected by RTSEL (pin 27). A high level applied to
RTSEL selects TS1R and a low level selects TS2R. Data
appearing at PCMOUT is framed by the read time-slot
signal and is guaranteed glitch free.

Recovery of the 128kHz timing signal is performed by a
variable length counter which is clocked by the 2.048MHz
signal applied to RXCK2MHz (pin 9). This clock is not
required to be synchronized with any other signals that
are applied to the XR-T6166. However, the RX2MHz
clock may also be used for this function. Positive input
data transitions are used to synchronize this counter with
the data. If synchronization is lost, the counter length is
shortened, and the clock recovery circuit enters a seek
mode until a transition is found. This mode is identified by
a high level at the CS output (pin 22). The extracted
128kHz signal is available at RXCKOUT (pin 7).

Octet timing ensures that bit grouping is maintained when
the data is converted from a 64kbps continuous stream to
eight bit 2.048Mbps bursts. Bipolar violations are used to
identify the last bit in each eight bit octet. In the absence of
these violations, for example when receiving a
transmitted alarm condition (transmitter ALARMIN is
high), the circuit will continue to operate in
synchronization with respect to the last received violation.
During this time, the data present at PCMOUT is still
correct as long as synchronization based on the last
received violation is still valid, and the BLS input (pin 4) is
held high. However, if BLS is low and an octet timing
violation is not received, receiver output data is blanked
by forcing PCMOUT to a high level. Also, if eight
successive octet timing violations are not received, the
ALARM output (pin 1) goes to a high level. A high level

applied to the BLANK input (pin 6) will also force
PCMOUT to an all-ones state.

Slip control logic is included in the receiver to
accommodate rate differences between input and output
data. The 64kbps input rate is determined by the remote
transmitter, while the PCMOUT rate is set by RX2MHz
which is a local clock. If this clock is slow, an octet will be
deleted periodically, while the last octet will be repeated
under fast conditions. Octet timing is maintained during
these operations. Outputs are provided to indicate when
an octet is inserted or deleted. The BIR flag (pin 26) is
high when PCMOUT data is repeated, and the BDR flag
(pin 25) is high when the receiver deletes an octet.

APPLICATION INFORMATION

64kbps Codirectional Interface

Figure 7 shows a codirectional interface circuit using the
XR-T6166 with the XR-T6164 line interface. The
XR-T6164 first converts the bipolar 64kbps transmit and
receive signals to active-low TTL compatible data
required by the XR-T6166. The XR-T6166 then performs
the digital functions that are necessary to interface this
64kbps continuous data to a 2.048Mbps PCM time-slot.
The 64kbps signals that have been attenuated and
distorted by the twisted pair cable are
transformer-coupled to the line side of the XR-T6164 as
shown on the left side of

Figure 7. A suggested

transformer for both the input and output applications is
the pulse type PE-65535.

The right side of

Figure 7 shows the XR-T6164 LOS (Loss

of Signal) output and the XR-T6166 digital inputs and
outputs. All of these pins are TTL compatible. Please
refer to the Pin Description section of this data sheet for
detailed information about each signal.

XR-T6166

Rev. 2.02

Loss of TX Sync

Byte Repeat Flag

Byte Delete Flag

T6164 LOS Output

Recovered CLK

Data to PCM Bus

CLK Seek Flag

ALARM

PCMOUT

BIR

BDR

RXCKOUT

BLS

RX2MHz

TS1R

TS2R

RTSEL

BLANK

RXCK2MHz

BDT

BIT

PCMIN

TX2MHz

TS1T

TS2T

TTSEL

TX256kHz

ALARMIN

S+R

S-R

T-R

T+R

XR-T6166

Receive

Side

Transmit

Side

+5V

0.1

+5V

0.1

1:2

480

RING

0.1

TIP

RX+I/P

RX-I/P

I/P BIAS

PEAK CAP

TX+O/P

TX-O/P

S+R

S-R

R
X
A

A
R

TX-I/P

TX+I/P

XR-T6164

Blank O/P for Alarm

time-slot 1

time-slot 2

time-slot Select

Forces All Ones

2.048MHz Clock

Byte Delete Flag

Byte Insert Flag

time-slot 1

time-slot 2

time-slot Select

Data from PCM Bus

Inhibit Violations

300

1:2

+5V

0.1

TIP

RING

64kbps Data

To Line

Figure 7. Typical Codirectional Application Circuit

2.048MHz Clock

256kHz Clock

PE-65535
TTI-17147

64kbps Data

To Line

XR-T6166

Rev. 2.02

Transmitter Code Conversion

Figure 8 shows the transmitter code conversion process
that CCITT G.703 specifies for a 64kbps codirectional
interface.

Step 1 - A 64kbps bit period is divided into four unit
intervals.

Step 2 - A binary 1 is coded as a 1100.

Step 3 - A binary 0 is coded as a 1010.

Step 4 - The binary signal is converted into a three-level
signal by alternating the polarity of consecutive blocks.

Step 5 - The alternation in polarity of the blocks is violated
every eighth block. The violation block marks the last bit
in an octet.

ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ

Bit Number

64kbps data

Steps 1-3

Step 4

Step 5

Octel Timing

Violation

Figure 8. Transmitter Code Conversion for a 64kbps Bipolar Line Signal

XR-T6166

Rev. 2.02

NOTICE

EXAR Corporation reserves the right to make changes to the products contained in this publication in order to im-
prove design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits de-
scribed herein, conveys no license under any patent or other right, and makes no representation that the circuits are
free of patent infringement. Charts and schedules contains herein are only for illustration purposes and may vary
depending upon a user's specific application. While the information in this publication has been carefully checked;
no responsibility, however, is assumed for inaccuracies.

EXAR Corporation does not recommend the use of any of its products in life support applications where the failure or
malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly
affect its safety or effectiveness. Products are not authorized for use in such applications unless EXAR Corporation
receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the
user assumes all such risks; (c) potential liability of EXAR Corporation is adequately protected under the circum-
stances.

Copyright 1990 EXAR Corporation
Datasheet June 1997
Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited.

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