Document Outline

• features
• applications
• block diagram of xrt7250
• ORDERING INFORMATION
• Table of Contents
• List of Figures
• List of Tables
• Pin Descriptions
• Electrical Characteristics
  • Absolute Maximums
  • DC Electrical Characteristics
  • AC Electrical Characteristics
  • AC Electrical Characteristics (Cont.)
  • 1.0 Timing Diagrams
    • Figure 1. Timing Diagram for Transmit Payload Input Interface, when the XRT7250 Device is operati...
    • Figure 2. Timing Diagram for the Transmit Payload Input Interface, when the XRT7250 Device is ope...
    • Figure 3. Timing Diagram for the Transmit Payload Data Input Interface, when the XRT7250 Device i...
    • Figure 4. Timing Diagram for the Transmit Payload Data Input Interface, when the XRT7250 Device i...
    • Figure 5. Timing Diagram for the Transmit Overhead Data Input Interface (Method 1 Access)
    • Figure 6. Timing Diagram for the Transmit Overhead Data Input Interface (Method 2 Access)
    • Figure 7. Transmit LIU Interface Timing - Framer is configured to update "TxPOS" and "TxNEG" on t...
    • Figure 8. Transmit LIU Interface Timing - Framer is configured to update "TxPOS" and "TxNEG" on t...
    • Figure 9. Receive LIU Interface Timing - Framer is configured to sample "RxPOS" and "RxNEG" on th...
    • Figure 10. Receiver LIU Interface Timing - Framer is configured to sample "RxPOS" and "RxNEG" on ...
    • Figure 11. Receive Payload Data Output Interface Timing
    • Figure 12. Receive Payload Data Output Interface Timing (Nibble Mode Operation)
    • Figure 13. Receive Overhead Data Output Interface Timing (Method 1 - Using RxOHClk)
    • Figure 14. Receive Overhead Data Output Interface Timing (Method 2 - Using RxOHEnable)
    • Figure 15. Microprocessor Interface Timing - Intel Type Programmed I/O Read Operations
    • Figure 16. Microprocessor Interface Timing - Intel Type Programmed I/O Write Operations
    • Figure 17. Microprocessor Interface Timing - Intel Type Read Burst Access Operation
    • Figure 18. Microprocessor Interface Timing - Intel Type Write Burst Access Operation
    • Figure 19. Microprocessor Interface Timing - Motorola Type Programmed I/O Read Operation
    • Figure 20. Microprocessor Interface Timing - Motorola Type Programmed I/O Write Operation
    • Figure 21. Microprocessor Interface Timing - Motorola Type Read Burst Access Operation
    • Figure 22. Microprocessor Interface Timing - Motorola Type Write Burst Access Operation
    • Figure 23. Microprocessor Interface Timing - Reset Pulse Width
  • 2.0 The Microprocessor Interface Block
    • Figure 24. Simple Block Diagram of the Microprocessor Interface Block, within the Framer IC
    • 2.1 The Microprocessor Interface Block Signal
      • Table 1: Description of the Microprocessor Interface Signals that exhibit constant roles in both ...
      • Table 2: Pin Description of Microprocessor Interface Signals - While the Microprocessor Interface...
      • Table 3: Pin Description of the Microprocessor Interface Signals while the Microprocessor Interfa...
    • 2.2 Interfacing the XRT7250 DS3/E3 Framer to the Local �C/�P via the Microprocessor Interface Block
      • 2.2.1 Interfacing the XRT7250 DS3/E3 Framer to the Microprocessor over an 8 bit wide bi-direction...
        • 2.2.1.1 Interfacing the Framer to the �C/�P over an 8-bit wide bi-directional data bus.
      • 2.2.2 Data Access Modes
        • 2.2.2.1 Data Access using Programmed I/O
      • Figure 25. Behavior of Microprocessor Interface signals during an Intel-type Programmed I/O Read ...
      • Figure 26. Behavior of the Microprocessor Interface Signals, during an Intel-type Programmed I/O ...
      • Figure 27. Illustration of the Behavior of Microprocessor Interface signals, during a Motorola- t...
      • Figure 28. Illustration of the Behavior of the Microprocessor Interface signal, during a Motorola...
        • 2.2.2.2 Data Access using Burst Mode I/O
      • Figure 29. Behavior of the Microprocessor Interface Signals, during the Initial Read Operation of...
      • Figure 30. Behavior of the Microprocessor Interface Signals, during subsequent Read Operations wi...
      • Figure 31. Behavior of the Microprocessor Interface signals, during the Initial Write Operation o...
      • Figure 32. Behavior of the Microprocessor Interface Signals, during subsequent Write Operations w...
      • Figure 33. Behavior of the Microprocessor Interface Signals, during the Initial Read Operation of...
      • Figure 34. Behavior the Microprocessor Interface Signals, during subsequent Read Operations withi...
      • Figure 35. Behavior of the Microprocessor Interface signals, during the Initial Write Operation o...
      • Figure 36. Behavior of the Microprocessor Interface Signals, during subsequent Write Operations w...
    • 2.3 On-Chip Register Organization
      • 2.3.1 Framer Register Addressing
      • Table 4: Register Addressing of the Framer Programmer Registers
        • 2.3.2 Framer Register Description
          • 2.3.2.1 Framer Operating Mode Register
          • 2.3.2.2 I/O Control Register
          • 2.3.2.3 Part Number Register
  • Part Number Register (Address = 0x02)
    • 2.3.2.4 Version Number Register
  • Version Number Register (Address = 0x03)
    • 2.3.2.5 Block Interrupt Enable Register
  • Block Interrupt Enable Register (Address = 0x04)
    • 2.3.2.6 Block Interrupt Status Register
  • Block Interrupt Status Register (Address = 0x05)
    • 2.3.2.7 Receive DS3 Configuration & Status Register
  • RxDS3 Configuration & Status Register (Address = 0x10)
    • 2.3.2.8 Receive DS3 Status Register
  • RxDS3 Status Register (Address = 0x11)
    • 2.3.2.9 Receive DS3 Interrupt Enable Register
  • RxDS3 Interrupt Enable Register (Address = 0x12)
    • 2.3.2.10 Receive DS3 Interrupt Status Register
  • RxDS3 Interrupt Status Register (Address = 0x13)
  • RxDS3 SYNC Detect Enable Register (Address = 0x14)
    • 2.3.2.11 Receive DS3 FEAC Register
    • 2.3.2.12 Receive DS3 FEAC Interrupt Enable/ Status Register
  • RxDS3 FEAC Interrupt Enable/Status Register (Address = 0x17)
    • 2.3.2.13 Receive DS3 LAPD Control Register
  • RxDS3 LAPD Control Register (Address = 0x18)
    • 2.3.2.14 Receive DS3 LAPD Status Register
  • RxDS3 LAPD Status Register (Address = 0x19)
    • 2.3.3 Receive E3 Framer Configuration Registers (ITU-T G.832)
      • 2.3.3.1 Receive E3 Configuration & Status Register 1 (E3, ITU-T G.832)
  • RxE3 Configuration & Status Register 1 (Address = 0x10)
    • 2.3.3.2 Receive E3 Configuration & Status Register 2 (E3, ITU-T G.832)
  • RxE3 Configuration & Status Register 2 (Address = 0x11)
    • 2.3.3.3 3.3.2.17 Receive E3 Interrupt Enable Register (E3, ITU-T G.832)
  • RxE3 Interrupt Enable Register - 1 (Address = 0x12)
    • 2.3.3.4 3.3.2.18 Receive E3 Interrupt Enable Register - 2 (E3, ITU-T G.832)
  • RxE3 Interrupt Enable Register - 2 (Address = 0x13)
    • 2.3.3.5 Receive E3 Interrupt Status Register - 1 (E3, ITU-T G.832)
  • RxE3 Interrupt Status Register - 1 (Address = 0x14)
    • 2.3.3.6 Receive E3 Interrupt Status Register - 2 (E3, ITU-T G.832)
  • RxE3 Interrupt Status Register - 2 (Address = 0x15)
    • 2.3.3.7 Receive E3 LAPD Control Register (E3, ITU-T G.832)
  • RxE3 LAPD Control Register (Address = 0x18)
    • 2.3.3.8 Receive E3 LAPD Status Register (E3, ITU-T G.832
  • RxE3 LAPD Status Register (Address = 0x19)
    • 2.3.3.9 Receive E3 NR Byte Register (E3, ITU-T G.832)
  • RxE3 NR Byte Register (Address = 0x1A)
    • 2.3.3.10 Receive E3 GC Byte Register (E3, ITU- T G.832)
  • RxE3 GC Byte Register (Address = 0x1B)
    • 2.3.3.11 Receive E3 TTB-0 Register (E3, ITU-T G.832)
  • RxE3 TTB-0 Register (Address = 0x1C)
    • 2.3.3.12 Receive E3 TTB-1 Register (E3, ITU-T G.832)
  • RxE3 TTB-1 Register (Address = 0x1D)
    • 2.3.3.13 Receive E3 TTB-2 Register (E3, ITU-T G.832)
  • RxE3 TTB-2 Register (Address = 0x1E)
    • 2.3.3.14 Receive E3 TTB-3 Register (E3, ITU-T G.832)
  • RxE3 TTB-3 Register (Address = 0x1F)
    • 2.3.3.15 Receive E3 TTB-4 Register (E3, ITU-T G.832)
  • RxE3 TTB-4 Register (Address = 0x20)
    • 2.3.3.16 Receive E3 TTB-5 Register (E3, ITU-T G.832)
  • RxE3 TTB-5 Register (Address = 0x21)
    • 2.3.3.17 Receive E3 TTB-6 Register (E3, ITU-T G.832)
  • RxE3 TTB-6 Register (Address = 0x22)
    • 2.3.3.18 Receive E3 TTB-7 Register (E3, ITU-T G.832)
  • RxE3 TTB-7 Register (Address = 0x23)
    • 2.3.3.19 Receive E3 TTB-8 Register (E3, ITU-T G.832)
  • RxE3 TTB-8 Register (Address = 0x24)
    • 2.3.3.20 Receive E3 TTB-9 Register (E3, ITU-T G.832)
  • RxE3 TTB-9 Register (Address = 0x25)
    • 2.3.3.21 Receive E3 TTB-10 Register (E3, ITU-T G.832)
  • RxE3 TTB-10 Register (Address = 0x26)
    • 2.3.3.22 Receive E3 TTB-11 Register (E3, ITU-T G.832)
  • RxE3 TTB-11 Register (Address = 0x27)
    • 2.3.3.23 Receive E3 TTB-12 Register (E3, ITU-T G.832)
  • RxE3 TTB-12 Register (Address = 0x28)
    • 2.3.3.24 Receive E3 TTB-13 Register (E3, ITU-T G.832)
  • RxE3 TTB-13 Register (Address = 0x29
    • 2.3.3.25 Receive E3 TTB-14 Register (E3, ITU-T G.832)
  • RxE3 TTB-14 Register (Address = 0x2A)
    • 2.3.3.26 Receive E3 TTB-15 Register (E3, ITU-T G.832)
  • RxE3 TTB-15 Register (Address = 0x2B)
    • 2.3.4 Receive E3 Framer Configuration Registers (ITU-T G.751)
      • 2.3.4.1 Receive E3 Framer Configuration & Status Register - 1 (E3, ITU-T G.751)
  • RxE3 Configuration & Status Register - 1 G.751 (Address = 0x10)
    • 2.3.4.2 Receive E3 Framer Configuration & Status Register -2 (E3, ITU-T G.751)
  • RxE3 Configuration & Status Register - 2 (Address = 0x11)
    • 2.3.4.3 Receive E3 Framer Interrupt Enable Register - 1 (E3, ITU-T G.751)
  • RxE3 Interrupt Enable Register - 1 (Address = 0x12)
    • 2.3.4.4 Receive E3 Interrupt Enable Register - 2 (E3, ITU-T G.751)
  • RxE3 Interrupt Enable Register - 2 (Address = 0x13)
    • 2.3.4.5 Receive E3 Interrupt Status Register - 1 (E3, ITU-T G.751)
  • RxE3 Interrupt Status Register - 1 (Address = 0x14)
    • 2.3.4.6 Receive E3 Interrupt Status Register - 2 (E3, ITU-T G.751)
  • RxE3 Interrupt Status Register - 2 (Address = 0x15)
    • 2.3.4.7 Receive E3 LAPD Control Register (E3, ITU-T G.751)
  • RxE3 LAPD Control Register (Address = 0x18)
    • 2.3.4.8 Receive E3 LAPD Status Register (E3, ITU-T G.751)
  • RxE3 LAPD Status Register (Address = 0x19)
    • 2.3.4.9 Receive E3 Service Bits Register (E3, ITU-T G.751)
  • RxE3 Service Bit Register (Address = 0x1A)
    • 2.3.5 Transmit DS3 Configuration Registers
      • 2.3.5.1 Transmit DS3 Configuration Register (DS3 Applications)
  • Transmit DS3 Configuration Register (Address = 0x30)
    • 2.3.5.2 Transmit DS3 FEAC Configuration & Status Register (DS3 Applications)
  • Transmit DS3 FEAC Configuration & Status Register (Address = 0x31)
    • 2.3.5.3 Transmit DS3 FEAC Register (DS3 Applications)
  • TxDS3 FEAC RegisTer (Address = 0x32)
    • 2.3.5.4 Transmit DS3 LAPD Configuration Register (DS3 Applications)
  • TxDS3 LAPD Configuration Register (Address = 0x33)
    • 2.3.5.5 Transmit DS3 LAPD Status and Interrupt Register (DS3 Applications)
  • TxDS3 LAPD Status and Interrupt Register (Address = 0x34)
    • 2.3.5.6 Transmit DS3 M-Bit Mask Register (DS3 Applications)
  • TxDS3 M-Bit Mask Register (Address = 0x35)
    • 2.3.5.7 Transmit DS3 F-Bit Mask Register - 1 (DS3 Applications)
  • TxDS3 F-Bit Mask Register - 1 (Address = 0x36)
    • 2.3.5.8 Transmit DS3 F-Bit Mask Register - 2 (DS3 Applications)
  • TxDS3 F-Bit Mask Register - 2 (Address = 0x37)
    • 2.3.5.9 Transmit F-Bit Mask Register - 3 (DS3 Applications)
  • TxDS3 F-Bit Mask Register - 3 (Address = 0x38)
    • 2.3.5.10 Transmit F-Bit Mask Register - 4 (DS3 Applications)
  • TxDS3 F-Bit Mask Register - 4 (Address = 0x39)
    • 2.3.6 Transmit E3 (ITU-T G.832) Configuration Registers
      • 2.3.6.1 Transmit E3 Configuration Register (E3, ITU-T G.832)
  • TxE3 Configuration Register (Address = 0x30)
    • 2.3.6.2 Transmit E3 LAPD Configuration Register (E3, ITU-T G.832)
  • TxE3 LAPD Configuration Register (Address = 0x33)
    • 2.3.6.3 Transmit E3 LAPD Status and Interrupt Register (E3, ITU-T G.832)
  • TxE3 LAPD Status and Interrupt Register (Address = 0x34)
    • 2.3.6.4 Transmit E3 GC Byte Register (E3, ITU- T G.832)
  • TxE3 GC Byte Register (Address = 0x35)
    • 2.3.6.5 Transmit E3 MA Byte Register (E3, ITU- T G.832)
  • TxE3 MA Byte Register (Address = 0x36)
    • 2.3.6.6 Transmit E3 NR Byte Register (E3, ITU- T G.832)
  • TxE3 NR Byte Register (Address = 0x37)
    • 2.3.6.7 Transmit E3 TTB-0 Register (E3, ITU-T G.832)
  • TxE3 TTB-0 Register (Address = 0x38)
    • 2.3.6.8 Transmit E3 TTB-1 Register (E3, ITU-T G.832)
  • TxE3 TTB-1 Register (Address = 0x39)
    • 2.3.6.9 Transmit E3 TTB-2 Register (E3, ITU-T G.832)
  • TxE3 TTB-2 Register (Address = 0x3A)
    • 2.3.6.10 Transmit E3 TTB-3 Register (E3, ITU-T G.832)
  • TxE3 TTB-3 Register (Address = 0x3B)
    • 2.3.6.11 Transmit E3 TTB-4 Register (E3, ITU-T G.832)
  • TxE3 TTB-4 Register (Address = 0x3C)
    • 2.3.6.12 Transmit E3 TTB-5 Register (E3, ITU-T G.832)
  • TxE3 TTB-5 Register (Address = 0x3D)
    • 2.3.6.13 Transmit E3 TTB-6 Register (E3, ITU-T G.832)
  • TxE3 TTB-6 Register (Address = 0x3E)
    • 2.3.6.14 Transmit E3 TTB-7 Register (E3, ITU-T G.832)
  • TxE3 TTB-7 Register (Address = 0x3F)
    • 2.3.6.15 Transmit E3 TTB-8 Register (E3, ITU-T G.832)
  • TxE3 TTB-8 Register (Address = 0x40)
    • 2.3.6.16 Transmit E3 TTB-9 Register (E3, ITU-T G.832)
  • TxE3 TTB-9 Register (Address = 0x41)
    • 2.3.6.17 Transmit E3 TTB-10 Register (E3, ITU-T G.832)
  • TxE3 TTB-10 Register (Address = 0x42)
    • 2.3.6.18 Transmit E3 TTB-11 Register (E3, ITU-T G.832)
  • TxE3 TTB-11 Register (Address = 0x43)
    • 2.3.6.19 3.3.2.77 Transmit E3 TTB-12 Register (E3, ITU-T G.832)
  • TxE3 TTB-12 Register (Address = 0x44)
    • 2.3.6.20 Transmit E3 TTB-13 Register (E3, ITU-T G.832)
  • TxE3 TTB-13 Register (Address = 0x45)
    • 2.3.6.21 Transmit E3 TTB-14 Register (E3, ITU-T G.832)
  • TxE3 TTB-14 Register (Address = 0x46)
    • 2.3.6.22 Transmit E3 TTB-15 Register (E3, ITU-T G.832)
  • TxE3 TTB-15 Register (Address = 0x47)
    • 2.3.6.23 Transmit E3 FA1 Byte Error Mask Register (E3, ITU-T G.832)
  • TxE3 FA1 Error Mask Register (Address = 0x48)
    • 2.3.6.24 Transmit E3 FA2 Byte Error Mask Register (E3, ITU-T G.832)
  • TxE3 FA2 Error Mask Register (Address = 0x49)
    • 2.3.6.25 Transmit E3 BIP-8 Error Mask Register (E3, ITU-T G.832)
  • TxE3 BIP-8 Error Mask Register (Address = 0x4A)
    • 2.3.7 Transmit E3 Framer Configuration Registers (ITU-T G.751)
      • 2.3.7.1 Transmit E3 Configuration Register (ITU-T G.751)
  • TxE3 Configuration Register (Address = 0x30)
    • 2.3.7.2 Transmit E3 LAPD Configuration Register (ITU-T G.751)
  • TxE3 LAPD Configuration Register (Address = 0x33)
    • 2.3.7.3 Transmit E3 LAPD Status and Interrupt Register (ITU-T G.751)
  • TxE3 LAPD Status and Interrupt Register (Address = 0x34)
    • 2.3.7.4 Transmit E3 Service Bits Register (ITU- T G.751)
  • TxE3 Service Bits Register (Address = 0x35)
    • 2.3.7.5 Transmit E3 FAS Mask Register - 0 (ITU-T G.751)
  • TxE3 FAS Error Mask Register - 0 (Address = 0x48)
    • 2.3.7.6 Transmit E3 FAS Error Mask Register - 1 (ITU-T G.751)
  • TxE3 FAS Error Mask Register - 1 (Address = 0x49)
    • 2.3.7.7 Transmit E3 BIP-4 Error Mask Register (ITU-T G.751)
  • TxE3 BIP-4 Error Mask Register (Address = 0x4A)
    • 2.3.8 Performance Monitor Registers
      • 2.3.8.1 PMON Line Code Violation Count Register - MSB
      • 2.3.8.2 PMON Line Code Violation Count Register - LSB
  • PMON LCV Event Count Register - LSB (Address = 0x51)
    • 2.3.8.3 PMON Framing Bit/Byte Error Count Register - MSB
  • PMON Framing Bit/Byte Error Count Register - MSB (Address = 0x52)
    • 2.3.8.4 PMON Framing Bit/Byte Error Count Register - LSB
  • PMON Framing Bit/Byte Error Count Register - LSB (Address = 0x53)
    • 2.3.8.5 PMON Parity Error Count Register - MSB
  • PMON Parity Error Count Register - MSB (Address = 0x54)
    • 2.3.8.6 PMON Parity Error Count Register - LSB
  • PMON Parity Error Count Register - LSB (Address = 0x55)
    • 2.3.8.7 PMON FEBE Event Count Register - MSB
  • PMON FEBE Event Count Register - MSB (Address = 0x56)
    • 2.3.8.8 PMON FEBE Event Count Register - LSB
  • PMON FEBE Event Count Register - LSB (Address = 0x57)
    • 2.3.8.9 PMON CP-Bit Error Event Count Register - MSB
  • PMON CP-Bit Error Count Register - MSB (Address = 0x58)
    • 2.3.8.10 PMON CP-Bit Error Event Count Register - LSB
  • PMON CP-Bit Error Count Register - LSB (Address = 0x59)
    • 2.3.8.11 PMON Holding Register
  • PMON Holding Register (Address = 0x6C)
    • 2.3.8.12 One-Second Error Status Register
  • One-Second Error Status Register (Address = 0x6D)
    • 2.3.8.13 One-Second Line Code Violation Accumulator Register - MSB
  • LCV - One-Second Accumulator Register - MSB (Address = 0x6E)
    • 2.3.8.14 One-Second Line Code Violation Accumulator Register - LSB
  • LCV - One-Second Accumulator Register - LSB (Address = 0x6F)
    • 2.3.8.15 One-Second Frame Parity Error Accumulator Register - MSB
  • Frame Parity Errors - One-Second Accumulator Register - MSB (Address = 0x70)
    • 2.3.8.16 One-Second Frame Parity Error Accumulator Register - LSB
  • Frame Parity Errors - One-Second Accumulator Register - LSB (Address = 0x71)
    • 2.3.8.17 One-Second Frame CP-Bit Error Accumulator Register - MSB
  • Frame CP-Bit Errors - One-Second Accumulator Register - MSB (Address = 0x72)
    • 2.3.8.18 One-Second Frame CP-Bit Error Accumulator Register - LSB
  • Frame Parity Errors - One-Second Accumulator Register - LSB (Address = 0x73)
    • 2.3.8.19 Line Interface Drive Register
  • Line Interface Drive Register (Address = 0x80)
    • 2.3.8.20 Line Interface Scan Register
  • Line Interface Scan Register (Address = 0x81)
    • 2.4 The Loss of Clock Enable Feature
  • Address = 0x01, Framer I/O Control Register
    • 2.5 Using the PMON Holding Register
    • 2.6 The Interrupt Structure within the Framer Microprocessor Interface Section
      • Table 5: List of all of the Possible Conditions that can Generate Interrupts within the XRT7250 F...
      • Table 6: A Listing of the XRT7250 Framer Device Interrupt Block Registers (for DS3 Applications)
      • Table 7: A Listing of the XRT7250 Framer Device Interrupt Block Registers (for E3, ITU-T G.832 Ap...
      • Table 8: A Listing of the XRT7250 Framer Device Interrupt Block Register (for E3, ITU-T G.751 App...
  • Block Interrupt Status Register (Address = 0x05)
  • Block Interrupt Enable Register (Address = 0x04)
    • Table 9: Interrupt Service Routine Guide (for DS3 Applications)
    • Table 10: Interrupt Service Routine Guide (for E3, ITU-T G.832 Applications)
    • Table 11: Interrupt Service Routine Guide (for E3, ITU-T G.751 Applications)
      • 2.6.1 Automatic Reset of Interrupt Enable Bits
  • framer operating mode Register (Address = 0x00)
    • 2.6.2 One-Second Interrupts
    • 2.7 Interfacing the framer to an intel-type microprocessor
      • Table 12: Alternate Functions of Port 3 Pins
      • Table 13: Interrupt Service Routine Location (in Code Memory) for the INT0* and INT1* Interrupt I...
      • Figure 37. Schematic depicting how to interface the XRT7250 DS3/E3 Framer IC to the 8051 Microcon...
    • 2.8 Interfacing the Framer IC to a Motorola- type Microprocessor
      • Figure 38. Schematic Depicting how to interface the XRT7250 DS3/E3 Framer IC to the MC68000 Micro...
      • Table 14: Auto-Vector Table for the MC68000 Microprocessor
  • 3.0 The Line Interface and scan section
    • Figure 39. Schematic Depicting how to interface the XRT7250 DS3/E3 Framer IC to the XRT7300 DS3/ ...
    • 3.1 Bit-Fields within the Line Interface Drive Register
  • LINE INTERFACE DRIVE Register (Address = 0x80)
    • Table 15: The Relationship between the states of RLOOP, LLOOP and the resulting loop-back mode wi...
    • 3.2 Bit-Fields within the Line Interface Scan Register
  • LINE INTERFACE sCAN Register (Address = 0x81)
• XRT7250 Configuration
  • 4.0 DS3 Operation of the XRT7250
  • Framer Operating Mode Register (Address = 0x00)
    • 4.1 Description of the DS3 Frames and Associated Overhead Bits
      • Figure 40. DS3 Frame Format for C-bit Parity
      • Figure 41. DS3 Frame Format for M13
  • Framer Operating Mode Register (Address = 0x00)
    • Table 16: The Relationship between the content of Bit 2, (C-Bit Parity*/M13) within the Framer Op...
    • Table 17: C-bit Functions for the C-bit Parity DS3 Frame Format
      • 4.1.1 Frame Synchronization Bits (Applies to both M13 and C-bit Parity Framing Formats)
      • 4.1.2 Performance Monitoring/Error Detection Bits (Parity)
      • 4.1.3 Alarm and Signaling-Related Overhead Bits
      • 4.1.4 The Data Link Related Overhead Bits
    • 4.2 The Transmit Section of the XRT7250 (DS3 Mode Operation)
      • Figure 42. A Simple Illustration of the Transmit Section, within the XRT7250, when it has been co...
        • 4.2.1 The Transmit Payload Data Input Interface Block
      • Figure 43. A Simple Illustration of the Transmit Payload Data Input Interface Block
      • Table 18: Listing and Description of the pins associated with the Transmit Payload Data Input Int...
        • 4.2.1.1 Mode 1 - The Serial/Loop-Timing Mode
      • Figure 44. Illustration of the Terminal Equipment being interfaced to the Transmit Payload Data I...
      • Figure 45. Behavior of the Terminal Interface signals between the Transmit Payload Data Input Int...
  • Framer Operating Mode Register (Address = 0x00)
    • 4.2.1.2 Mode 2 - The Serial/Local-Timed/ Frame-Slave Mode Behavior of the XRT7250
    • Figure 46. Illustration of the Terminal Equipment being interfaced to the Transmit Payload Data I...
    • Figure 47. Behavior of the Terminal Interface signals between the XRT7250 and the Terminal Equipm...
  • Framer Operating Mode Register (Address = 0x00)
    • 4.2.1.3 Mode 3 - The Serial/Local-Timed/ Frame-Master Mode Behavior of the XRT7250
    • Figure 48. Illustration of the Terminal Equipment being interfaced to the Transmit Payload Data I...
    • Figure 49. Behavior of the Terminal Interface signals between the XRT7250 and the Terminal Equipm...
  • Framer Operating Mode Register (Address = 0x00)
    • 4.2.1.4 Mode 4 - The Nibble-Parallel/Loop- Timed Mode Behavior of the XRT7250
    • Figure 50. Illustration of the Terminal Equipment being interfaced to the Transmit Payload Data I...
    • Figure 51. Behavior of the Terminal Interface signals between the XRT7250 and the Terminal Equipm...
  • Framer Operating Mode Register (Address = 0x00)
    • 4.2.1.5 Mode 5 - The Nibble-Parallel/Local- Timed/Frame-Slave Interface Mode Behavior of the XRT7250
    • Figure 52. Illustration of the Terminal Equipment being interfaced to the Transmit Payload Data I...
    • Figure 53. Behavior of the Terminal Interface signals between the XRT7250 and the Terminal Equipm...
  • Framer Operating Mode Register (Address = 0x00)
    • 4.2.1.6 Mode 6 - The Nibble-Parallel/TxInClk/ Frame-Master Interface Mode Behavior of the XRT7250
    • Figure 54. Illustration of the Terminal Equipment being interfaced to the Transmit Payload Data I...
    • Figure 55. Behavior of the Terminal Interface signals between the XRT7250 and the Terminal Equipm...
  • Framer Operating Mode Register (Address = 0x00)
    • 4.2.2 The Transmit Overhead Data Input Interface
    • Figure 56. Simple Illustration of the Transmit Overhead Data Input Interface block
    • Table 19: A Listing of the Overhead bits within the DS3 frame, and their potential sources, withi...
      • 4.2.2.1 4.2.2.1 Method 1 - Using the TxOHClk Clock Signal
    • Table 20: Description of Method 1 Transmit Overhead Input Interface Signals
    • Figure 57. Illustration of the Terminal Equipment being interfaced to the Transmit Overhead Data ...
    • Table 21: The Relationship between the Number of Rising Clock Edges in TxOHClk, (since TxOHFrame ...
    • Figure 58. Illustration of the signal that must occur between the Terminal Equipment and the XRT7...
      • 4.2.2.2 Method 2 - Using the TxInClk and TxOHEnable Signals
    • Table 22: Description of Method 2 Transmit Overhead Input Interface Signals
    • Figure 59. Illustration of the Terminal Equipment being interfaced to the Transmit Overhead Data ...
    • Table 23: The Relationship between the Number of TxOHEnable pulses (since the last occurrence of ...
    • Figure 60. Behavior of Transmit Overhead Data Input Interface signals between the XRT7250 and the...
      • 4.2.3 The Transmit DS3 HDLC Controller
        • 4.2.3.1 Bit-Oriented Signaling (or FEAC Message) processing via the Transmit DS3 HDLC Controller.
  • Tx DS3 FEAC Register (Address = 0x32)
  • Transmit DS3 FEAC Configuration and Status Register (Address = 0x31)
  • Transmit DS3 FEAC Configuration and Status Register (Address = 0x31)
    • Figure 61. A Flow Chart depicting how to transmit a FEAC Message via the FEAC Transmitter
      • 4.2.3.2 Message-Oriented Signaling (e.g., LAP-D) processing via the Transmit DS3 HDLC Controller
    • Figure 62. LAPD Message Frame Format
    • Table 24: The LAPD Message Type and the Corresponding value of the First Byte, within the Informa...
  • Transmit DS3 LAPD Configuration Register (Address = 0x33)
    • Table 25: Relationship between TxLAPD Msg Length and the LAPD Message Size
  • Transmit DS3 LAPD Configuration Register (Address = 0x33)
    • Table 26: Relationship between TxLAPD Msg Length and the LAPD Message Size
  • Transmit DS3 LAPD Status/Interrupt Register (Address = 0x34)
    • Figure 63. Flow Chart depict how to use the LAPD Transmitter
  • Framer Operating Mode Register (Address = 0x00)
  • Block Interrupt Enable Register (Address = 0x04)
    • 4.2.4 The Transmit DS3 Framer Block
      • 4.2.4.1 Brief Description of the Transmit DS3 Framer
      • 4.2.4.2 Detailed Functional Description of the Transmit DS3 Framer Block
    • Figure 64. A Simple Illustration of the Transmit DS3 Framer Block and the associated paths to oth...
  • Tx DS3 Configuration Register (Address = 0x30)
    • Table 27: The Relationship between the contents of Bit 7 (Tx Yellow Alarm) within the Tx DS3 Conf...
    • Table 28: The Relationship between the contents of Bit 6 (Tx X-Bits) within the Tx DS3 Configurat...
    • Table 29: The Relationship between the contents of Bit 5 (Tx Idle) within the Tx DS3 Configuratio...
    • Table 30: The Relationship between the contents of Bit 4 (Tx AIS Pattern) within the Tx DS3 Confi...
    • Table 31: The Relationship between the contents of Bit 3 (Tx LOS) within the Tx DS3 Configuration...
  • Tx DS3 M-Bit Mask Register, Address = 0x35
  • Tx DS3 F-Bit Mask1 Register, Address = 0x36
  • Tx DS3 F-Bit Mask2 Register, Address = 0x37
  • Tx DS3 F-Bit Mask3 Register, Address = 0x38
  • Tx DS3 F-Bit Mask4 Register, Address = 0x39
    • 4.2.5 The Transmit DS3 Line Interface Block
    • Figure 65. Approach to Interfacing the XRT7250 Framer IC to the XRT7300 DS3/E3/STS-1 Transmitter LIU
    • Figure 66. A Simple Illustration of the Transmit DS3 LIU Interface block
    • Figure 67. The Behavior of TxPOS and TxNEG signals during data transmission while the Transmit DS...
      • 4.2.5.1 Selecting the various Line Codes
  • I/O Control Register (Address = 0x01)
    • Table 32: The Relationship between the content of Bit 3 (Unipolar/Bipolar*) within the UNI I/O Co...
    • Figure 68. Illustration of AMI Line Code
    • Figure 69. Illustration of two examples of B3ZS Encoding
  • I/O Control Register (Address = 0x01)
    • Table 33: The Relationship between Bit 4 (AMI/B3ZS*) within the I/O Control Register and the Bipo...
      • 4.2.5.2 TxLineClk Clock Edge Selection
  • II/O Control Register (Address = 0x01)
    • Table 34: The Relationship between the contents of Bit 2 (TxLineClk Inv) within the I/O Control R...
    • Figure 70. Waveform/Timing Relationship between TxLineClk, TxPOS and TxNEG - TxPOS and TxNEG are ...
    • Figure 71. Waveform/Timing Relationship between TxLineClk, TxPOS and TxNEG - TxPOS and TxNEG are ...
      • 4.2.6 Transmit Section Interrupt Processing
        • 4.2.6.1 Enabling Transmit Section Interrupts
  • Block Interrupt Enable Register (Address = 0x04)
  • Transmit DS3 FEAC Configuration & Status Register (Address = 0x31)
  • Transmit DS3 FEAC Configuration & Status Register (Address = 0x31)
  • TxDS3 LAPD Status and Interrupt Register (Address = 0x34)
  • TxDS3 LAPD Status and Interrupt Register (Address = 0x34)
    • 4.3 The Receive Section of the XRT7250 (DS3 Mode Operation)
      • Figure 72. A Simple Illustration of the Receive Section of the XRT7250, when it has been configur...
        • 4.3.1 The Receive DS3 LIU Interface Block
      • Figure 73. A Simple Illustration of the Receive DS3 LIU Interface Block
        • 4.3.1.1 Unipolar Decoding
      • Figure 74. Behavior of the RxPOS, RxNEG and RxLineClk signals during data reception of Unipolar Data
  • II/O Control Register (Address = 0x01)
    • Table 35: The Relationship between the contents of Bit 2 (TxLineClk Inv) within the I/O Control R...
      • 4.3.1.2 Bipolar Decoding
    • Figure 75. Illustration on how the Receive DS3 Framer (within the XRT7250 Framer IC) being interf...
    • Figure 76. Illustration of AMI Line Code
    • Figure 77. Illustration of two examples of B3ZS Decoding
  • II/O Control Register (Address = 0x01)
    • Table 36: The Relationship between the contents of Bit 1 (RxLineClk Inv) of the I/O Control Regis...
    • Figure 78. Waveform/Timing Relationship between RxLineClk, RxPOS and RxNEG - When RxPOS and RxNEG...
    • Figure 79. Waveform/Timing Relationship between RxLineClk, RxPOS and RxNEG - When RxPOS and RxNEG...
      • 4.3.2 The Receive DS3 Framer Block
    • Figure 80. A Simple Illustration of the Receive DS3 Framer Block and the Associated Paths to the ...
    • Figure 81. The State Machine Diagram for the Receive DS3 Framer block's Frame Acquisition/Mainten...
      • 4.3.2.1 Frame Acquisition Mode Operation
  • Rx DS3 Configuration and Status Register, (Address = 0x10)
    • Table 37: The Relationship between the contents of Bit 2 (Framing on Parity) within the Rx DS3 Co...
      • 4.3.2.2 Frame Maintenance Mode Operation
  • Rx DS3 Configuration and Status Register, (Address = 0x10)
    • Table 38: The Relationship between the contents of Bit 1 (F-Sync Algo) within the Rx DS3 Configur...
  • Rx DS3 Configuration and Status Register, (Address = 0x10)
    • Table 39: The Relationship between the contents of Bit 0 (M-Sync Algo) within the Rx DS3 Configur...
  • Rx DS3 Configuration and Status Register, (Address = 0x10)
    • 4.3.2.3 Forcing a Reframe via Software Command
  • I/O Control Register (Address = 0x01)
    • 4.3.2.4 Performance Monitoring of the Receive DS3 Framer block
  • PMON Framing Bit Error Event Count Register - MSB (Address = 0x52)
  • PMON Framing Bit Error Event Count Register - LSB (Address = 0x53)
    • 4.3.2.5 DS3 Receive Alarms
  • Rx DS3 Configuration and Status Register, (Address = 0x10)
  • Rx DS3 Configuration and Status Register, (Address = 0x10)
  • Rx DS3 Configuration and Status Register, (Address = 0x10)
  • Rx DS3 Configuration and Status Register, (Address = 0x10)
  • Rx DS3 Configuration and Status Register, (Address = 0x10)
  • Rx DS3 Status Register (Address = 0x11)
  • Rx DS3 Interrupt Status Register (Address = 0x13)
  • RxDS3 Status Register (Address = 0x11)
  • RxDS3 Interrupt Status Register (Address = 0x13)
    • 4.3.2.6 Performance Monitoring of the DS3 Transport Medium
  • PMON Parity Error Event Count Register - MSB (Address = 0x54)
  • PMON Parity Error Event Count Register - LSB (Address = 0x55)
    • Figure 82. A Simple Illustration of the Locations of the Source, Mid-Network and Sink Terminal Eq...
    • Figure 83. Illustration of the Presumed Configuration of the Mid-Network Terminal Equipment
      • 4.3.3 The Receive HDLC Controller Block
        • 4.3.3.1 Bit-Oriented Signaling (or FEAC) Processing via the Receive DS3 HDLC Controller.
  • Rx DS3 FEAC Interrupt Enable/Status Register (Address = 0x17)
  • Rx DS3 FEAC Register (Address = 0x16)
  • Rx DS3 FEAC Interrupt Enable/Status Register (Address = 0x17)
    • Figure 84. Flow Diagram depicting how the Receive FEAC Processor Functions
      • 4.3.3.2 The Message Oriented Signaling (e.g., LAP-D) Processing via the Receive DS3 HDLC Controll...
    • Figure 85. LAPD Message Frame Format
  • Rx DS3 LAPD Control Register (Address = 0x18)
  • Rx DS3 LAPD Status Register (Address = 0x19)
    • Table 40: The Relationship between RxLAPDType[1:0] and the resulting LAPD Message type and size
    • Figure 86. Flow Chart depicting the Functionality of the LAPD Receiver
      • 4.3.4 The Receive Overhead Data Output Interface
    • Figure 87. A Simple Illustration of the Receive Overhead Output Interface block
      • 4.3.4.1 Method 1 - Using the RxOHClk Clock signal
    • Table 41: Listing and Description of the Pin Associated with the Receive Overhead Data Output Int...
    • Figure 88. Illustration of how to interface the Terminal Equipment to the Receive Overhead Data O...
    • Table 42: The Relationship between the Number of Rising Clock Edges in RxOHClk, (since RxOHFrame ...
    • Figure 89. Illustration of the signals that are output via the Receive Overhead Output Interface ...
    • Table 43: Listing and Description of the Pin Associated with the Receive Overhead Data Output Int...
    • Figure 90. Illustration of how to interface the Terminal Equipment to the Receive Overhead Data O...
    • Table 44: The Relationship between the Number of RxOHEnable output pulses ((since RxOHFrame was l...
    • Figure 91. Illustration of the signals that are output via the Receive Overhead Data Output Inter...
      • 4.3.5 The Receive Payload Data Output Interface
    • Figure 92. A Simple illustration of the Receive Payload Data Output Interface block
    • Table 45: Listing and Description of the pin associated with the Receive Payload Data Output Inte...
      • 4.3.5.1 Serial Mode Operation
    • Figure 93. Illustration of the XRT7250 DS3/E3 Framer IC being interfaced to the Receive Terminal ...
    • Figure 94. An Illustration of the behavior of the signals between the Receive Payload Data Output...
      • 4.3.5.2 Nibble-Parallel Mode Operation
    • Figure 95. Illustration of the XRT7250 DS3/E3 Framer IC being interfaced to the Receive Section o...
    • Figure 96. An Illustration of the Behavior of the signals between the Receive Payload Data Output...
      • 4.3.6 Receive Section Interrupt Processing
        • 4.3.6.1 Enabling Receive Section Interrupts
  • Block Interrupt Enable Register (Address = 0x04)
    • 4.3.6.2 Enabling/Disabling and Servicing Receive Section Interrupts
  • RxDS3 Interrupt Enable Register (Address = 0x12)
  • RxDS3 Interrupt Status Register (Address = 0x13)
  • RxDS3 Configuration & Status Register (Address = 0x10)
  • RxDS3 Interrupt Enable Register (Address = 0x12)
  • RxDS3 Interrupt Status Register (Address = 0x13)
  • RxDS3 Configuration & Status Register (Address = 0x10)
  • RxDS3 Interrupt Enable Register (Address = 0x12)
  • RxDS3 Interrupt Status Register (Address = 0x13)
  • RxDS3 Configuration & Status Register (Address = 0x10)
  • RxDS3 Interrupt Enable Register (Address = 0x12)
  • RxDS3 Interrupt Status Register (Address = 0x13)
  • RxDS3 Configuration & Status Register (Address = 0x10)
  • RxDS3 Interrupt Enable Register (Address = 0x12)
  • RxDS3 Interrupt Status Register (Address = 0x13)
  • RxDS3 Status Register (Address = 0x11)
  • RxDS3 Interrupt Enable Register (Address = 0x12)
  • RxDS3 Interrupt Status Register (Address = 0x13)
  • RxDS3 Interrupt Enable Register (Address = 0x12)
  • RxDS3 Interrupt Status Register (Address = 0x13)
  • RxDS3 Interrupt Enable Register (Address = 0x12)
  • RxDS3 Interrupt Status Register (Address = 0x13)
  • RxDS3 FEAC Interrupt Enable/Status Register (Address = 0x17)
  • RxDS3 FEAC Interrupt Enable/Status Register (Address = 0x17)
  • RxDS3 FEAC Interrupt Enable/Status Register (Address = 0x17)
  • RxDS3 FEAC Interrupt Enable/Status Register (Address = 0x17)
  • RxDS3 LAPD Control Register (Address = 0x18)
  • RxDS3 LAPD Control Register (Address = 0x18)
  • 5.0 E3/ITU-T G.751 Operation of the XRT7250
  • Framer Operating Mode Register (Address = 0x00)
    • 5.1 Description of the E3, ITU-T G.751 Frames and Associated Overhead Bits
      • Figure 97. Illustration of the E3, ITU-T G.751 Framing Format.
        • 5.1.1 Definition of the Overhead Bits
          • 5.1.1.1 The �A� (Alarm) Bit
          • 5.1.1.2 The �N� Bit
    • 5.2 The Transmit Section of the XRT7250 (E3, ITU-T G.751 Mode Operation)
      • Figure 98. A Simple Illustration of the XRT7250 Transmit Section when it has been configured to o...
        • 5.2.1 The Transmit Payload Data Input Interface Block
      • Figure 99. A Simple Illustration of the Transmit Payload Data Input Interface Block
      • Table 46: Listing and Description of the pins associated with the Transmit Payload Data Input Int...
        • 5.2.1.1 Mode 1 - The Serial/Loop-Timing Mode The Behavior of the XRT7250
      • Figure 100. Illustration of the Terminal Equipment being interfaced to the Transmit Payload Data ...
  • TxE3 Configuration Register (Address = 0x30)
    • Figure 101. Behavior of the Terminal Interface signals between the XRT7250 Transmit Payload Data ...
  • Framer Operating Mode Register (Address = 0x00)
    • 5.2.1.2 Mode 2 - The Serial/Local-Timed/ Frame-Slave Mode Behavior of the XRT7250
    • Figure 102. Illustration of the Terminal Equipment being interfaced to the Transmit Payload Data ...
    • Figure 103. Behavior of the Terminal Interface signals between the XRT7250 and the Terminal Equip...
  • Framer Operating Mode Register (Address = 0x00)
    • 5.2.1.3 Mode 3 - The Serial/Local-Timed/ Frame-Master Mode Behavior of the XRT7250
    • Figure 104. Illustration of the Terminal Equipment being interfaced to the Transmit Payload Data ...
    • Figure 105. Behavior of the Terminal Interface signals between the XRT7250 and the Terminal Equip...
  • Framer Operating Mode Register (Address = 0x00)
    • 5.2.1.4 Mode 4 - The Nibble-Parallel/Loop- Timed Mode Behavior of the XRT7250
    • Figure 106. Illustration of the Terminal Equipment being interfaced to the Transmit Payload Data ...
    • Figure 107. Behavior of the Terminal Interface signals between the XRT7250 and the Terminal Equip...
  • Framer Operating Mode Register (Address = 0x00)
    • 5.2.1.5 Mode 5 - The Nibble-Parallel/Local- Timed/Frame-Slave Interface Mode Behavior of the XRT7250
    • Figure 108. Illustration of the Terminal Equipment being interfaced to the Transmit Payload Data ...
    • Figure 109. Behavior of the Terminal Interface signals between the XRT7250 and the Terminal Equip...
  • Framer Operating Mode Register (Address = 0x00)
    • 5.2.1.6 4.2.1.6 Mode 6 - The Nibble-Parallel/ Local-Timed/Frame-Master Interface Mode Behavior of...
    • Figure 110. Illustration of the Terminal Equipment being interfaced to the Transmit Payload Data ...
    • Figure 111. Behavior of the Terminal Interface signals between the XRT7250 and the Terminal Equip...
  • Framer Operating Mode Register (Address = 0x00)
    • 5.2.2 The Transmit Overhead Data Input Interface
    • Figure 112. Simple Illustration of the Transmit Overhead Data Input Interface block
    • Table 47: A Listing of the Overhead bits within the E3 frame, and their potential sources, within...
      • 5.2.2.1 Method 1 - Using the TxOHClk Clock Signal
    • Table 48: Description of Method 1 Transmit Overhead Input Interface Signals
    • Figure 113. Illustration of the Terminal Equipment being interfaced to the Transmit Overhead Data...
    • Table 49: The Relationship between the Number of Rising Clock Edges in TxOHClk, (since TxOHFrame ...
    • Figure 114. Illustration of the signal that must occur between the Terminal Equipment and the XRT...
      • 5.2.2.2 Method 2 - Using the TxInClk and TxOHEnable Signals
    • Table 50: Description of Method 2 Transmit Overhead Input Interface Signals
    • Figure 115. Illustration of the Terminal Equipment being interfaced to the Transmit Overhead Data...
    • Table 51: The Relationship between the Number of TxOHEnable pulses (since the last occurrence of ...
    • Figure 116. Behavior of Transmit Overhead Data Input Interface signals between the XRT7250 and th...
      • 5.2.3 The Transmit E3 HDLC Controller
        • 5.2.3.1 Message-Oriented Signaling (e.g., LAP-D) processing via the Transmit DS3 HDLC Controller
    • Figure 117. LAPD Message Frame Format
    • Table 52: The LAPD Message Type and the Corresponding value of the First Byte, within the Informa...
  • TxE3 Configuration Register (Address = 0x30)
  • Transmit E3 LAPD Configuration Register (Address = 0x33)
    • Table 53: Relationship between TxLAPD Msg Length and the LAPD Message Size
  • TxE3 LAPD Configuration Register (Address = 0x33)
  • Transmit E3 LAPD Configuration Register (Address = 0x33)
  • TxE3 LAPD Status and Interrupt Register (Address = 0x34)
  • TxE3 LAPD Status and Interrupt Register (Address = 0x34)
    • Figure 118. Flow Chart Depicting how to use the LAPD Transmitter
  • Block Interrupt Enable Register (Address = 0x04)
    • 5.2.4 The Transmit E3 Framer Block
      • 5.2.4.1 Brief Description of the Transmit E3 Framer
      • 5.2.4.2 Detailed Functional Description of the Transmit E3 Framer Block
    • Figure 119. A Simple Illustration of the Transmit E3 Framer Block and the associated paths to oth...
  • TxE3 Configuration Register (Address = 0x30)
    • Table 54: The Relationship between the contents of Bit 2 (Tx AIS Enable) within the Tx E3 Configu...
    • Table 55: The Relationship between the contents of Bit 1 (Tx LOS) within the Tx E3 Configuration ...
  • TxE3 Configuration Register (Address = 0x30)
  • TxE3 Service Bits Register (Address = 0x35)
  • TxE3 Configuration Register (Address = 0x30)
  • TxE3 Configuration Register (Address = 0x30)
  • TxE3 FAS Error Mask Register - 0 (Address = 0x48)
  • TxE3 FAS Error Mask Register - 1 (Address = 0x49)
  • TxE3 BIP-4 Error Mask Register (Address = 0x4A)
    • 5.2.5 The Transmit E3 Line Interface Block
    • Figure 120. Approach to Interfacing the XRT7250 Framer IC device to the XRT7300 DS3/E3/STS-1 LIU
    • Figure 121. A Simple Illustration of the Transmit E3 LIU Interface block
    • Figure 122. The Behavior of TxPOS and TxNEG signals during data transmission while the Transmit D...
      • 5.2.5.1 Selecting the various Line Codes
  • I/O Control Register (Address = 0x01)
    • Table 56: The Relationship between the content of Bit 3 (Unipolar/Bipolar*) within the UNI I/O Co...
    • Figure 123. Illustration of AMI Line Code
    • Figure 124. Illustration of two examples of HDB3 Encoding
  • I/O Control Register (Address = 0x01)
    • Table 57: The Relationship between Bit 4 (AMI/ HDB3*) within the I/O Control Register and the Bip...
      • 5.2.5.2 TxLineClk Clock Edge Selection
  • II/O Control Register (Address = 0x01)
    • Table 58: The Relationship between the contents of Bit 2 (TxLineClk Inv) within the I/O Control R...
    • Figure 125. Waveform/Timing Relationship between TxLineClk, TxPOS and TxNEG - TxPOS and TxNEG are...
    • Figure 126. Waveform/Timing Relationship between TxLineClk, TxPOS and TxNEG - TxPOS and TxNEG are...
      • 5.2.6 Transmit Section Interrupt Processing
        • 5.2.6.1 Enabling Transmit Section Interrupts
  • Block Interrupt Enable Register (Address = 0x04)
  • TxE3 LAPD Status and Interrupt Register (Address = 0x34)
  • TxE3 LAPD Status and Interrupt Register (Address = 0x34)
    • 5.3 The Receive Section of the XRT7250 (E3 Mode Operation)
      • Figure 127. A Simple Illustration of the Receive Section of the XRT7250 configured to operate in ...
        • 5.3.1 The Receive E3 LIU Interface Block
      • Figure 128. A Simple Illustration of the Receive E3 LIU Interface Block
        • 5.3.1.1 Unipolar Decoding
      • Figure 129. Behavior of the RxPOS, RxNEG and RxLineClk signals during data reception of Unipolar ...
  • II/O Control Register (Address = 0x01)
    • Table 59: The Relationship between the contents of Bit 2 (TxLineClk Inv) within the I/O Control R...
      • 5.3.1.2 Bipolar Decoding
    • Figure 130. Illustration on how the Receive E3 Framer (within the XRT7250 Framer IC) being interf...
    • Figure 131. Illustration of AMI Line Code
    • Figure 132. Illustration of two examples of HDB3 Decoding
  • II/O Control Register (Address = 0x01)
    • Table 60: The Relationship between the contents of Bit 1 (RxLineClk Inv) of the I/O Control Regis...
    • Figure 133. Waveform/Timing Relationship between RxLineClk, RxPOS and RxNEG - When RxPOS and RxNE...
    • Figure 134. Waveform/Timing Relationship between RxLineClk, RxPOS and RxNEG - When RxPOS and RxNE...
      • 5.3.2 The Receive E3 Framer Block
    • Figure 135. A Simple Illustration of the Receive E3 Framer Block and the Associated Paths to the ...
      • 5.3.2.1 The Framing Acquisition Mode
    • Figure 136. The State Machine Diagram for the Receive E3 Framer E3 Frame Acquisition/Maintenance ...
    • Figure 137. Illustration of the E3, ITU-T G.751 Framing Format
  • RxE3 Interrupt Status Register - 1 (Address = 0x14)
  • RxE3 Configuration & Status Register - 2 (Address = 0x11)
  • RxE3 Interrupt Status Register - 1 (Address = 0x14)
    • 5.3.2.2 The Framing Maintenance Mode
  • RxE3 Interrupt Status Register - 1 (Address = 0x14)
  • RxE3 Configuration & Status Register - 2 (Address = 0x11)
  • PMON Framing Bit/Byte Error Count Register - MSB (Address = 0x52)
  • PMON Framing Bit/Byte Error Count Register - LSB (Address = 0x53)
    • 5.3.2.3 Forcing a Reframe via Software Command
  • RxE3 Configuration & Status Register - 2 (Address = 0x11)
    • 5.3.2.4 Performance Monitoring of the Frame Synchronization Section, within the Receive E3 Framer...
    • 5.3.2.5 The RxOOF and RxLOF output pin.
    • Table 61: The Relationship between the Logic State of the RxOOF and RxLOF output pins, and the Fr...
      • 5.3.2.6 E3 Receive Alarms
      • 5.3.2.7 The Loss of Signal (LOS) Alarm
  • RxE3 Configuration & Status Register - 2 (Address = 0x11)
  • RxE3 Interrupt Status Register - 1 (Address = 0x14)
  • RxE3 Configuration & Status Register - 2 (Address = 0x11)
    • 5.3.2.8 The AIS (Alarm Indication Status) Condition
  • RxE3 Interrupt Status Register - 1 (Address = 0x14)
  • RxE3 Configuration & Status Register - 2 (Address = 0x11)
  • RxE3 Configuration & Status Register - 2 (Address = 0x11)
    • 5.3.2.9 The Far-End-Receive Failure (FERF) Condition
  • RxE3 Configuration & Status Register - 1 G.751 (Address = 0x10)
  • RxE3 Interrupt Status Register - 2 (Address = 0x15)
  • RxE3 Configuration & Status Register - 2 (Address = 0x11)
  • RxE3 Configuration & Status Register - 2 (Address = 0x11)
    • 5.3.2.10 Error Checking of the Incoming E3 Frames
    • Figure 138. Illustration of the Local Receive E3 Framer block, receiving an E3 Frame (from the Re...
    • Figure 139. Illustration of the Local Receive E3 Framer block, transmitting an E3 Frame (to the R...
    • Figure 140. Illustration of the Local Receive E3 Framer block, receiving an E3 Frame (from the Re...
    • Figure 141. Illustration of the Local Receive E3 Framer block, transmitting an E3 Frame (to the R...
  • RxE3 Interrupt Status Register - 2 (Address = 0x15)
  • PMON Parity Error Count Register - MSB (Address = 0x54)
  • PMON Parity Error Count Register - LSB (Address = 0x55)
  • TxE3 Configuration Register (Address = 0x30)
  • RxE3 Interrupt Enable Register - 2 (Address = 0x13)
    • 5.3.3 The Receive HDLC Controller Block
    • Figure 142. LAPD Message Frame Format
  • RxE3 LAPD Control Register (Address = 0x18
  • RxE3 LAPD Status Register (Address = 0x19)
  • RxE3 LAPD Status Register (Address = 0x19)
  • RxE3 LAPD Status Register (Address = 0x19)
  • RxE3 LAPD Status Register (Address = 0x19)
  • RxE3 LAPD Status Register (Address = 0x19)
    • Table 62: The Relationship between the Contents of RxLAPDType[1:0] bit-fields and the PMDL Messag...
  • RxE3 LAPD Control Register (Address = 0x18
  • RxE3 LAPD Status Register (Address = 0x19)
    • Figure 143. Flow Chart depicting the Functionality of the LAPD Receiver
      • 5.3.4 The Receive Overhead Data Output Interface
    • Figure 144. A Simple Illustration of the Receive Overhead Output Interface block
      • 5.3.4.1 Method 1 - Using the RxOHClk Clock signal
    • Figure 145. Illustration of how to interface the Terminal Equipment to the Receive Overhead Data ...
    • Table 63: Listing and Description of the Pin Associated with the Receive Overhead Data Output Int...
    • Table 64: The Relationship between the Number of Rising Clock Edges in RxOHClk, (since RxOHFrame ...
    • Figure 146. Illustration of the signals that are output via the Receive Overhead Output Interface...
    • Table 65: Listing and Description of the Pin Associated with the Receive Overhead Data Output Int...
    • Figure 147. Illustration of how to interface the Terminal Equipment to the Receive Overhead Data ...
    • Table 66: The Relationship between the Number of RxOHEnable output pulses (since RxOHFrame was la...
    • Figure 148. Illustration of the signals that are output via the Receive Overhead Data Output Inte...
      • 5.3.5 The Receive Payload Data Output Interface
    • Figure 149. A Simple illustration of the Receive Payload Data Output Interface block
    • Table 67: Listing and Description of the pin associated with the Receive Payload Data Output Inte...
      • 5.3.5.1 Serial Mode Operation Behavior of the XRT7250
    • Figure 150. Illustration of the Terminal Equipment being interfaced to the Receive Payload Data I...
    • Figure 151. An Illustration of the behavior of the signals between the Receive Payload Data Outpu...
      • 5.3.5.2 Nibble-Parallel Mode Operation Behavior of the XRT7250
    • Figure 152. Illustration of the XRT7250 DS3/E3 Framer IC being interfaced to the Receive Section ...
    • Figure 153. Illustration of the signals that are output via the Receive Payload Data Output Inter...
      • 5.3.6 Receive Section Interrupt Processing
        • 5.3.6.1 Enabling Receive Section Interrupts
  • Block Interrupt Enable Register (Address = 0x04)
    • 5.3.6.2 Enabling/Disabling and Servicing Interrupts
  • RxE3 Interrupt Enable Register - 1 (Address = 0x12)
  • RxE3 Interrupt Status Register - 1 (Address = 0x14)
  • RxE3 Configuration & Status Register - 2 (Address = 0x11)
  • RxE3 Interrupt Enable Register - 1 (Address = 0x12)
  • RxE3 Interrupt Status Register - 1 (Address = 0x14)
  • RxE3 Configuration & Status Register 2 (Address = 0x11)
  • RxE3 Interrupt Enable Register - 1 (Address = 0x12)
  • RxE3 Configuration & Status Register - 2 (Address = 0x11)
  • RxE3 Interrupt Enable Register - 1 (Address = 0x12)
  • RxE3 Configuration & Status Register - 2 (Address = 0x11)
  • RxE3 Interrupt ENABLE Register - 1 (Address = 0x12)
  • RxE3 Interrupt Status Register - 1 (Address = 0x14)
  • RxE3 Interrupt Enable Register - 2 (Address = 0x13)
  • RxE3 Interrupt Status Register - 2 (Address = 0x15)
  • RxE3 Configuration & Status Register - 2 (Address = 0x11)
  • RxE3 Interrupt Enable Register - 2 (Address = 0x13)
  • RxE3 Interrupt Status Register - 2 (Address = 0x15)
  • RxE3 Interrupt Enable Register - 2 (Address = 0x13)
  • RxE3 Interrupt Status Register - 2 (Address = 0x15)
  • RxE3 LAPD Control Register (Address = 0x18)
  • RxE3 LAPD Control Register (Address = 0x18)
  • 6.0 E3/ITU-T G.832 Operation of the XRT7250
  • Framer Operating Mode Register (Address = 0x00)
    • 6.1 Description of the E3, ITU-T G.832 Frames and Associated Overhead Bytes
      • Figure 154. Illustration of the E3, ITU-T G.832 Framing Format.
        • 6.1.1 Definition of the Overhead Bytes
  • Framer Operating Mode Register (Address = 0x00)
    • 6.1.1.1 Frame Alignment (FA1 and FA2) Bytes
    • 6.1.1.2 Error Monitor (EM) Byte
    • 6.1.1.3 The Trail-Trace Buffer (TTB) Byte
    • Table 68: Definition of the Trail Trace Buffer Bytes, within The E3, ITU-T G.832 Framing Format
      • 6.1.1.4 Maintenance and Adaptation (MA) Byte
  • The Maintenance and Adaptation (ma) byte format
    • Table 69: A Listing of the Various Payload Type Values and their corresponding Meaning
      • 6.1.1.5 The Network Operator (NR) Byte
      • 6.1.1.6 The General Purpose Communications Channel (GC) Byte
    • 6.2 The Transmit Section of the XRT7250 (E3 Mode Operation)
      • Figure 155. A Simple Illustration of the Transmit Section, within the XRT7250, when it has been c...
        • 6.2.1 The Transmit Payload Data Input Interface Block
      • Figure 156. A Simple Illustration of the Transmit Payload Data Input Interface Block
      • Table 70: Listing and Description of the pins associated with the Transmit Payload Data Input Int...
        • 6.2.1.1 Mode 1 - The Serial/Loop-Timing Mode
      • Figure 157. Illustration of the Terminal Equipment being interfaced to the Transmit Payload Data ...
      • Figure 158. Behavior of the Terminal Interface signals between the Transmit Payload Data Input In...
  • Framer Operating Mode Register (Address = 0x00)
    • 6.2.1.2 Mode 2 - The Serial/Local-Timed/ Frame-Slave Mode Behavior of the XRT7250
    • Figure 159. Illustration of the Terminal Equipment being interfaced to the Transmit Payload Data ...
    • Figure 160. Behavior of the Terminal Interface signals between the XRT7250 and the Terminal Equip...
  • Framer Operating Mode Register (Address = 0x00)
    • 6.2.1.3 Mode 3 - The Serial/Local-Timed/ Frame-Master ModeBehavior of the XRT7250
    • Figure 161. Illustration of the Terminal Equipment being interfaced to the Transmit Payload Data ...
    • Figure 162. Behavior of the Terminal Interface signals between the XRT7250 and the Terminal Equip...
  • Framer Operating Mode Register (Address = 0x00)
    • 6.2.1.4 Mode 4 - The Nibble-Parallel/Loop- Timed Mode Behavior of the XRT7250
    • Figure 163. Illustration of the Terminal Equipment being interfaced to the Transmit Payload Data ...
    • Figure 164. Behavior of the Terminal Interface signals between the XRT7250 and the Terminal Equip...
  • Framer Operating Mode Register (Address = 0x00)
    • 6.2.1.5 Mode 5 - The Nibble-Parallel/Local- Time/Frame-Slave Interface Mode Behavior of the XRT7250
    • Figure 165. Illustration of the Terminal Equipment being interfaced to the Transmit Payload Data ...
    • Figure 166. Behavior of the Terminal Interface signals between the XRT7250 and the Terminal Equip...
  • Framer Operating Mode Register (Address = 0x00)
    • 6.2.1.6 Mode 6 - The Nibble-Parallel/Local- Timed/Frame-Master Interface Mode Behavior of the XRT...
    • Figure 167. Illustration of the Terminal Equipment being interfaced to the Transmit Payload Data ...
    • Figure 168. Behavior of the Terminal Interface signals between the XRT7250 and the Terminal Equip...
  • Framer Operating Mode Register (Address = 0x00)
    • 6.2.2 The Transmit Overhead Data Input Interface
    • Figure 169. Simple Illustration of the Transmit Overhead Data Input Interface block
    • Table 71: A Listing of the Overhead bits within the E3 frame, and their potential sources, within...
      • 6.2.2.1 Method 1 - Using the TxOHClk Clock Signal
    • Table 72: Description of Method 1 Transmit Overhead Input Interface Signals
    • Figure 170. Illustration of the Terminal Equipment being interfaced to the Transmit Overhead Data...
    • Table 73: The Relationship between the Number of Rising Clock Edges in TxOHClk, (since "TxOHFrame...
    • Figure 171. Illustration of the signal that must occur between the Terminal Equipment and the XRT...
      • 6.2.2.2 Method 2 - Using the TxInClk and TxOHEnable Signals
    • Table 74: Description of Method 1 Transmit Overhead Input Interface Signals
    • Figure 172. Illustration of the Terminal Equipment being interfaced to the Transmit Overhead Data...
    • Table 75: The Relationship between the Number of TxOHEnable pulses (since the last occurrence of ...
    • Figure 173. Behavior of Transmit Overhead Data Input Interface signals between the XRT7250 and th...
      • 6.2.3 The Transmit E3 HDLC Controller
        • 6.2.3.1 Message-Oriented Signaling (e.g., LAP-D) processing via the Transmit DS3 HDLC Controller
    • Figure 174. LAPD Message Frame Format
    • Table 76: The LAPD Message Type and the Corresponding value of the First Byte, within the Informa...
  • Transmit E3 LAPD Configuration Register (Address = 0x33)
    • Table 77: Relationship between TxLAPD Msg Length and the LAPD Message Size
  • TxE3 Configuration Register (Address = 0x30)
  • TxE3 LAPD Configuration Register (Address = 0x33)
  • Transmit E3 LAPD Configuration Register (Address = 0x33)
  • TxE3 LAPD Status and Interrupt Register (Address = 0x34)
  • TxE3 LAPD Status and Interrupt Register (Address = 0x34)
    • Figure 175. Flow Chart depicting how to use the LAPD Transmitter (LAPD Transmitter is configured ...
    • Figure 176. Flow Chart depicting how to use the LAPD Transmitter (LAPD Transmitter is configured ...
  • Block Interrupt Enable Register (Address = 0x04)
    • 6.2.4 The Transmit E3 Framer Block
      • 6.2.4.1 Brief Description of the Transmit E3 Framer
      • 6.2.4.2 Detailed Functional Description of the Transmit E3 Framer Block
    • Figure 177. A Simple Illustration of the Transmit E3 Framer Block and the associated paths to oth...
  • TxE3 Configuration Register (Address = 0x30)
    • Table 78: The Relationship between the contents of Bit 2 (Tx AIS Enable) within the Tx E3 Configu...
    • Table 79: The Relationship between the contents of Bit 1 (Tx LOS) within the Tx E3 Configuration ...
      • 6.2.5 The Transmit E3 Line Interface Block
    • Figure 178. Approach to Interfacing the XRT7250 Framer IC device to the XRT7300 DS3/E3/STS-1 LIU
    • Figure 179. A Simple Illustration of the Transmit E3 LIU Interface block
    • Figure 180. The Behavior of TxPOS and TxNEG signals during data transmission while the Transmit D...
      • 6.2.5.1 Selecting the various Line Codes
  • I/O Control Register (Address = 0x01)
    • Table 80: The Relationship between the content of Bit 3 (Unipolar/Bipolar*) within the UNI I/O Co...
    • Figure 181. Illustration of AMI Line Code
    • Figure 182. Illustration of two examples of HDB3 Encoding
  • I/O Control Register (Address = 0x01)
    • Table 81: The Relationship between Bit 4 (AMI/ HDB3*) within the I/O Control Register and the Bip...
      • 6.2.5.2 TxLineClk Clock Edge Selection
  • II/O Control Register (Address = 0x01)
    • Table 82: The Relationship between the contents of Bit 2 (TxLineClk Inv) within the I/O Control R...
    • Figure 183. Waveform/Timing Relationship between TxLineClk, TxPOS and TxNEG - TxPOS and TxNEG are...
    • Figure 184. Waveform/Timing Relationship between TxLineClk, TxPOS and TxNEG - TxPOS and TxNEG are...
      • 6.2.6 Transmit Section Interrupt Processing
        • 6.2.6.1 Enabling Transmit Section Interrupts
  • Block Interrupt Enable Register (Address = 0x04)
  • TxE3 LAPD Status and Interrupt Register (Address = 0x34)
  • TxE3 LAPD Status and Interrupt Register (Address = 0x34)
    • 6.3 The Receive Section of the XRT7250 (E3 Mode Operation)
      • Figure 185. A Simple Illustration of the Receive Section of the XRT7250, when it has been configu...
        • 6.3.1 The Receive E3 LIU Interface Block
      • Figure 186. A Simple Illustration of the Receive E3 LIU Interface Block
        • 6.3.1.1 Unipolar Decoding
      • Figure 187. Behavior of the RxPOS, RxNEG and RxLineClk signals during data reception of Unipolar ...
  • II/O Control Register (Address = 0x01)
    • Table 83: The Relationship between the contents of Bit 2 (TxLineClk Inv) within the I/O Control R...
      • 6.3.1.2 Bipolar Decoding
    • Figure 188. Illustration on how the Receive E3 Framer (within the XRT7250 Framer IC) being interf...
    • Figure 189. Illustration of AMI Line Code
    • Figure 190. Illustration of two examples of HDB3 Decoding
  • II/O Control Register (Address = 0x01)
    • Table 84: The Relationship between the contents of Bit 1 (RxLineClk Inv) of the I/O Control Regis...
    • Figure 191. Waveform/Timing Relationship between RxLineClk, RxPOS and RxNEG - When RxPOS and RxNE...
    • Figure 192. Waveform/Timing Relationship between RxLineClk, RxPOS and RxNEG - When RxPOS and RxNE...
      • 6.3.2 The Receive E3 Framer Block
    • Figure 193. A Simple Illustration of the Receive E3 Framer Block and the Associated Paths to the ...
      • 6.3.2.1 The Framing Acquisition Mode
    • Figure 194. The State Machine Diagram for the Receive E3 Framer E3 Frame Acquisition/Maintenance ...
    • Figure 195. Illustration of the E3, ITU-T G.832 Framing Format
  • RxE3 Interrupt Status Register - 1 (Address = 0x14)
  • RxE3 Configuration & Status Register 2 (Address = 0x11)
  • RxE3 Interrupt Status Register - 1 (Address = 0x14)
    • 6.3.2.2 The Framing Maintenance Mode
  • RxE3 Interrupt Status Register - 1 (Address = 0x14)
  • RxE3 Configuration & Status Register 2 (Address = 0x11)
  • PMON Framing Bit/Byte Error Count Register - MSB (Address = 0x52)
  • PMON Framing Bit/Byte Error Count Register - LSB (Address = 0x53)
    • 6.3.2.3 Forcing a Reframe via Software Command
  • RxE3 Configuration & Status Register 2 (Address = 0x11)
    • 6.3.2.4 Performance Monitoring of the Frame Synchronization Section, within the Receive E3 Framer...
    • 6.3.2.5 The RxOOF and RxLOF output pin.
    • Table 85: The Relationship between the Logic State of the RxOOF and RxLOF output pins, and the Fr...
      • 6.3.2.6 E3 Receive Alarms
  • RxE3 Configuration & Status Register 2 (Address = 0x11)
  • RxE3 Interrupt Status Register - 1 (Address = 0x14)
  • RxE3 Configuration & Status Register 2 (Address = 0x11)
  • RxE3 Interrupt Status Register - 1 (Address = 0x14)
  • RxE3 Configuration & Status Register 2 (Address = 0x11)
  • RxE3 Configuration & Status Register 2 (Address = 0x11)
  • The Maintenance and Adaptation (ma) byte format
  • RxE3 Configuration & Status Register 1 - (E3, ITU-T G.832) (Address = 0x10)
  • RxE3 Interrupt Enable Register - 2 (Address = 0x13)
  • RxE3 Configuration & Status Register 2 (Address = 0x11)
  • RxE3 Configuration & Status Register 2 (Address = 0x11)
    • 6.3.2.7 Error Checking of the Incoming E3 Frames
    • Figure 196. Illustration of the Local Receive E3 Framer block, receiving an E3 Frame (from the Re...
    • Figure 197. Illustration of the Local Receive E3 Framer block, transmitting an E3 Frame (to the R...
    • Figure 198. Illustration of the Local Receive E3 Framer block, receiving an E3 Frame (from the Re...
    • Figure 199. Illustration of the Local Receive E3 Framer block, transmitting an E3 Frame (to the R...
  • RxE3 Interrupt Status Register - 2 (Address = 0x15)
  • PMON Parity Error Count Register - MSB (Address = 0x54)
  • PMON Parity Error Count Register - LSB (Address = 0x55)
    • 6.3.2.8 Processing of the Far-End-Block Error (FEBE) Bit-fields
  • RxE3 Interrupt Status Register - 2 (Address = 0x15)
  • PMON FEBE Event Count Register - MSB (Address = 0x56)
  • PMON FEBE Event Count Register - LSB (Address = 0x57)
    • 6.3.2.9 Receiving the Trail Trace Buffer Messages
  • RxE3 Interrupt Status Register - 2 (Address = 0x15)
    • 6.3.3 The Receive HDLC Controller Block
    • Figure 200. LAPD Message Frame Format
  • RxE3 LAPD Control Register (Address = 0x18)
  • RxE3 LAPD Control Register (Address = 0x18)
  • RxE3 LAPD Status Register (Address = 0x19)
  • RxE3 LAPD Status Register (Address = 0x19)
  • RxE3 LAPD Status Register (Address = 0x19)
  • RxE3 LAPD Status Register (Address = 0x19)
  • RxE3 LAPD Status Register (Address = 0x19)
    • Table 86: The Relationship between the Contents of RxLAPDType[1:0] bit-fields and the PMDL Messag...
  • RxE3 LAPD Control Register (Address = 0x18)
  • RxE3 LAPD Status Register (Address = 0x19)
    • Figure 201. Flow Chart depicting the Functionality of the LAPD Receiver
    • Figure 202. Flow Chart depicting the Functionality of the LAPD Receiver (Continued)
      • 6.3.4 The Receive Overhead Data Output Interface
    • Figure 203. A Simple Illustration of the Receive Overhead Output Interface block
      • 6.3.4.1 Method 1 - Using the RxOHClk Clock signal
    • Figure 204. Illustration of how to interface the Terminal Equipment to the Receive Overhead Data ...
    • Table 87: Listing and Description of the Pin Associated with the Receive Overhead Data Output Int...
    • Table 88: The Relationship between the Number of Rising Clock Edges in RxOHClk, (since RxOHFrame ...
    • Figure 205. Illustration of the signals that are output via the Receive Overhead Output Interface...
      • 6.3.4.2 Method 2 - Using RxOutClk and the RxOHEnable signals
    • Table 89: Listing and Description of the Pin Associated with the Receive Overhead Data Output Int...
    • Figure 206. Illustration of how to interface the Terminal Equipment to the Receive Overhead Data ...
    • Table 90: The Relationship between the Number of RxOHEnable output pulses (since RxOHFrame was la...
    • Figure 207. Illustration of the signals that are output via the Receive Overhead Data Output Inte...
      • 6.3.5 The Receive Payload Data Output Interface
    • Figure 208. A Simple illustration of the Receive Payload Data Output Interface block
    • Table 91: Listing and Description of the pin associated with the Receive Payload Data Output Inte...
      • 6.3.5.1 Serial Mode Operation Behavior of the XRT7250
    • Figure 209. Illustration of the Receive Payload Data Output Interface Block (of the XRT7250 DS3/ ...
    • Figure 210. An Illustration of the behavior of the signals between the Receive Payload Data Outpu...
      • 6.3.5.2 Nibble-Parallel Mode OperationBehavior of the XRT7250
    • Figure 211. Illustration of the XRT7250 DS3/E3 Framer IC being interfaced to the Receive Section ...
    • Figure 212. Illustration of the signals that are output via the Receive Overhead Data Output Inte...
      • 6.3.6 Receive Section Interrupt Processing
        • 6.3.6.1 Enabling Receive Section Interrupts
  • Block Interrupt Enable Register (Address = 0x04)
    • 6.3.6.2 Enabling/Disabling and Servicing Interrupts
  • RxE3 Interrupt Enable Register - 1 (Address = 0x12)
  • RxE3 Interrupt Status Register - 1 (Address = 0x14)
  • RxE3 Configuration & Status Register 2 (Address = 0x11)
  • RxE3 Interrupt Enable Register - 1 (Address = 0x12)
  • RxE3 Interrupt Status Register - 1 (Address = 0x14)
  • RxE3 Configuration & Status Register 2 (Address = 0x11)
  • RxE3 Interrupt Enable Register - 1 (Address = 0x12)
  • RxE3 Configuration & Status Register 2 (Address = 0x11)
  • RxE3 Interrupt ENABLE Register - 1 (Address = 0x12)
  • RxE3 Interrupt Status Register - 1 (Address = 0x14)
  • RxE3 Interrupt Enable Register - 1 (Address = 0x12)
  • RxE3 Interrupt Status Register - 1 (Address = 0x14)
  • RxE3 Configuration & Status Register 2 (Address = 0x11)
  • RxE3 Interrupt Enable Register - 2 (Address = 0x13)
  • RxE3 Interrupt Status Register - 2 (Address = 0x15)
  • RxE3 Interrupt Enable Register - 2 (Address = 0x13)
  • RxE3 Interrupt Status Register - 2 (Address = 0x15)
  • RxE3 Configuration & Status Register 2 (Address = 0x11)
  • RxE3 Interrupt Enable Register - 2 (Address = 0x13)
  • RxE3 Interrupt Status Register - 2 (Address = 0x15)
  • RxE3 Interrupt Enable Register - 2 (Address = 0x13)
  • RxE3 Interrupt Status Register - 2 (Address = 0x15)
  • RxE3 Interrupt Enable Register - 2 (Address = 0x13)
  • RxE3 Interrupt Status Register - 2 (Address = 0x15)
  • RxE3 Configuration & Status Register 1 (Address = 0x10)
  • RxE3 Interrupt Enable Register - 2 (Address = 0x13)
  • RxE3 Interrupt Status Register - 2 (Address = 0x15)
  • RxE3 LAPD Control Register (Address = 0x18)
  • RxE3 LAPD Control Register (Address = 0x18)
  • 7.0 diagnostic operation of the xrt7250 framer ic
    • Figure 213. Illustration of the Framer Local Loop-back path, within the XRT7250 DS3/E3 Framer IC
• Ordering Information
• Package Dimensions
  • Revision History