XR-T7295

...the analog plus company

DS3/Sonet STS-1

Integrated Line Receiver

Rev. 1.05

1992

EXAR Corporation, 48720 Kato Road, Fremont, CA 94538

(510) 668-7000

FAX (510) 668-7017

June 1997-3

FEATURES

Fully Integrated Receive Interface for DS3 and
STS-1 Rate Signals

Integrated Equalization (Optional) and Timing
Recovery

Loss-of-Signal and Loss-of-Lock Alarms

Variable Input Sensitivity Control

5V Power Supply

Pin Compatible with XR-T7295E

Companion Device to T7296 Transmitter

APPLICATIONS

Interface to DS-3 Networks

Digital Cross-Connect Systems

CSU/DSU Equipment

PCM Test Equipment

Fiber Optic Terminals

GENERAL DESCRIPTION

The XR-T7295 DS3/SONET STS-1 integrated line
receiver is a fully integrated receive interface that
terminates a bipolar DS3 (44.736Mbps) or Sonet STS-1
(51.84Mbps) signal transmitted over coaxial cable. (See
Figure 13).

The device also provides the functions of receive
equalization (optional), automatic-gain control (AGC),
clock-recovery and data retiming, loss-of-signal and
loss-of-frequency-lock detection. The digital system
interface is dual-rail, with received positive and negative
1s appearing as unipolar digital signals on separate
output leads. The on-chip equalizer is designed for cable
distances of 0 to 450ft. from the cross-connect frame to
the device. The receive input has a variable input
sensitivity control, providing three different sensitivity

settings, to adapt longer cables. High input sensitivity
allows for significant amounts of flat loss within the
system.

Figure 1 shows the block diagram of the device.

The XR-T7295 device is manufactured using linear
CMOS technology. The XR-T7295 is available in either a
20-pin plastic DIP or 20-pin plastic SOJ package for
surface mounting.

Two versions of the chip are available, one is for either
DS3 or STS-1 operation (the XR-T7295, this data sheet),
and the other is for E3 operation (the XR-T7295E, refer to
the XR-T7295E data sheet). Both versions are pin
compatible.

For either DS3 or STS-1, an input reference clock at
44.736MHz or 51.84MHz provides the frequency
reference for the device.

ORDERING INFORMATION

Part No.

Package

Operating

Temperature Range

XR-T7295IP

20 Lead 300 Mil PDIP

-40

C to + 85

XR-T7295IW

20 Lead 300 Mil JEDEC SOJ

-40

C to + 85

XR-T7295

Rev. 1.05

BLOCK DIAGRAM

Figure 1. Block Diagram

ООООО

ООО

ООООО

ОООООО

ООО

ОО

ООО

ОО

Attenuator

AGC

Peak

Detector

Slicers

Phase

Detector

Loop
Filter

VCO

Digital

LOS

Detector

Analog

LOS

Frequency Phase

Aquisition Circuit

Equalizer

Tuning Ckt.

Analog

LOS

Gain &

Equalizer

REQB

LOSTHR

ICT

TMC1

TMC2

EXCLK

RLOL

RLOS

RNDATA

RPDATA

RCLK

LPF1

LPF2

A GNDA V

D GNDD V

C GNDC

Retimer

XR-T7295

Rev. 1.05

PIN CONFIGURATION

LOSTHR

REQB
ICT
RPDATA
RNDATA
RCLK

EXCLK

GNDA

TMC1

LPF1
LPF2

TMC2
RLOS

RLOL

GNDD

GNDC

20 Lead PDIP (0.300")

LOSTHR
REQB
ICT

GNDA

TMC1

LPF1

RPDATA

RNDATA
RCLK
EXCLK

LPF2

TMC2
RLOS

RLOL

GNDD

GNDC

20 Lead SOJ (Jedec, 0.300")

PIN DESCRIPTION

Pin #

Symbol

Type

Description

GNDA

Analog Ground.

Receive Input. Analog receive input. This pin is internally biased at about 1.5V in series
with 50 k

3,6

TMC1-TMC2

Test Mode Control 1 and 2. Internal test modes are enabled within the device by using
TMC1 and TMC2. Users must tie these pins to the ground plane.

4,5

LPF1-LPF2

PLL Filter 1 and 2. An external capacitor (0.1

20%) is connected between these pins.

RLOS

Receive Loss-of-signal. This pin us set high on loss of the data signal at the receive input.

(See

Table 7)

RLOL

Receive PLL Loss-of-lock. This pin is set high on loss of PLL frequency lock.

GNDD

Digital Ground for PLL Clock. Ground lead for all circuitry running synchronously with
PLL clock.

GNDC

Digital Ground for EXCLK. Ground lead for all circuitry running synchronously with
EXCLK.

5V Digital Supply (

10%) for PLL Clock. Power for all circuitry running synchronously

with PLL clock.

5V Digital Supply (

10%) for EXCLK. Power for all circuitry running synchronously with

EXCLK.

EXCLK

External Reference Clock. A valid DS3 (44.736MHz

100ppm) or STS-1 (51.84MHz +

100ppm) clock must be provided at this input. The duty cycle of EXCLK, referenced to V

/2 levels, must be within 40% - 60% with a minimum rise and fall time (10% to 90%) of 5ns.

RCLK

Receive Clock. Recovered clock signal to the terminal equipment.

RNDATA

Receive Negative Data. Negative pulse data output to the terminal equipment. (See
Figure 11.)

RPDATA

Receive Positive Data. Positive pulse data output to the terminal equipment. (See
Figure 11)

ICT

In-circuit Test Control (Active-low). If ICT is forced low, all digital output pins (RCLK,
RPDATA, RNDATA, RLOS, RLOL) are placed in a high-impedance state to allow for in-cir-
cuit testing. There is an internal pull-up on this pin.

REQB

Receive Equalization Bypass. A high on this pin bypasses the internal equalizer. A low
places the equalizer in the data path.

LOSTHR

Loss-of-signal Threshold Control. The voltage forced on this pin controls the input loss-
of-signal threshold. Three settings are provided by forcing GND, V

/2, or V

. This pin

must be set to the desired level upon power-up and should not be changed during opera-
tion.

5V Analog Supply (

10%).

XR-T7295

Rev. 1.05

ELECTRICAL CHARACTERISTICS

Test Conditions: T

= -40

C to +85

C, V

= 5V

10%

Typical Values are for V

= 5.0 V, 25

C, and Random Data. Maximum Values are for V

= 5.5V all 1s Data.

Symbol

Parameter

Min.

Typ.

Max.

Unit

Condition

Electrical Characteristics

Power Supply Current

DS3

REQB = 0

106

REQB = 1

103

STS-1

REQB = 0

111

REQB = 1

108

Logic Interface Characteristics

Input Voltage

Low

GNDD

0.5

High

D-

0.5

Output Voltage

Low

GNDD

0.4

-5.0mA

High

D-

0.5

5.0mA

Input Capacitance

Load Capacitance

Input Leakage

-10

-0.5 to V

+ 0.5V

(all input pins except 2 and 17)

500

0 V (pin 17)

100

(pin 2)

-50

-5

GNDD (pin 2)

Specifications are subject to change without notice

ABSOLUTE MAXIMUM RATINGS

Power Supply

-0.5V to +6.5V

. . . . . . . . . . . . . . . . . . . . .

Storage Temperature

-40

C to +125

. . . . . . . . . . . .

Power Dissipation

700 mW

. . . . . . . . . . . . . . . . . . . . . . .

XR-T7295

Rev. 1.05

ОООО

ООООО

ОООО

XR-T7296

Transmitter

Cross

Connect

Frame

DSX-3

or STSX-1

Type 728A
Coaxial Cable

0-450 ft.

System A

XR-T7295

System B

Figure 2. Application Diagram

Receiver

SYSTEM DESCRIPTION

Receive Path Configurations

In the receive signal path (see

Figure 1), the internal

equalizer can be included by setting REQB = 0 or
bypassed by setting REQB = 1. The equalizer bypass
option allows easy interfacing of the XR-T7295 device
into systems already containing external equalizers.
Figure 3 illustrates the receive path options.

In Case 1 of

Figure 3, the signal from the DSX-3

cross-connect feeds directly into R

. In this mode, the

user should set REQB = 0, engaging the equalizer in the
data path.

Table 1 and the following sections describe the

receive signal requirements.

In Case 2 of

Figure 3, external line build-out (LBO) and

equalizer networks precede the XR-T7295 device. In this
mode, the signal at R

is already equalized, and the

on-chip filters should be bypassed by setting REQB=1.
The signal at R

must meet the amplitude limits

described in

Table 1

In applications where the XR-T7295 device is used to
monitor DS3 transmitter outputs directly, the receive
equalizer should be bypassed. Again, the signal at R

must meet the amplitude limits described in

Table 1.

Minimum signals are for SOJ devices. Due to increased
package parasitics, add 3dB to all table values for DIP
devices.

Maximum input amplitude under all conditions is 850mV
pk.

Although system designers typically use power in dBm to
describe input levels, the XR-T7295 responds to peak
input signal amplitude. Therefore, the XR-T7295 input
signal limits are given in mV pk. Conversion factors are as
follows:

At DSX3: 390mV pk

0 dBm

At DSX3 + 450 ft. of cable: 310 mV pk

0 dBm

Data
Rate

REQB

LOSTHR

Minimum

Signal

Unit

DS3

mV pk

STS-1

110

mV pk

110

mV pk

110

mV pK

110

mV pk

Table 1. Receive Input Signal Amplitude

Requirements

XR-T7295

Rev. 1.05

DS3 SIGNAL REQUIREMENTS AT THE DSX

Pulse characteristics are specified at the DSX-3, which is
an interconnection and test point referred to as the
cross-connect (see

Figure 2.) The cross-connect exists

at the point where the transmitted signal reaches the
distribution frame jack.

Table 2 lists the signal

requirements. Currently, two isolated pulse template

requirements exist: the ACCUNET T45 pulse template
(see

Table 3 and Figure 4) and the G.703 pulse template

(see

Table 4 and Figure 5). Table 3 and Table 5 give the

associated boundary equations for the templates. The
XR-T7295 correctly decodes any transmitted signal that
meets one of these templates at the cross-connect.

Parameter

Specification

Line Rate

44.736 Mbps

20 ppm

Line Code

Bipolar with three-0 substitution (B3ZS)

Test Load

Pulse Shape

An isolated pulse must fit the template in

Figure 4 or Figure 5.

The pulse amplitude may be scaled by

a constant factor to fit the template. The pulse amplitude must be between 0.36vpk and 0.85vpk,
measured at the center of the pulse.

Power Levels

For and all 1s transmitted pattern, the power at 22.368

0.002MHz must be -1.8 to +5.7dBm, and

the power at 44.736

0.002MHz must be -21.8dBm to -14.3dBm.

2, 3

Notes

The pulse template proposed by G.703 standards is shown in Figure 5 and specified in Table 4. The proposed G.703 standards
further state that the voltage in a time slot containing a 0 must not exceed

5% of the peak pulse amplitude, except for the residue

of preceding pulses.

The power levels specified by the proposed G.703 standards are identical except that the power is to be measured in 3kHz bands.

The all 1s pattern must be a pure all 1s signal, without framing or other control bits.

Table 2. DSX-3 Interconnection Specification

Lower Curve

Upper Curve

Time

Equation

Time

Equation

-0.36

-0.68

-0.36

+0.28

0.5 1+sin

[

1+T/0.18

]

-0.68

+0.36

0.5 1+sin

[

1+T/0.34

]

0.28

0.11e

-3.42(T-0.3)

0.36

0.05 + 0.407e

-1.84(T-0.36)

Table 3. DSX-3 Pulse Template Boundaries for ACCUNET T45 Standards (See

Figure 4.)

XR-T7295

Rev. 1.05

Figure 4. DSX-3 Isolated Pulse Template for ACCUNET T45 Standards

ООООООООООООООО

1.0

0.8

0.6

0.4

0.2

-1.0

-0.5

0.5

1.0

1.5

2.0

Time Slots - Normalized To Peak Location

ОООООООООООООО

ОООООООО

Normalized Amplitude

Lower Curve

Upper Curve

Time

Function

Time

Function

-0.36

-0.65

-0.36

+0.28

0.5 1+sin

[

1+T/0.18

]

-0.65

1.05 1-e

-4.6(T+0.65)

0.28

0.11e

-3.42(T-0.3)

0.36

0.5 1+sin

[

1+T/0.34

]

0.36

0.05+0.407e

-1.84(T-0.36)

Table 4. DSX-3 Pulse Template Boundaries for G.703 Standards (See

Figure 5)

Figure 5. DSX-3 Isolated Pulse Template for G.703 Standards

ООООООООООООООО

1.0

0.8

0.6

0.4

0.2

-1.0

-0.5

0.5

1.0

1.5

2.0

Time Slots - Normalized To Peak Location

ОООООООООООООО

ООООООО

Normalized Amplitude

XR-T7295

Rev. 1.05

STS-1 SIGNAL REQUIREMENTS AT THE STSX

For STS-1 operation, the cross-connect is referred at the
STSX-1.

Table 5 lists the signal requirements at the

STSX-1. Instead of the DS3 isolated pulse template, an
eye diagram mask is specified for STS-1 operation
(TA-TSY-000253). The XR-T7295 correctly decodes any
transmitted signal that meets the mask shown in

Figure 6

at the STSX-1.

Parameter

Specification

Line Rate

51.84 Mbps

Line Code

Bipolar with three-0 substitution (B3ZS)

Test Load

Power Levels

A wide-band power level measurement
at the STSX-1 interface using a low-pass
filter with a 3dB cutoff frequency of at
least 200MHz is within -2.7 dBm and 4.7
dBm.

Table 5. STSX-1 Interconnection Specification

Figure 6. STSX-1 Isolated Pulse Template for Bellcore TA-TSY-000253

ООООООООООООООО

1.0

0.8

0.6

0.4

0.2

-1.0

-0.5

0.5

1.0

1.5

2.0

Time Slots - Normalized To Peak Location

ОООООООООООООО

ООООООО

Normalized Amplitude

LINE TERMINATION AND INPUT CAPACITANCE

The recommended receive termination is shown in
Figure 3 The 75

resistor terminates the coaxial cable

with its characteristic impedance. The 0.01

F capacitor

to R

couples the signal into the receive input without

disturbing the internally generated DC bias level present
on R

. The input capacitance at the R

pin is 2.8pF

typical (SOJ package) and 3.6pF typical (DIP package).

LOSS LIMITS FROM THE DSX-3 TO THE RECEIVE
INPUT

The signal at the cross-connect may travel through a
distribution frame, coaxial cable, connector, splitters, and
back planes before reaching the XR-T7295 device. This
section defines the maximum distribution frame and cable
loss from the cross-connect to the XR-T7295 input.

The distribution frame jack may introduce 0.6

0.55 dB

of loss. This loss may be any combination of flat or
shaped (cable) loss.

The maximum cable distance between the point where
the transmitted signal exits the distribution frame jack and
the XR-T7295 device is 450 ft. (see

Figure 2.) The

coaxial cable (Type 728A) used for specifying this
distance limitation has the loss and phase characteristics
shown in

Figure 7 and Figure 8. Other cable types also

may be acceptable if distances are scaled to maintain
cable loss equivalent to Type 728A cable loss.

TIMING RECOVERY

External Loop Filter Capacitor

Figure 3 shows the connection to an external 0.1

capacitor at the LPF1/LPF2 pins. This capacitor is part of
the PLL filter. A non-polarized, low-leakage capacitor
should be used. A ceramic capacitor with the value 0.1

20% is acceptable.

XR-T7295

Rev. 1.05

OUTPUT JITTER

The total jitter appearing on the RCLK output during
normal operation consists of two components. First,
some jitter appears on RCLK because of jitter on the
incoming signal. (The next section discusses the jitter
transfer characteristic, which describes the relationship
between input and output jitter.) Second, noise sources
within the XR-T7295 device and noise sources that are
coupled into the device through the power supplies and

data pattern dependent jitter due to misequalization of the
input signal, all create jitter on RCLK. The magnitude of
this internally generated jitter is a function of the PLL
bandwidth, which in turn is a function of the input 1s
density. For higher 1s density, the amount of generated
jitter decreases. Generated jitter also depends on the
quality of the power supply bypassing networks used.
Figure 12 shows the suggested bypassing network, and
Table 6 lists the typical generated jitter performance.

Figure 7. Loss Characteristic of 728A

Coaxial Cable (450 ft.)

Figure 8. Phase Characteristic of 728A

Coaxial Cable (450 ft.)

ОООООООООООО

1.0

2.0

5.0 10

100

Frequency (MHz)

ООООООООООООО

100

1.0

2.0

5.0

100

Frequency (MHz)

Loss (dB)

Phase (Degree)

JITTER TRANSFER CHARACTERISTIC

The jitter transfer characteristic indicates the fraction of
input jitter that reaches the RCLK output as a function of
input jitter frequency.

Table 6 shows Important jitter

transfer characteristic parameters.

Figure 9 also shows a

typical characteristic, with the operating conditions as
described in

Table 6. Although existing standards do not

specify jitter transfer characteristic requirements, the
XR-T7295 information is provided here to assist in
evaluation of the device.

Parameter

Typ

Max

Unit

Generated Jitter

All 1s pattern

1.0

ns peak-to-peak

Repetitive "100"
pattern

1.5

ns peak-to-peak

Jitter Transfer
Characteristic

Characteristic

Peaking

0.05

0.1

f 3dB

0 05

205

kHz

Notes

Repetitive input data pattern at nominal DSX-3 level with

= 5V T

= 25

Repetitive "100 " input at nominal DSX-3 level with V

= 5V,

= 25

Table 6. Generated Jitter and Jitter Transfer

Characteristics

XR-T7295

Rev. 1.05

JITTER ACCOMMODATION

Under all allowable operating conditions, the jitter
accommodation of the XR-T7295 device exceeds all
system requirements for error-free operation
(BER<1E

-9

). The typical (V

= 5V, T = 25

C, DSX-3

nominal signal level) jitter accommodation for the
XR-T7295 is shown in

Figure 10.

FALSE-LOCK IMMUNITY

False-lock is defined as the condition where a PLL
recovered clock obtains stable phase-lock at a frequency
not equal to the incoming data rate. The XR-T7295
device uses a combination frequency/phase-lock
architecture to prevent false-lock. An on-chip frequency
comparator continuously compares the EXCLK reference
to the PLL clock. If the frequency difference between the
EXCLK and PLL clock exceeds approximately

0.5%,

correction circuitry forces re-acquisition of the proper
frequency and phase.

ACQUISITION TIME

If a valid input signal is assumed to be already present at
R

, the maximum time between the application of device

power and error-free operation is 20ms. If power has
already been applied, the interval between the application
of valid data (or the action of valid data following a loss of
signal) and error-free operation is 4ms.

LOSS-OF-LOCK DETECTION

As stated above, the PLL acquisition aid circuitry monitors
the PLL clock frequency relative to the EXCLK frequency.
The RLOL alarm is activated if the difference between the
PLL clock and the EXCLK frequency exceeds
approximately

0.5%.

This will not occur until at least 250 bit periods after loss of
input data.

Figure 9. Typical PLL Jitter Transfer

Characteristic

ОООООООООООО

ОООООООООО

-5

-4

-3

-2

-1

100

500 1K

5K 10K

50K100K

500K

PEAK = 0.05dB

f3dB = 205kHz

Frequency (Hz)

Magnitude Response (dB)

ОООООООООООООООООООООО

1 10 100 1K 10K 100K 1000K

1.0

0.1

ООООО

XR-T7295 Typical

PUB 54014

G.824

ОООО

TR-TSY-000499

Category 1

ОООО

TR-TSY-000499

Category 2

ОООООООО

5k 10

10k 5
60k 1

300k 0.5

1M 0.4

XR-T7295 Typical

Sinewave Jitter Frequency (Hz)

Figure 10. Input Jitter Tolerance at DSX-3 Level

Jitter

Frequency

(Hz)

Jitter

Amplitude

(U.I.)

Peak-Peak Sinewave Jitter (U.I.)

XR-T7295

Rev. 1.05

A high RLOL output indicates that the acquisition circuit is
working to bring the PLL into proper frequency lock.
RLOL remains high until frequency lock has occurred;
however, the minimum RLOL pulse width is 32 clock
cycles.

PHASE HITS

In response to a phase hit in the input data, the XR-T7295
returns to error free operation in less than 2ms. During
the requisition time, RLOS may temporarily be indicated.

LOSS-OF-SIGNAL DETECTION

Figure 1 shows that analog and digital methods of
loss-of-signal (LOS) detection are combined to create the
RLOS alarm output. RLOS is set if either the analog or
digital detection circuitry indicates LOS has occurred.

ANALOG DETECTION

The analog LOS detector monitors the peak input signal
amplitude. RLOS makes a high-to-low transition (input
signal regained) when the input signal amplitude exceeds
the loss-of signal threshold defined in

Table 7. The RLOS

low-to-high transition (input signal loss) occurs at a level
typically 1.0 dB below the high-to-low transition level. The
hysteresis prevents RLOS chattering. Once set, the
RLOS alarm remains high for at least 32 clock cycles,
allowing for system detection of a LOS condition without
the use of an external latch.

To allow for varying levels of noise and crosstalk in
different applications, three loss-of-signal threshold
settings are available using the LOSTHR pin. Setting
LOSTHR = V

provides the lowest loss-of-signal

threshold; LOSTHR = V

/2 (can be produced using two

50 k

10% resistors as a voltage divider between

D and GNDD) provides an intermediate threshold;

and LOSTHR = GND provides the highest threshold. The
LOSTHR pin must be set to its desired value at power-up
and must not be changed during operation.

DIGITAL DETECTION

In addition to the signal amplitude monitoring of the
analog LOS detector, the digital LOS detector monitors
the recovered data 1s density. The RLOS alarm goes
high if 160

32 or more consecutive 0s occur in the

receive data stream. The alarm goes low when at least
ten 1s occur in a string of 32 consecutive bits. This
hysteresis prevents RLOS chattering and guarantees a
minimum RLOS pulse width of 32 clock cycles. Note,
however, that RLOS chatter can still occur. When
REQB=1, input signal levels above the analog RLOS
threshold can still be low enough to result in a high bit error
rate. The resultant data stream (containing) errors can
temporarily activate the digital LOS detector, and RLOS
chatter can occur. Therefore, RLOS should not be used
as a bit error rate monitor.

RLOS chatter can also occur when RLOL is activated
(high).

XR-T7295

Rev. 1.05

Data
Rate

REQB

LOSTHR

Min.

Threshold

Max.

Threshold

Unit

DS3

220

mV pk

145

mV pk

175

mV pk

115

mV pk

STS-1

275

mV pk

185

mV pk

115

mV pk

220

mV pk

145

mV pk

Notes
- Lower threshold is 1.5 dB below upper threshold.
- The RLOS alarm is an indication of the presence of an input signal, not a bit error rate indication. Table 1 gives the minimum

input amplitude needed for error free operation (BER < 1e-

) Independent of the RLOS state, the device will attempt to recover

correct timing data. The RLOS low-to-high transition typically occurs 1dB below the high to low transition.

Table 7. Analog Loss-of-Signal Thresholds

RECOVERED CLOCK AND DATA TIMING

Table 8 and Figure 11 summarize the timing relationships
between the logic signals RCLK, RPDATA, and RNDATA.
The duty cycle is referenced to V

/2 threshold level.

RPDATA and RNDATA change on the rising edge of
RCLK and are valid during the falling edge of RCLK. A
positive pulse at R

creates a high level on RPDATA and

a low level on RNDATA. A negative pulse at the input
creates a high level on RNDATA and a low level on
RPDATA, and a received zero produces low levels on
both RPDATA and RNDATA.

IN-CIRCUIT TEST CAPABILITY

When pulled low, the ICT pin forces all digital output
buffers (RCLK, RPDATA, RNDATA, RLOS, RLOL pins) to
be placed in a high output impedance state. This feature
allows in-circuit testing to be done on neighboring devices
without concern for XR-T7295 device buffer damage. An
internal pull-up device (nominally 50k

) is provided on

this pin therefore, users can leave this pin unconnected
for normal operation. Test equipment can pull ICT low
during in-circuit testing without damaging the device.
This is the only pin for which internal pull-up/pull-down is
provided.

XR-T7295

Rev. 1.05

TIMING CHARACTERISTICS
Test Conditions: All Timing Characteristics are Measrured with 10pF Loading, -40

+85

C, V

10%

Symbol

Parameter

Min

Typ

Max

Unit

tRCH1RCH2

Clock Rise Time (10% - 90%)

3.5

tRCL2RCL1

Clock Fall Time (10% - 90%)

2.5

tRDVRCL

Receive Data Set-up Time

5.0

tRCLRDX

Receive Data Hold Time

8.5

tRCHRDV

Receive Propagation Delay

0.6

3.7

Clock Duty Cycle

Notes

The total delay from R

to the digital outputs RPDATA and RNDATA is three and a half RCLK clocks.

Table 8. System Interface Timing Characteristics

Figure 11. Timing Diagram for System Interface

RCLK

RPDATA

RNDATA

(RC)

(RD)

tRCHRDV

tRCL2RCL1

tRCH1RCH2

tRCLRDX

tRDVRCL

BOARD LAYOUT CONSIDERATIONS

Power Supply Bypassing

Figure 12 illustrates the recommended power supply
bypassing network. A 0.1

F capacitor bypasses the

digital supplies. The analog supply V

A is bypassed by

using a 0.1

F capacitor and a shield bead that removes

significant amounts of high-frequency noise generated by
the system and by the device logic. Good quality,
high-frequency (low lead inductance) capacitors should
be used. Finally, it is most important that all ground
connections be made to a low-impedance ground plane.

Receive Input

The connections to the receive input pin, R

, must be

carefully considered. Noise-coupling must be minimized
along the path from the signal entering the board to the

input pin. Any noise coupled into the XR-T7295 input
directly degrades the signal-to-noise ratio of the input
signal and may degrade sensitivity.

PLL Filter Capacitor

The PLL filter capacitor between pins LPF1 and LPF2
must be placed as close to the chip as possible. The LPF1
and LPF2 pins are adjacent, allowing for short lead
lengths with no crossovers to the external capacitor.
Noise-coupling into the LPF1 and LPF2 pins may
degrade PLL performance.

Handling Precautions

Although protection circuitry has been designed into this
device, proper precautions should be taken to avoid
exposure to electrostatic discharge (ESD) during
handling and mounting.

XR-T7295

Rev. 1.05

Sensitive Node

Shield Bead

+5V

GNDA

GNDD

GNDC

0.1

XR-T7295

0.1

Figure 12. Recommended Power Supply

Bypassing Network

Notes

Recommended shield beads are the Fair-Rite
2643000101 or the Fair-Rite 2743019446 (surface
mount).

COMPLIANCE SPECIFICATIONS

Compliance with

AT&T Publication 54014, "ACCU-

NET

T45 Service Description and Interface Spec-

ifications," June 1987.

Compliance with

ANSI Standard T1.102-1989,

"Digital Hierarchy - Electrical Interfaces, " 1989.

Compliance with

Compatibility Bulletin 119,

"Interconnection Specification for Digital
Cross-Connects," October 1979.

Compliance with

CCITT Recommendations G.703

and G.824, 1988.

Compliance with

TR-TSY-000499, "Transport Sys-

tems Generic Requirements (TSGR): Common Re-
quirements," December 1988.

Compliance with

TA-TSY-000253, "Synchronous

Optical Network (SONET) Transport System Gener-
ic Criteria," February 1990.

XR-T7295

Rev. 1.05

2 1 3 4 5 6 7 8

R22

22K

O
S

H
R

R21

22K

SW DIP-4

RLOS

RLOL

RECEIVER

MONITOR

OUTPUTS

RLOL

RLOS

EXCLK

V
D
D
A

V
D
D
C

1
2

V
D
D
D

GNDD

GNDC

GNDA

REQB

RNDATA

RPDATA

TMC1

TMC2

LPF1

LPF2

LOSTHR

ICT/

0.01

INPUT

SIGNAL

EXTERNAL

CLOCK

R10

TCLK

GND

LLOOP

RLOOP

DS3,STS-1/E3/

TAOS

ICT/

TXLEV

ENCODIS

DECODIS

RCLK

RNDATA

RPDATA

DMO

BPV

TNDATA

TCLK

TPDATA

GNDA

GNDD

MTIP

MRING

TTIP

TRING

RCLKO

RPOS

RNEG

RNRZ

XR-T7296

RNEG

RCLKO

RPOS

LLOOP

RLOOP

T3/E3

TAOS

TXLEV

ICT

ENCODIS

DECODIS

RECEIVER

2
3

4
5

7
8

14
13

SW DIP-8

OUTPUTS

PE65966

TRING

TTIP

R15

270

R16

270

RNRZ

TNDATA

TPDATA

0.1

C3
0.1

0.1

BT1

FERRITE BEAD

FERRITE BEAD # FAIR RITE 2643000101

0.1

TRANSMITER

MONITOR
OUTPUTS

DMO

BPV

0.1

TRANSFORMER # PULSE ENGINEERING

BT2

FERRITE BEAD

0.1

PE 65966

PE 65967 IN SURFACE MOUNT

XR-T7295

RCLK

R
E
Q
B

C
T

Figure 13. Typical Application Schematic

XR-T7295

Rev. 1.05

NOTICE

EXAR Corporation reserves the right to make changes to the products contained in this publication in order to im-
prove design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits de-
scribed herein, conveys no license under any patent or other right, and makes no representation that the circuits are
free of patent infringement. Charts and schedules contained here in are only for illustration purposes and may vary
depending upon a user's specific application. While the information in this publication has been carefully checked;
no responsibility, however, is assumed for inaccuracies.

EXAR Corporation does not recommend the use of any of its products in life support applications where the failure or
malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly
affect its safety or effectiveness. Products are not authorized for use in such applications unless EXAR Corporation
receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the
user assumes all such risks; (c) potential liability of EXAR Corporation is adequately protected under the circum-
stances.

Copyright 1992 EXAR Corporation
Datasheet June 1997
Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited.

Р­Р»РµРєС‚СЂРѕРЅРЅС‹Р№ РєРѕРјРїРѕРЅРµРЅС‚: XR-T7295IP

РР»РµРєС‚СЂРѕРЅРЅС‹Р№ РєРѕРјРїРѕРЅРµРЅС‚: XR-T7295IP