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Электронный компонент: XRT72L53IC

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Exar
Corporation 48720 Kato Road, Fremont CA, 94538
(510) 668-7000
FAX (510) 668-7017
www.exar.com
PRELIMINARY
XRT72L53
THREE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
FEBRUARY 2001
REV. P1.1.7
GENERAL DESCRIPTION
The XRT72L53, 3 Channel DS3/E3 Framer IC is de-
signed to accept User Data from the Terminal Equip-
ment and insert this data into the Payload bit-fields
within an Outbound DS3/E3 Data Stream. Further,
the Framer IC is also designed to receive an Inbound
DS3/E3 Data Stream (from the Remote Terminal
Equipment) and extract out the User Data.
The XRT72L53 DS3/E3 Framer device is designed to
support full-duplex data flow between Terminal Equip-
ment and an LIU (Line Interface Unit) IC. The Framer
Device will transmit, receive and process data in the
DS3-C-bit Parity, DS3-M13, E3-ITU-T G.751 and E3-
ITU-T G.832 (November 1995 and October 1998 Re-
visions) Framing Formats.
The XRT72L53 DS3/E3 Framer IC consists of three
Transmit sections, three Receiver sections, three Per-
formance Monitor Sections and a Microprocessor in-
terface.
Each Transmit Sections, include a Transmit Payload
Data Input Interface block, a Transmit Overhead Data
Input Interface block, a Transmit FEAC and LAPD
Controller, a Transmit DS3/E3 Framer block and a
Transmit LIU Interface Block which permits the Termi-
nal Equipment to transmit data to a remote terminal.
The Receive Sections, consist of a Receive LIU Inter-
face, a Receive DS3/E3 Framer, a Receive FEAC and
LAPD Controller, a Receive Payload Data Output In-
terface, and a Receive Overhead Data Interface
which allows the local terminal equipment to receive
data from remote terminal equipment.
The Microprocessor Interface is used to configure the
Framer IC in different operating modes and monitor
the performance of the Framer.
The Performance Monitor Sections consist of a large
number of Reset-upon-Read and Read-Only regis-
ters that contain cumulative and One-Second statis-
tics that reflect the performance/health of the three
channels of the Framer IC/system.
FEATURES
Transmits, Receives and Processes data in the
DS3-C-bit Parity, DS3-M13, E3-ITU-T G.751 and
E3-ITU-T G.832 Framing Formats.
3 Channel HDLC Controller - Tx and Rx
Interfaces to all Popular Microprocessors
Integrated Framer Performance Monitor
Available in a 272 Ball PBGA package
3.3V Power Supply, 5V Tolerant I/O
Operating Temperature -40C to +85C
APPLICATIONS
Network Interface Units
CSU/DSU Equipment.
PCM Test Equipment
Fiber Optic Terminals
DS3/E3 Frame Relay Equipment
F
IGURE
1. B
LOCK
D
IAGRAM
OF
THE
XRT72L53
T3/E3 Transmit
Framer
T3 FEAC & Data
Link Controller
T3/E3 Receive
Framer
Performance
Monitor
Interrupt
Controller
TxOHInd[n:0]
TxNibFrame[n:0]
TxFrame[n:0]
TxNibClk[n:0]
TxLnClk[n:0]
TxFrameRef[n:0]
TxNib[n:0]
TxSer[n:0]
T3/E3
transmit
Input
RxClk[n:0]
RxOHind[n:0]
RxFrame[n:0]
RxNib[n:0]
RxSer[n:0]
RxOUTClk[n:0]
T3/E3
Receive
Output
uP
Interface
Typical Channel n
Where n = 0, 1 & 2
TxLineClk[n:0]
TxPOS[n:0]
TxNEG[n:0]
RxLineClk[n:0]
RxPOS[n:0]
RxNEG[n:0]
ExtLOS
LIU
Interface/
Controller
TxOHEnable
TxOHClk
TxOHFrame
TxAISEn
TxOH
TxOHIns
T3/E3
Transmit
Overhead
Interface
RxOHEnable[n:0]
RxOHClk[n:0]
RxOH[n:0]
RxRed[n:0]
RxOHFrame[n:0]
RxOOF[n:0]
T3/E3
Receive
Overhead
Interface
HDLC
controller
HDLC
controller
Reset
TestMode
NibbleLnTF
A(11:0)
D(7:0)
ALE_AS
WR_R/W
CS
RDY_DTCK
Reset
INT
MOTO
RD_DS
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XRT72L53
THREE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
REV. P1.1.7
PRELIMINARY
2
F
IGURE
2. P
IN
O
UT
OF
THE
XRT72L53
20
19
1
2
3
4
5
6
7
8
17
18
13
14
15
16
9
10
11
12
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
(See pin list for pin names and function)
G
G
G
XRT72L53
G
G
G
L
20
G
V
DD
G
L
18
L
19
A1
D1
G
C1
B1
G
V
DD
L4
G
G
T4
E1
F1
G1
H1
J1
K1
L1
M1
U1
V1
W1
Y1
N1
P1
R1
T1
L2
T2
L3
T3
G
G
G
G
G
G
G
G
G
G
G
G
G
G
G
G
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
ORDERING INFORMATION
P
ART
N
UMBER
P
ACKAGE
T
YPE
O
PERATING
T
EMPERATURE
R
ANGE
XRT72L53
27x27 mm 272 Ball PBGA
-40C to +85C
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XRT72L53
THREE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
PRELIMINARY
REV. P1.1.7
I
TABLE OF CONTENTS
GENERAL DESCRIPTION ............................................................................................... 1
FEATURES
................................................................................................................................................. 1
APPLICATIONS
........................................................................................................................................... 1
Figure 1. Block Diagram of the XRT72L53 ............................................................................................ 1
Figure 2. Pin Out of the XRT72L53 ........................................................................................................ 2
ORDERING INFORMATION ......................................................................................................................... 2
PIN DESCRIPTIONS ........................................................................................................ 3
ELECTRICAL CHARACTERISTICS .............................................................................. 33
A
BSOLUTE
M
AXIMUMS
............................................................................................................................. 33
DC E
LECTRICAL
C
HARACTERISTICS
......................................................................................................... 33
AC E
LECTRICAL
C
HARACTERISTICS
......................................................................................................... 33
AC E
LECTRICAL
C
HARACTERISTICS
(C
ONT
.) ............................................................................................ 35
1.0 Timing Diagrams ................................................................................................................................. 39
Figure 3. Timing Diagram for Transmit Payload Input Interface, when the XRT72L53 Device is operating in
both the DS3 and Loop-Timing Modes ................................................................................................. 39
Figure 4. Timing Diagram for the Transmit Payload Input Interface, when the XRT72L53 Device is operating
in both the DS3 and Local-Timing Modes ............................................................................................. 39
Figure 5. Timing Diagram for the Transmit Payload Data Input Interface, when the XRT72L53 Device is
operating in both the DS3/Nibble and Looped-Timing Modes .............................................................. 40
Figure 6. Timing Diagram for the Transmit Payload Data Input Interface, when the XRT72L53 Device is
operating in the DS3/Nibble and Local-Timing Modes .......................................................................... 40
Figure 7. Timing Diagram for the Transmit Overhead Data Input Interface (Method 1 Access) .......... 41
Figure 8. Timing Diagram for the Transmit Overhead Data Input Interface (Method 2 Access) .......... 41
Figure 9. Transmit LIU Interface Timing - Framer is configured to update "TxPOS" and "TxNEG" on the
rising edge of "TxLineClk" ..................................................................................................................... 42
Figure 10. Transmit LIU Interface Timing - Framer is configured to update "TxPOS" and "TxNEG" on the
falling edge of "TxLineClk" .................................................................................................................... 42
Figure 11. Receive LIU Interface Timing - Framer is configured to sample "RxPOS" and "RxNEG" on the
rising edge of "RxLineClk" ..................................................................................................................... 43
Figure 12. Receiver LIU Interface Timing - Framer is configured to sample "RxPOS" and "RxNEG" on the
falling edge of "RxLineClk" .................................................................................................................... 43
Figure 13. Receive Payload Data Output Interface Timing .................................................................. 44
Figure 14. Receive Payload Data Output Interface Timing (Nibble Mode Operation) ......................... 44
Figure 15. Receive Overhead Data Output Interface Timing (Method 1 - Using RxOHClk) ................ 45
Figure 16. Receive Overhead Data Output Interface Timing (Method 2 - Using RxOHEnable) .......... 45
Figure 17. Microprocessor Interface Timing - Intel Type Programmed I/O Read Operations .............. 46
Figure 18. Microprocessor Interface Timing - Intel Type Programmed I/O Write Operations .............. 46
Figure 19. Microprocessor Interface Timing - Intel Type Read Burst Access Operation ..................... 47
Figure 20. Microprocessor Interface Timing - Intel type Write Burst Access Operation ....................... 47
Figure 21. Microprocessor Interface Timing - Motorola Type Programmed I/O Read Operation ........ 48
Figure 22. Microprocessor Interface Timing - Motorola Type Programmed I/O Write Operation ......... 48
Figure 23. Microprocessor Interface Timing - Reset Pulse Width ........................................................ 49
2.0 The Microprocessor Interface Block ................................................................................................. 50
2.1 C
HANNEL
S
ELECTION
WITHIN
THE
XRT72L53 D
EVICE
.......................................................................................... 50
T
ABLE
1: T
HE
R
ELATIONSHIP
BETWEEN
A
DDRESS
B
ITS
A9, A10
AND
THE
S
ELECTED
C
ONFIGURATION
R
EGISTER
B
ANK
...................................................................................................................................................... 50
Figure 24. Simple Block Diagram of the Microprocessor Interface Block, within the Framer IC .......... 51
2.2 T
HE
M
ICROPROCESSOR
I
NTERFACE
B
LOCK
S
IGNAL
.............................................................................................. 51
T
ABLE
2: D
ESCRIPTION
OF
THE
M
ICROPROCESSOR
I
NTERFACE
S
IGNALS
THAT
EXHIBIT
CONSTANT
ROLES
IN
BOTH
THE
I
NTEL
AND
M
OTOROLA
M
ODES
.......................................................................................................... 52
T
ABLE
3: P
IN
D
ESCRIPTION
OF
M
ICROPROCESSOR
I
NTERFACE
S
IGNALS
- W
HILE
THE
M
ICROPROCESSOR
I
NTER
-
FACE
IS
O
PERATING
IN
THE
I
NTEL
M
ODE
.................................................................................................. 52
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XRT72L53
THREE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
REV. P1.1.7
PRELIMINARY
II
T
ABLE
4: P
IN
D
ESCRIPTION
OF
THE
M
ICROPROCESSOR
I
NTERFACE
S
IGNALS
WHILE
THE
M
ICROPROCESSOR
I
N
-
TERFACE
IS
OPERATING
IN
THE
M
OTOROLA
M
ODE
..................................................................................... 53
2.3 I
NTERFACING
THE
XRT72L53 DS3/E3 F
RAMER
TO
THE
L
OCAL
C/P
VIA
THE
M
ICROPROCESSOR
I
NTERFACE
B
LOCK
53
2.3.1 Interfacing the XRT72L53 DS3/E3 Framer to the Microprocessor over an 8 bit wide bi-directional Data Bus
53
2.3.2 Data Access Modes ................................................................................................................................ 54
Figure 25. Behavior of Microprocessor Interface signals during an Intel-type Programmed I/O Read Oper-
ation ....................................................................................................................................................... 55
Figure 26. Behavior of the Microprocessor Interface Signals, during an Intel-type Programmed I/O Write
Operation ............................................................................................................................................... 56
Figure 27. Illustration of the Behavior of Microprocessor Interface signals, during a Motorola-type Pro-
grammed I/O Read Operation ............................................................................................................... 57
Figure 28. Illustration of the Behavior of the Microprocessor Interface signal, during a Motorola-type Pro-
grammed I/O Write Operation ............................................................................................................... 58
Figure 29. Behavior of the Microprocessor Interface Signals, during the Initial Read Operation of a Burst
Cycle (Intel Type Processor) ................................................................................................................. 59
Figure 30. Behavior of the Microprocessor Interface Signals, during subsequent Read Operations within
the Burst I/O Cycle ................................................................................................................................ 60
Figure 31. Behavior of the Microprocessor Interface signals, during the Initial Write Operation of a Burst
Cycle (Intel-type Processor) .................................................................................................................. 62
Figure 32. Behavior of the Microprocessor Interface Signals, during subsequent Write Operations within
the Burst I/O Cycle ................................................................................................................................ 63
Figure 33. Behavior of the Microprocessor Interface Signals, during the Initial Read Operation of a Burst
Cycle (Motorola Type Processor) .......................................................................................................... 64
Figure 34. Behavior the Microprocessor Interface Signals, during subsequent Read Operations within the
Burst I/O Cycle (Motorola-type C/P) .................................................................................................. 65
Figure 35. Behavior of the Microprocessor Interface signals, during the Initial Write Operation of a Burst
Cycle (Motorola-type Processor) ........................................................................................................... 66
Figure 36. Behavior of the Microprocessor Interface Signals, during subsequent Write Operations with the
Burst I/O Cycle (Motorola-type C/P) .................................................................................................. 67
2.4 O
N
-C
HIP
R
EGISTER
O
RGANIZATION
...................................................................................................................... 67
2.4.1 Framer Register Addressing .................................................................................................................... 67
T
ABLE
5: R
EGISTER
A
DDRESSING
OF
THE
F
RAMER
P
ROGRAMMER
R
EGISTERS
......................................... 68
2.4.2 Framer Register Description .................................................................................................................... 71
P
ART
N
UMBER
R
EGISTER
(A
DDRESS
= 0
X
02) .......................................................................................... 74
V
ERSION
N
UMBER
R
EGISTER
(A
DDRESS
= 0
X
03) ..................................................................................... 74
B
LOCK
I
NTERRUPT
E
NABLE
R
EGISTER
(A
DDRESS
= 0
X
04) ........................................................................ 74
B
LOCK
I
NTERRUPT
S
TATUS
R
EGISTER
(A
DDRESS
= 0
X
05) ........................................................................ 75
TEST R
EGISTER
(A
DDRESS
= 0
X
0C) ....................................................................................................... 76
R
X
DS3 C
ONFIGURATION
& S
TATUS
R
EGISTER
(A
DDRESS
= 0
X
10) ........................................................... 77
R
X
DS3 S
TATUS
R
EGISTER
(A
DDRESS
= 0
X
11) ........................................................................................ 78
R
X
DS3 I
NTERRUPT
E
NABLE
R
EGISTER
(A
DDRESS
= 0
X
12) ....................................................................... 79
R
X
DS3 I
NTERRUPT
S
TATUS
R
EGISTER
(A
DDRESS
= 0
X
13) ....................................................................... 80
R
X
DS3 SYNC D
ETECT
E
NABLE
R
EGISTER
(A
DDRESS
= 0
X
14) ................................................................ 82
R
X
DS3 FEAC I
NTERRUPT
E
NABLE
/S
TATUS
R
EGISTER
(A
DDRESS
= 0
X
17) ............................................... 82
R
X
DS3 LAPD C
ONTROL
R
EGISTER
(A
DDRESS
= 0
X
18) ........................................................................... 83
R
X
DS3 LAPD S
TATUS
R
EGISTER
(A
DDRESS
= 0
X
19) .............................................................................. 84
2.4.3 Receive E3 Framer Configuration Registers (ITU-T G.832) .................................................................... 84
R
X
E3 C
ONFIGURATION
& S
TATUS
R
EGISTER
1 (A
DDRESS
= 0
X
10) ........................................................... 85
R
X
E3 C
ONFIGURATION
& S
TATUS
R
EGISTER
2 (A
DDRESS
= 0
X
11) ........................................................... 86
R
X
E3 I
NTERRUPT
E
NABLE
R
EGISTER
- 1 (A
DDRESS
= 0
X
12) .................................................................... 87
R
X
E3 I
NTERRUPT
E
NABLE
R
EGISTER
- 2 (A
DDRESS
= 0
X
13) .................................................................... 88
R
X
E3 I
NTERRUPT
S
TATUS
R
EGISTER
- 1 (A
DDRESS
= 0
X
14) .................................................................... 88
R
X
E3 I
NTERRUPT
S
TATUS
R
EGISTER
- 2 (A
DDRESS
= 0
X
15) .................................................................... 90
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XRT72L53
THREE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
PRELIMINARY
REV. P1.1.7
III
R
X
E3 LAPD C
ONTROL
R
EGISTER
(A
DDRESS
= 0
X
18) ............................................................................. 91
R
X
E3 LAPD S
TATUS
R
EGISTER
(A
DDRESS
= 0
X
19) ................................................................................ 91
R
X
E3 NR B
YTE
R
EGISTER
(A
DDRESS
= 0
X
1A) ........................................................................................ 92
R
X
E3 GC B
YTE
R
EGISTER
(A
DDRESS
= 0
X
1B) ....................................................................................... 92
R
X
E3 TTB-0 R
EGISTER
(A
DDRESS
= 0
X
1C) ............................................................................................ 93
R
X
E3 TTB-1 R
EGISTER
(A
DDRESS
= 0
X
1D) ............................................................................................ 93
R
X
E3 TTB-2 R
EGISTER
(A
DDRESS
= 0
X
1E) ............................................................................................ 93
R
X
E3 TTB-3 R
EGISTER
(A
DDRESS
= 0
X
1F) ............................................................................................ 94
R
X
E3 TTB-4 R
EGISTER
(A
DDRESS
= 0
X
20) ............................................................................................ 94
R
X
E3 TTB-5 R
EGISTER
(A
DDRESS
= 0
X
21) ............................................................................................ 94
R
X
E3 TTB-6 R
EGISTER
(A
DDRESS
= 0
X
22) ............................................................................................ 94
R
X
E3 TTB-7 R
EGISTER
(A
DDRESS
= 0
X
23) ............................................................................................ 95
R
X
E3 TTB-8 R
EGISTER
(A
DDRESS
= 0
X
24) ............................................................................................ 95
R
X
E3 TTB-9 R
EGISTER
(A
DDRESS
= 0
X
25) ............................................................................................ 95
R
X
E3 TTB-10 R
EGISTER
(A
DDRESS
= 0
X
26) .......................................................................................... 96
R
X
E3 TTB-11 R
EGISTER
(A
DDRESS
= 0
X
27) .......................................................................................... 96
R
X
E3 TTB-12 R
EGISTER
(A
DDRESS
= 0
X
28) .......................................................................................... 96
R
X
E3 TTB-13 R
EGISTER
(A
DDRESS
= 0
X
29 ........................................................................................... 96
R
X
E3 TTB-14 R
EGISTER
(A
DDRESS
= 0
X
2A) .......................................................................................... 97
R
X
E3 TTB-15 R
EGISTER
(A
DDRESS
= 0
X
2B) .......................................................................................... 97
R
X
E3
SSM
R
EGISTER
(A
DDRESS
= 0
X
2B) ................................................................................................ 97
2.4.4 Receive E3 Framer Configuration Registers (ITU-T G.751) ................................................................... 98
R
X
E3 C
ONFIGURATION
& S
TATUS
R
EGISTER
- 1 G.751 (A
DDRESS
= 0
X
10) ............................................. 98
R
X
E3 C
ONFIGURATION
& S
TATUS
R
EGISTER
- 2 (A
DDRESS
= 0
X
11) ........................................................ 98
R
X
E3 I
NTERRUPT
E
NABLE
R
EGISTER
- 1 (A
DDRESS
= 0
X
12) ................................................................... 99
R
X
E3 I
NTERRUPT
E
NABLE
R
EGISTER
- 2 (A
DDRESS
= 0
X
13) ................................................................. 100
R
X
E3 I
NTERRUPT
S
TATUS
R
EGISTER
- 1 (A
DDRESS
= 0
X
14) ................................................................. 100
R
X
E3 I
NTERRUPT
S
TATUS
R
EGISTER
- 2 (A
DDRESS
= 0
X
15) ................................................................. 101
R
X
E3 LAPD C
ONTROL
R
EGISTER
(A
DDRESS
= 0
X
18) ........................................................................... 102
R
X
E3 LAPD S
TATUS
R
EGISTER
(A
DDRESS
= 0
X
19) .............................................................................. 102
R
X
E3 S
ERVICE
B
IT
R
EGISTER
(A
DDRESS
= 0
X
1A) ................................................................................. 103
2.4.5 Transmit DS3 Configuration Registers .................................................................................................. 103
T
RANSMIT
DS3 C
ONFIGURATION
R
EGISTER
(A
DDRESS
= 0
X
30) ............................................................. 104
T
RANSMIT
DS3 FEAC C
ONFIGURATION
& S
TATUS
R
EGISTER
(A
DDRESS
= 0
X
31) .................................. 105
T
X
DS3 FEAC R
EGIS
T
ER
(A
DDRESS
= 0
X
32) ........................................................................................ 106
T
X
DS3 LAPD C
ONFIGURATION
R
EGISTER
(A
DDRESS
= 0
X
33) ............................................................... 106
T
X
DS3 LAPD S
TATUS
AND
I
NTERRUPT
R
EGISTER
(A
DDRESS
= 0
X
34) ................................................... 107
T
X
DS3 M-B
IT
M
ASK
R
EGISTER
(A
DDRESS
= 0
X
35) ............................................................................... 107
T
X
DS3 F-B
IT
M
ASK
R
EGISTER
- 1 (A
DDRESS
= 0
X
36) ........................................................................... 108
T
X
DS3 F-B
IT
M
ASK
R
EGISTER
- 2 (A
DDRESS
= 0
X
37) ........................................................................... 109
T
X
DS3 F-B
IT
M
ASK
R
EGISTER
- 3 (A
DDRESS
= 0
X
38) ........................................................................... 109
T
X
DS3 F-B
IT
M
ASK
R
EGISTER
- 4 (A
DDRESS
= 0
X
39) ........................................................................... 109
2.4.6 Transmit E3 (ITU-T G.832) Configuration Registers ............................................................................. 109
T
X
E3 C
ONFIGURATION
R
EGISTER
(A
DDRESS
= 0
X
30) ............................................................................ 110
T
X
E3 LAPD C
ONFIGURATION
R
EGISTER
(A
DDRESS
= 0
X
33) ................................................................. 111
T
X
E3 LAPD S
TATUS
AND
I
NTERRUPT
R
EGISTER
(A
DDRESS
= 0
X
34) ...................................................... 111
T
X
E3 GC B
YTE
R
EGISTER
(A
DDRESS
= 0
X
35) ...................................................................................... 112
T
X
E3 MA B
YTE
R
EGISTER
(A
DDRESS
= 0
X
36) ...................................................................................... 113
T
X
E3 MA B
YTE
R
EGISTER
(A
DDRESS
= 0
X
36) ...................................................................................... 113
T
X
E3 NR B
YTE
R
EGISTER
(A
DDRESS
= 0
X
37) ...................................................................................... 113
T
X
E3 TTB-0 R
EGISTER
(A
DDRESS
= 0
X
38) ........................................................................................... 114
T
X
E3 TTB-1 R
EGISTER
(A
DDRESS
= 0
X
39) ........................................................................................... 114
T
X
E3 TTB-2 R
EGISTER
(A
DDRESS
= 0
X
3A) .......................................................................................... 114
T
X
E3 TTB-3 R
EGISTER
(A
DDRESS
= 0
X
3B) .......................................................................................... 115
T
X
E3 TTB-4 R
EGISTER
(A
DDRESS
= 0
X
3C) .......................................................................................... 115

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