Электронный компонент: XRT72L54

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Exar

Corporation 48720 Kato Road, Fremont CA, 94538

�

(510) 668-7000

�

FAX (510) 668-7017

�

www.exar.com

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PRELIMINARY

XRT72L54

FOUR CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

JANUARY 2001

REV. P1.1.2

GENERAL DESCRIPTION

The XRT72L54, 4 Channel DS3/E3 Framer IC is de-
signed to accept "User Data" from the Terminal
Equipment and insert this data into the "payload" bit-
fields within an "outbound" DS3/E3 Data Stream. Fur-
ther, the Framer IC is also designed to receive an "in-
bound" DS3/E3 Data Stream (from the Remote Ter-
minal Equipment) and extract out the "User Data".

The XRT72L54 DS3/E3 Framer device is designed to
support full-duplex data flow between Terminal Equip-
ment and an LIU (Line Interface Unit) IC. The Framer
Device will transmit, receive and process data in the
DS3-C-bit Parity, DS3-M13, E3-ITU-T G.751 and E3-
ITU-T G.832 Framing Formats.

The XRT72L54 DS3/E3 Framer IC consists of Four
Transmit sections, Four Receiver sections, Four Per-
formance Monitor Sections and a Microprocessor in-
terface.

The Transmit Sections, include a Transmit Payload
Data Input Interface, a Transmit Overhead data Input
Interface Section, a Transmit HDLC Controller, a
Transmit DS3/E3 Framer block and a Transmit LIU In-
terface Block which permits the Terminal Equipment
to transmit data to a remote terminal.

The Receive Sections, consist of a Receive LIU Inter-
face, a Receive DS3/E3 Framer, a Receive HDLC
Controller, a Receive Payload Data Output Interface,
and a Receive Overhead Data Interface which allows

the local terminal equipment to receive data from re-
mote terminal equipment.

The Microprocessor Interface is used to configure the
Framer IC in different operating modes and monitor
the performance of the Framer.

The Performance Monitor Sections consist of a large
number of "Reset-upon-Read" and "Read-Only" reg-
isters that contain cumulative and "one-second" sta-
tistics that reflect the performance/health of the Four
channels of the Framer IC/system.

FEATURES

� Transmits, Receives and Processes data in the

DS3-C-bit Parity, DS3-M13, E3-ITU-T G.751 and
E3-ITU-T G.832 Framing Formats.

� 6 Channel HDLC Controller - Tx and Rx

� Interfaces to all Popular Microprocessors

� Integrated Framer Performance Monitor

� Available in a 272 Ball PBGA package

� 3.3V Power Supply, 5V Tolerant I/O

� Operating Temperature -40�C to +85�C

APPLICATIONS

� Network Interface Units

� CSU/DSU Equipment.

� PCM Test Equipment

� Fiber Optic Terminals

� DS3/E3 Frame Relay Equipment

F

IGURE

1. B

LOCK

D

IAGRAM

OF

THE

XRT72L54

T3/E3 Transmit

Framer

T3 FEAC & Data

Link Controller

T3/E3 Receive

Framer

Performance

Monitor

Interrupt

Controller

TxOHInd[n:0]
TxNibFrame[n:0]
TxFrame[n:0]
TxNibClk[n:0]
TxLnClk[n:0]
TxFrameRef[n:0]
TxNib[n:0]
TxSer[n:0]

T3/E3

transmit

Input

RxClk[n:0]
RxOHind[n:0]
RxFrame[n:0]
RxNib[n:0]
RxSer[n:0]
RxOUTClk[n:0]

T3/E3

Receive

Output

uP

Interface

Typical Channel n

Where n = 0, 1, 2 & 3

TxLineClk[n:0]

TxPOS[n:0]

TxNEG[n:0]

RxLineClk[n:0]

RxPOS[n:0]

RxNEG[n:0]

ExtLOS

LIU

Interface/

Controller

TxOHEnable

TxOHClk

TxOHFrame

TxAISEn

TxOH

TxOHIns

T3/E3

Transmit

Overhead

Interface

RxOHEnable[n:0]

RxOHClk[n:0]

RxOH[n:0]

RxRed[n:0]

RxOHFrame[n:0]

RxOOF[n:0]

T3/E3

Receive

Overhead

Interface

HDLC

controller

HDLC

controller

Reset

TestMode

NibbleLnTF

A(11:0)
D(7:0)
ALE_AS
WR_R/W
CS
RDY_DTCK
Reset
INT
MOTO
RD_DS

XRT72L54

��

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FOUR CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

REV. P1.1.2

PRELIMINARY

2

ORDERING INFORMATION

F

IGURE

2. P

IN

O

UT

OFTHE

XRT72L54

20

19

1

2

3

4

5

6

7

8

17

18

13

14

15

16

9

10

11

12

A

B

C

D

E

F

G

H

J

K

L

M

N

P

R

T

U

V

W

Y

(See pin list for pin names and function)

G

G

G

XRT72L54

G

G

G

L

20

G

V

DD

G

L

18

L

19

A1

D4

G

C1

B1

G

V

DD

L4

G

G

T4

E1

F1

G1

H1

J1

K1

L1

M1

U1

V1

W1

Y1

N1

P1

R1

T1

L2

T2

L3

T3

G

G

G

G

G

G

G

G

G

G

G

G

G

G

G

G

V

DD

V

DD

V

DD

V

DD

V

DD

V

DD

V

DD

V

DD

V

DD

V

DD

P

ART

N

UMBER

P

ACKAGE

T

YPE

O

PERATING

T

EMPERATURE

R

ANGE

XRT72L54

27x27 mm 272 Ball PBGA

-40�C to +85�C

��

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XRT72L54

FOUR CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

ADVANCED CONFIDENTIAL

REV. P1.1.2

I

TABLE OF CONTENTS

GENERAL DESCRIPTION ............................................................................................... 1

FEATURES

................................................................................................................................................. 1

APPLICATIONS

........................................................................................................................................... 1

Figure 1. Block Diagram of the XRT72L54 ............................................................................................ 1
Figure 2. Pin Out ofthe XRT72L54 ......................................................................................................... 2

ORDERING INFORMATION ............................................................................................ 2
ELECTRICAL CHARACTERISTICS .............................................................................. 28

A

BSOLUTE

M

AXIMUMS

............................................................................................................................. 28

DC E

LECTRICAL

C

HARACTERISTICS

......................................................................................................... 28

AC E

LECTRICAL

C

HARACTERISTICS

......................................................................................................... 28

AC E

LECTRICAL

C

HARACTERISTICS

(C

ONT

.) ............................................................................................ 30

1.0 Timing Diagrams ................................................................................................................................. 34

Figure 3. Timing Diagram for Transmit Payload Input Interface, when the XRT72L54 Device is operating in
both the DS3 and Loop-Timing Modes ................................................................................................. 34
Figure 4. Timing Diagram for the Transmit Payload Input Interface, when the XRT72L54 Device is operating
in both the DS3 and Local-Timing Modes ............................................................................................. 34
Figure 5. Timing Diagram for the Transmit Payload Data Input Interface, when the XRT72L54 Device is
operating in both the DS3/Nibble and Looped-Timing Modes .............................................................. 35
Figure 6. Timing Diagram for the Transmit Payload Data Input Interface, when the XRT72L54 Device is
operating in the DS3/Nibble and Local-Timing Modes .......................................................................... 35
Figure 7. Timing Diagram for the Transmit Overhead Data Input Interface (Method 1 Access) .......... 36
Figure 8. Timing Diagram for the Transmit Overhead Data Input Interface (Method 2 Access) .......... 36
Figure 9. Transmit LIU Interface Timing - Framer is configured to update "TxPOS" and "TxNEG" on the
rising edge of "TxLineClk" ..................................................................................................................... 37
Figure 10. Transmit LIU Interface Timing - Framer is configured to update "TxPOS" and "TxNEG" on the
falling edge of "TxLineClk" .................................................................................................................... 37
Figure 11. Receive LIU Interface Timing - Framer is configured to sample "RxPOS" and "RxNEG" on the
rising edge of "RxLineClk" ..................................................................................................................... 38
Figure 12. Receiver LIU Interface Timing - Framer is configured to sample "RxPOS" and "RxNEG" on the
falling edge of "RxLineClk" .................................................................................................................... 38
Figure 13. Receive Payload Data Output Interface Timing .................................................................. 39
Figure 14. Receive Payload Data Output Interface Timing (Nibble Mode Operation) ......................... 39
Figure 15. Receive Overhead Data Output Interface Timing (Method 1 - Using RxOHClk) ................ 40
Figure 16. Receive Overhead Data Output Interface Timing (Method 2 - Using RxOHEnable) .......... 40
Figure 17. Microprocessor Interface Timing - Intel Type Programmed I/O Read Operations .............. 41
Figure 18. Microprocessor Interface Timing - Intel Type Programmed I/O Write Operations .............. 41
Figure 19. Microprocessor Interface Timing - Intel Type Read Burst Access Operation ..................... 42
Figure 20. Microprocessor Interface Timing - Intel type Write Burst Access Operation ....................... 42
Figure 21. Microprocessor Interface Timing - Motorola Type Programmed I/O Read Operation ........ 43
Figure 22. Microprocessor Interface Timing - Motorola Type Programmed I/O Write Operation ......... 43
Figure 23. Microprocessor Interface Timing - Reset Pulse Width ........................................................ 44

2.0 The Microprocessor Interface Block ................................................................................................. 45

2.1 C

HANNEL

S

ELECTION

WITHIN

THE

XRT72L54 D

EVICE

.......................................................................................... 45

T

ABLE

1: T

HE

R

ELATIONSHIP

BETWEEN

A

DDRESS

B

ITS

A9, A10

AND

THE

S

ELECTED

C

ONFIGURATION

R

EGISTER

B

ANK

...................................................................................................................................................... 45

Figure 24. Simple Block Diagram of the Microprocessor Interface Block, within the Framer IC .......... 46

2.2 T

HE

M

ICROPROCESSOR

I

NTERFACE

B

LOCK

S

IGNAL

.............................................................................................. 46

T

ABLE

2: D

ESCRIPTION

OF

THE

M

ICROPROCESSOR

I

NTERFACE

S

IGNALS

THAT

EXHIBIT

CONSTANT

ROLES

IN

BOTH

THE

I

NTEL

AND

M

OTOROLA

M

ODES

.......................................................................................................... 47

T

ABLE

3: P

IN

D

ESCRIPTION

OF

M

ICROPROCESSOR

I

NTERFACE

S

IGNALS

- W

HILE

THE

M

ICROPROCESSOR

I

NTER

-

FACE

IS

O

PERATING

IN

THE

I

NTEL

M

ODE

.................................................................................................. 47

T

ABLE

4: P

IN

D

ESCRIPTION

OF

THE

M

ICROPROCESSOR

I

NTERFACE

S

IGNALS

WHILE

THE

M

ICROPROCESSOR

I

N

-

XRT72L54

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FOUR CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

REV. P1.1.2

PRELIMINARY

II

TERFACE

IS

OPERATING

IN

THE

M

OTOROLA

M

ODE

..................................................................................... 48

2.3 I

NTERFACING

THE

XRT72L54 DS3/E3 F

RAMER

TO

THE

L

OCAL

�C/�P

VIA

THE

M

ICROPROCESSOR

I

NTERFACE

B

LOCK

48

2.3.1 Interfacing the XRT72L54 DS3/E3 Framer to the Microprocessor over an 8 bit wide bi-directional Data Bus
48
2.3.2 Data Access Modes ................................................................................................................................ 49

Figure 25. Behavior of Microprocessor Interface signals during an Intel-type Programmed I/O Read Oper-
ation ....................................................................................................................................................... 50
Figure 26. Behavior of the Microprocessor Interface Signals, during an Intel-type Programmed I/O Write
Operation ............................................................................................................................................... 51
Figure 27. Illustration of the Behavior of Microprocessor Interface signals, during a Motorola-type Pro-
grammed I/O Read Operation ............................................................................................................... 52
Figure 28. Illustration of the Behavior of the Microprocessor Interface signal, during a Motorola-type Pro-
grammed I/O Write Operation ............................................................................................................... 53
Figure 29. Behavior of the Microprocessor Interface Signals, during the Initial Read Operation of a Burst
Cycle (Intel Type Processor) ................................................................................................................. 54
Figure 30. Behavior of the Microprocessor Interface Signals, during subsequent Read Operations within
the Burst I/O Cycle ................................................................................................................................ 55
Figure 31. Behavior of the Microprocessor Interface signals, during the Initial Write Operation of a Burst
Cycle (Intel-type Processor) .................................................................................................................. 57
Figure 32. Behavior of the Microprocessor Interface Signals, during subsequent Write Operations within
the Burst I/O Cycle ................................................................................................................................ 58
Figure 33. Behavior of the Microprocessor Interface Signals, during the Initial Read Operation of a Burst
Cycle (Motorola Type Processor) .......................................................................................................... 59
Figure 34. Behavior the Microprocessor Interface Signals, during subsequent Read Operations within the
Burst I/O Cycle (Motorola-type �C/�P) .................................................................................................. 60
Figure 35. Behavior of the Microprocessor Interface signals, during the Initial Write Operation of a Burst
Cycle (Motorola-type Processor) ........................................................................................................... 61
Figure 36. Behavior of the Microprocessor Interface Signals, during subsequent Write Operations with the
Burst I/O Cycle (Motorola-type �C/�P) .................................................................................................. 62

2.4 O

N

-C

HIP

R

EGISTER

O

RGANIZATION

...................................................................................................................... 62

2.4.1 Framer Register Addressing .................................................................................................................... 62

T

ABLE

5: R

EGISTER

A

DDRESSING

OF

THE

F

RAMER

P

ROGRAMMER

R

EGISTERS

......................................... 63

2.4.2 Framer Register Description .................................................................................................................... 66

P

ART

N

UMBER

R

EGISTER

(A

DDRESS

= 0

X

02) .......................................................................................... 69

V

ERSION

N

UMBER

R

EGISTER

(A

DDRESS

= 0

X

03) ..................................................................................... 69

B

LOCK

I

NTERRUPT

E

NABLE

R

EGISTER

(A

DDRESS

= 0

X

04) ........................................................................ 69

B

LOCK

I

NTERRUPT

S

TATUS

R

EGISTER

(A

DDRESS

= 0

X

05) ........................................................................ 70

TEST R

EGISTER

(A

DDRESS

= 0

X

0C) ....................................................................................................... 71

R

X

DS3 C

ONFIGURATION

& S

TATUS

R

EGISTER

(A

DDRESS

= 0

X

10) ........................................................... 72

R

X

DS3 S

TATUS

R

EGISTER

(A

DDRESS

= 0

X

11) ........................................................................................ 73

R

X

DS3 I

NTERRUPT

E

NABLE

R

EGISTER

(A

DDRESS

= 0

X

12) ....................................................................... 74

R

X

DS3 I

NTERRUPT

S

TATUS

R

EGISTER

(A

DDRESS

= 0

X

13) ....................................................................... 75

R

X

DS3 SYNC D

ETECT

E

NABLE

R

EGISTER

(A

DDRESS

= 0

X

14) ................................................................ 77

R

X

DS3 FEAC I

NTERRUPT

E

NABLE

/S

TATUS

R

EGISTER

(A

DDRESS

= 0

X

17) ............................................... 77

R

X

DS3 LAPD C

ONTROL

R

EGISTER

(A

DDRESS

= 0

X

18) ........................................................................... 78

R

X

DS3 LAPD S

TATUS

R

EGISTER

(A

DDRESS

= 0

X

19) .............................................................................. 79

2.4.3 Receive E3 Framer Configuration Registers (ITU-T G.832) .................................................................... 79

R

X

E3 C

ONFIGURATION

& S

TATUS

R

EGISTER

1 (A

DDRESS

= 0

X

10) ........................................................... 80

R

X

E3 C

ONFIGURATION

& S

TATUS

R

EGISTER

2 (A

DDRESS

= 0

X

11) ........................................................... 81

R

X

E3 I

NTERRUPT

E

NABLE

R

EGISTER

- 1 (A

DDRESS

= 0

X

12) .................................................................... 82

R

X

E3 I

NTERRUPT

E

NABLE

R

EGISTER

- 2 (A

DDRESS

= 0

X

13) .................................................................... 83

R

X

E3 I

NTERRUPT

S

TATUS

R

EGISTER

- 1 (A

DDRESS

= 0

X

14) .................................................................... 83

R

X

E3 I

NTERRUPT

S

TATUS

R

EGISTER

- 2 (A

DDRESS

= 0

X

15) .................................................................... 85

R

X

E3 LAPD C

ONTROL

R

EGISTER

(A

DDRESS

= 0

X

18) .............................................................................. 86

��

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XRT72L54

FOUR CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

ADVANCED CONFIDENTIAL

REV. P1.1.2

III

R

X

E3 LAPD S

TATUS

R

EGISTER

(A

DDRESS

= 0

X

19) ................................................................................ 86

R

X

E3 NR B

YTE

R

EGISTER

(A

DDRESS

= 0

X

1A) ........................................................................................ 87

R

X

E3 GC B

YTE

R

EGISTER

(A

DDRESS

= 0

X

1B) ....................................................................................... 87

R

X

E3 TTB-0 R

EGISTER

(A

DDRESS

= 0

X

1C) ............................................................................................ 88

R

X

E3 TTB-1 R

EGISTER

(A

DDRESS

= 0

X

1D) ............................................................................................ 88

R

X

E3 TTB-2 R

EGISTER

(A

DDRESS

= 0

X

1E) ............................................................................................ 88

R

X

E3 TTB-3 R

EGISTER

(A

DDRESS

= 0

X

1F) ............................................................................................ 89

R

X

E3 TTB-4 R

EGISTER

(A

DDRESS

= 0

X

20) ............................................................................................ 89

R

X

E3 TTB-5 R

EGISTER

(A

DDRESS

= 0

X

21) ............................................................................................ 89

R

X

E3 TTB-6 R

EGISTER

(A

DDRESS

= 0

X

22) ............................................................................................ 89

R

X

E3 TTB-7 R

EGISTER

(A

DDRESS

= 0

X

23) ............................................................................................ 90

R

X

E3 TTB-8 R

EGISTER

(A

DDRESS

= 0

X

24) ............................................................................................ 90

R

X

E3 TTB-9 R

EGISTER

(A

DDRESS

= 0

X

25) ............................................................................................ 90

R

X

E3 TTB-10 R

EGISTER

(A

DDRESS

= 0

X

26) .......................................................................................... 91

R

X

E3 TTB-11 R

EGISTER

(A

DDRESS

= 0

X

27) .......................................................................................... 91

R

X

E3 TTB-12 R

EGISTER

(A

DDRESS

= 0

X

28) .......................................................................................... 91

R

X

E3 TTB-13 R

EGISTER

(A

DDRESS

= 0

X

29 ........................................................................................... 91

R

X

E3 TTB-14 R

EGISTER

(A

DDRESS

= 0

X

2A) .......................................................................................... 92

R

X

E3 TTB-15 R

EGISTER

(A

DDRESS

= 0

X

2B) .......................................................................................... 92

R

X

E3

SSM

R

EGISTER

(A

DDRESS

= 0

X

2B) ................................................................................................ 92

2.4.4 Receive E3 Framer Configuration Registers (ITU-T G.751) ................................................................... 93

R

X

E3 C

ONFIGURATION

& S

TATUS

R

EGISTER

- 1 G.751 (A

DDRESS

= 0

X

10) ............................................. 93

R

X

E3 C

ONFIGURATION

& S

TATUS

R

EGISTER

- 2 (A

DDRESS

= 0

X

11) ........................................................ 93

R

X

E3 I

NTERRUPT

E

NABLE

R

EGISTER

- 1 (A

DDRESS

= 0

X

12) ................................................................... 94

R

X

E3 I

NTERRUPT

E

NABLE

R

EGISTER

- 2 (A

DDRESS

= 0

X

13) ................................................................... 95

R

X

E3 I

NTERRUPT

S

TATUS

R

EGISTER

- 1 (A

DDRESS

= 0

X

14) ................................................................... 95

R

X

E3 I

NTERRUPT

S

TATUS

R

EGISTER

- 2 (A

DDRESS

= 0

X

15) ................................................................... 96

R

X

E3 LAPD C

ONTROL

R

EGISTER

(A

DDRESS

= 0

X

18) ............................................................................. 97

R

X

E3 LAPD S

TATUS

R

EGISTER

(A

DDRESS

= 0

X

19) ................................................................................ 97

R

X

E3 S

ERVICE

B

IT

R

EGISTER

(A

DDRESS

= 0

X

1A) ................................................................................... 98

2.4.5 Transmit DS3 Configuration Registers .................................................................................................... 98

T

RANSMIT

DS3 C

ONFIGURATION

R

EGISTER

(A

DDRESS

= 0

X

30) ............................................................... 99

T

RANSMIT

DS3 FEAC C

ONFIGURATION

& S

TATUS

R

EGISTER

(A

DDRESS

= 0

X

31) .................................. 100

T

X

DS3 FEAC R

EGIS

T

ER

(A

DDRESS

= 0

X

32) ........................................................................................ 101

T

X

DS3 LAPD C

ONFIGURATION

R

EGISTER

(A

DDRESS

= 0

X

33) ............................................................... 101

T

X

DS3 LAPD S

TATUS

AND

I

NTERRUPT

R

EGISTER

(A

DDRESS

= 0

X

34) ................................................... 102

T

X

DS3 M-B

IT

M

ASK

R

EGISTER

(A

DDRESS

= 0

X

35) ............................................................................... 102

T

X

DS3 F-B

IT

M

ASK

R

EGISTER

- 1 (A

DDRESS

= 0

X

36) ........................................................................... 103

T

X

DS3 F-B

IT

M

ASK

R

EGISTER

- 2 (A

DDRESS

= 0

X

37) ........................................................................... 104

T

X

DS3 F-B

IT

M

ASK

R

EGISTER

- 3 (A

DDRESS

= 0

X

38) ........................................................................... 104

T

X

DS3 F-B

IT

M

ASK

R

EGISTER

- 4 (A

DDRESS

= 0

X

39) ........................................................................... 104

2.4.6 Transmit E3 (ITU-T G.832) Configuration Registers ............................................................................. 104

T

X

E3 C

ONFIGURATION

R

EGISTER

(A

DDRESS

= 0

X

30) ............................................................................ 105

T

X

E3 LAPD C

ONFIGURATION

R

EGISTER

(A

DDRESS

= 0

X

33) ................................................................. 106

T

X

E3 LAPD S

TATUS

AND

I

NTERRUPT

R

EGISTER

(A

DDRESS

= 0

X

34) ...................................................... 106

T

X

E3 GC B

YTE

R

EGISTER

(A

DDRESS

= 0

X

35) ...................................................................................... 107

T

X

E3 MA B

YTE

R

EGISTER

(A

DDRESS

= 0

X

36) ...................................................................................... 108

T

X

E3 MA B

YTE

R

EGISTER

(A

DDRESS

= 0

X

36) ...................................................................................... 108

T

X

E3 NR B

YTE

R

EGISTER

(A

DDRESS

= 0

X

37) ...................................................................................... 108

T

X

E3 TTB-0 R

EGISTER

(A

DDRESS

= 0

X

38) ........................................................................................... 109

T

X

E3 TTB-1 R

EGISTER

(A

DDRESS

= 0

X

39) ........................................................................................... 109

T

X

E3 TTB-2 R

EGISTER

(A

DDRESS

= 0

X

3A) .......................................................................................... 109

T

X

E3 TTB-3 R

EGISTER

(A

DDRESS

= 0

X

3B) .......................................................................................... 110

T

X

E3 TTB-4 R

EGISTER

(A

DDRESS

= 0

X

3C) .......................................................................................... 110

T

X

E3 TTB-5 R

EGISTER

(A

DDRESS

= 0

X

3D) .......................................................................................... 111

Document Outline

• GENERAL DESCRIPTION
  • features
  • applications
    • Figure 1. Block Diagram of the XRT72L54
    • Figure 2. Pin Out ofthe XRT72L54
• Ordering Information
• Electrical Characteristics
  • Absolute Maximums
  • DC Electrical Characteristics
  • AC Electrical Characteristics
  • AC Electrical Characteristics (Cont.)
• 1.0 Timing Diagrams
  • Figure 3. Timing Diagram for Transmit Payload Input Interface, when the XRT72L54 Device is operat...
  • Figure 4. Timing Diagram for the Transmit Payload Input Interface, when the XRT72L54 Device is op...
  • Figure 5. Timing Diagram for the Transmit Payload Data Input Interface, when the XRT72L54 Device ...
  • Figure 6. Timing Diagram for the Transmit Payload Data Input Interface, when the XRT72L54 Device ...
  • Figure 7. Timing Diagram for the Transmit Overhead Data Input Interface (Method 1 Access)
  • Figure 8. Timing Diagram for the Transmit Overhead Data Input Interface (Method 2 Access)
  • Figure 9. Transmit LIU Interface Timing - Framer is configured to update "TxPOS" and "TxNEG" on t...
  • Figure 10. Transmit LIU Interface Timing - Framer is configured to update "TxPOS" and "TxNEG" on ...
  • Figure 11. Receive LIU Interface Timing - Framer is configured to sample "RxPOS" and "RxNEG" on t...
  • Figure 12. Receiver LIU Interface Timing - Framer is configured to sample "RxPOS" and "RxNEG" on ...
  • Figure 13. Receive Payload Data Output Interface Timing
  • Figure 14. Receive Payload Data Output Interface Timing (Nibble Mode Operation)
  • Figure 15. Receive Overhead Data Output Interface Timing (Method 1 - Using RxOHClk)
  • Figure 16. Receive Overhead Data Output Interface Timing (Method 2 - Using RxOHEnable)
  • Figure 17. Microprocessor Interface Timing - Intel Type Programmed I/O Read Operations
  • Figure 18. Microprocessor Interface Timing - Intel Type Programmed I/O Write Operations
  • Figure 19. Microprocessor Interface Timing - Intel Type Read Burst Access Operation
  • Figure 20. Microprocessor Interface Timing - Intel type Write Burst Access Operation
  • Figure 21. Microprocessor Interface Timing - Motorola Type Programmed I/O Read Operation
  • Figure 22. Microprocessor Interface Timing - Motorola Type Programmed I/O Write Operation
  • Figure 23. Microprocessor Interface Timing - Reset Pulse Width
• 2.0 The Microprocessor Interface Block
  • 2.1 Channel Selection within the XRT72L54 Device
    • Table 1: The Relationship between Address Bits A9, A10 and the Selected Configuration Register Bank
    • Figure 24. Simple Block Diagram of the Microprocessor Interface Block, within the Framer IC
  • 2.2 The Microprocessor Interface Block Signal
    • Table 2: Description of the Microprocessor Interface Signals that exhibit constant roles in both ...
    • Table 3: Pin Description of Microprocessor Interface Signals - While the Microprocessor Interface...
    • Table 4: Pin Description of the Microprocessor Interface Signals while the Microprocessor Interfa...
  • 2.3 Interfacing the XRT72L54 DS3/E3 Framer to the Local �C/�P via the Microprocessor Interface Block
    • 2.3.1 Interfacing the XRT72L54 DS3/E3 Framer to the Microprocessor over an 8 bit wide bi-directio...
    • 2.3.2 Data Access Modes
    • Figure 25. Behavior of Microprocessor Interface signals during an Intel-type Programmed I/O Read ...
    • Figure 26. Behavior of the Microprocessor Interface Signals, during an Intel-type Programmed I/O ...
    • Figure 27. Illustration of the Behavior of Microprocessor Interface signals, during a Motorola- t...
    • Figure 28. Illustration of the Behavior of the Microprocessor Interface signal, during a Motorola...
    • Figure 29. Behavior of the Microprocessor Interface Signals, during the Initial Read Operation of...
    • Figure 30. Behavior of the Microprocessor Interface Signals, during subsequent Read Operations wi...
    • Figure 31. Behavior of the Microprocessor Interface signals, during the Initial Write Operation o...
    • Figure 32. Behavior of the Microprocessor Interface Signals, during subsequent Write Operations w...
    • Figure 33. Behavior of the Microprocessor Interface Signals, during the Initial Read Operation of...
    • Figure 34. Behavior the Microprocessor Interface Signals, during subsequent Read Operations withi...
    • Figure 35. Behavior of the Microprocessor Interface signals, during the Initial Write Operation o...
    • Figure 36. Behavior of the Microprocessor Interface Signals, during subsequent Write Operations w...
  • 2.4 On-Chip Register Organization
    • 2.4.1 Framer Register Addressing
    • Table 5: Register Addressing of the Framer Programmer Registers
    • 2.4.2 Framer Register Description
  • Part Number Register (Address = 0x02)
  • Version Number Register (Address = 0x03)
  • Block Interrupt Enable Register (Address = 0x04)
  • Block Interrupt Status Register (Address = 0x05)
  • TEST Register (Address = 0x0C)
  • RxDS3 Configuration & Status Register (Address = 0x10)
  • RxDS3 Status Register (Address = 0x11)
  • RxDS3 Interrupt Enable Register (Address = 0x12)
  • RxDS3 Interrupt Status Register (Address = 0x13)
  • RxDS3 SYNC Detect Enable Register (Address = 0x14)
  • RxDS3 FEAC Interrupt Enable/Status Register (Address = 0x17)
  • RxDS3 LAPD Control Register (Address = 0x18)
  • RxDS3 LAPD Status Register (Address = 0x19)
    • 2.4.3 Receive E3 Framer Configuration Registers (ITU-T G.832)
  • RxE3 Configuration & Status Register 1 (Address = 0x10)
  • RxE3 Configuration & Status Register 2 (Address = 0x11)
  • RxE3 Interrupt Enable Register - 1 (Address = 0x12)
  • RxE3 Interrupt Enable Register - 2 (Address = 0x13)
  • RxE3 Interrupt Status Register - 1 (Address = 0x14)
  • RxE3 Interrupt Status Register - 2 (Address = 0x15)
  • RxE3 LAPD Control Register (Address = 0x18)
  • RxE3 LAPD Status Register (Address = 0x19)
  • RxE3 NR Byte Register (Address = 0x1A)
  • RxE3 GC Byte Register (Address = 0x1B)
  • RxE3 TTB-0 Register (Address = 0x1C)
  • RxE3 TTB-1 Register (Address = 0x1D)
  • RxE3 TTB-2 Register (Address = 0x1E)
  • RxE3 TTB-3 Register (Address = 0x1F)
  • RxE3 TTB-4 Register (Address = 0x20)
  • RxE3 TTB-5 Register (Address = 0x21)
  • RxE3 TTB-6 Register (Address = 0x22)
  • RxE3 TTB-7 Register (Address = 0x23)
  • RxE3 TTB-8 Register (Address = 0x24)
  • RxE3 TTB-9 Register (Address = 0x25)
  • RxE3 TTB-10 Register (Address = 0x26)
  • RxE3 TTB-11 Register (Address = 0x27)
  • RxE3 TTB-12 Register (Address = 0x28)
  • RxE3 TTB-13 Register (Address = 0x29
  • RxE3 TTB-14 Register (Address = 0x2A)
  • RxE3 TTB-15 Register (Address = 0x2B)
  • RxE3 ssm Register (Address = 0x2B)
    • 2.4.4 Receive E3 Framer Configuration Registers (ITU-T G.751)
  • RxE3 Configuration & Status Register - 1 G.751 (Address = 0x10)
  • RxE3 Configuration & Status Register - 2 (Address = 0x11)
  • RxE3 Interrupt Enable Register - 1 (Address = 0x12)
  • RxE3 Interrupt Enable Register - 2 (Address = 0x13)
  • RxE3 Interrupt Status Register - 1 (Address = 0x14)
  • RxE3 Interrupt Status Register - 2 (Address = 0x15)
  • RxE3 LAPD Control Register (Address = 0x18)
  • RxE3 LAPD Status Register (Address = 0x19)
  • RxE3 Service Bit Register (Address = 0x1A)
    • 2.4.5 Transmit DS3 Configuration Registers
  • Transmit DS3 Configuration Register (Address = 0x30)
  • Transmit DS3 FEAC Configuration & Status Register (Address = 0x31)
  • TxDS3 FEAC RegisTer (Address = 0x32)
  • TxDS3 LAPD Configuration Register (Address = 0x33)
  • TxDS3 LAPD Status and Interrupt Register (Address = 0x34)
  • TxDS3 M-Bit Mask Register (Address = 0x35)
  • TxDS3 F-Bit Mask Register - 1 (Address = 0x36)
  • TxDS3 F-Bit Mask Register - 2 (Address = 0x37)
  • TxDS3 F-Bit Mask Register - 3 (Address = 0x38)
  • TxDS3 F-Bit Mask Register - 4 (Address = 0x39)
    • 2.4.6 Transmit E3 (ITU-T G.832) Configuration Registers
  • TxE3 Configuration Register (Address = 0x30)
  • TxE3 LAPD Configuration Register (Address = 0x33)
  • TxE3 LAPD Status and Interrupt Register (Address = 0x34)
  • TxE3 GC Byte Register (Address = 0x35)
  • TxE3 MA Byte Register (Address = 0x36)
  • TxE3 MA Byte Register (Address = 0x36)
  • TxE3 NR Byte Register (Address = 0x37)
  • TxE3 TTB-0 Register (Address = 0x38)
  • TxE3 TTB-1 Register (Address = 0x39)
  • TxE3 TTB-2 Register (Address = 0x3A)
  • TxE3 TTB-3 Register (Address = 0x3B)
  • TxE3 TTB-4 Register (Address = 0x3C)
  • TxE3 TTB-5 Register (Address = 0x3D)
  • TxE3 TTB-6 Register (Address = 0x3E)
  • TxE3 TTB-7 Register (Address = 0x3F)
  • TxE3 TTB-8 Register (Address = 0x40)
  • TxE3 TTB-9 Register (Address = 0x41)
  • TxE3 TTB-10 Register (Address = 0x42)
  • TxE3 TTB-11 Register (Address = 0x43)
  • TxE3 TTB-12 Register (Address = 0x44)
  • TxE3 TTB-13 Register (Address = 0x45)
  • TxE3 TTB-14 Register (Address = 0x46)
  • TxE3 TTB-15 Register (Address = 0x47)
  • TxE3 FA1 Error Mask Register (Address = 0x48)
  • TxE3 FA2 Error Mask Register (Address = 0x49)
  • TxE3 BIP-8 Error Mask Register (Address = 0x4A)
    • 2.4.7 Transmit E3 Framer Configuration Registers (ITU-T G.751)
  • TxE3 Configuration Register (Address = 0x30)
  • TxE3 LAPD Configuration Register (Address = 0x33)
  • TxE3 LAPD Status and Interrupt Register (Address = 0x34)
  • TxE3 Service Bits Register (Address = 0x35)
  • TxE3 FAS Error Mask Register - 0 (Address = 0x48)
  • TxE3 FAS Error Mask Register - 1 (Address = 0x49)
  • TxE3 BIP-4 Error Mask Register (Address = 0x4A)
    • 2.4.8 Performance Monitor Registers
  • PMON LCV Event Count Register - LSB (Address = 0x51)
  • PMON Framing Bit/Byte Error Count Register - MSB (Address = 0x52)
  • PMON Framing Bit/Byte Error Count Register - LSB (Address = 0x53)
  • PMON Parity Error Count Register - MSB (Address = 0x54)
  • PMON Parity Error Count Register - LSB (Address = 0x55)
  • PMON FEBE Event Count Register - MSB (Address = 0x56)
  • PMON FEBE Event Count Register - LSB (Address = 0x57)
  • PMON CP-Bit Error Count Register - MSB (Address = 0x58)
  • PMON CP-Bit Error Count Register - LSB (Address = 0x59)
  • PMON Holding Register (Address = 0x6C)
  • One-Second Error Status Register (Address = 0x6D)
  • LCV - One-Second Accumulator Register - MSB (Address = 0x6E)
  • LCV - One-Second Accumulator Register - LSB (Address = 0x6F)
  • Frame Parity Errors - One-Second Accumulator Register - MSB (Address = 0x70)
  • Frame Parity Errors - One-Second Accumulator Register - LSB (Address = 0x71)
  • Frame CP-Bit Errors - One-Second Accumulator Register - MSB (Address = 0x72)
  • Frame Parity Errors - One-Second Accumulator Register - LSB (Address = 0x73)
  • Line Interface Drive Register (Address = 0x80)
  • Line Interface Scan Register (Address = 0x81)
  • HDLC Control Register (Address = 0x82)
  • 2.5 The Loss of Clock Enable Feature
  • Address = 0x01, Framer I/O Control Register
  • 2.6 Using the PMON Holding Register
  • 2.7 The Interrupt Structure within the Framer Microprocessor Interface Section
    • Table 6: List of all of the Possible Conditions that can Generate Interrupts within each channel ...
    • Table 7: A Listing of the XRT72L54 Framer Device Interrupt Block Registers (for DS3 Applications)
    • Table 8: A Listing of the XRT72L54 Framer Device Interrupt Block Registers (for E3, ITU-T G.832 A...
    • Table 9: A Listing of the XRT72L54 Framer Device Interrupt Block Register (for E3, ITU-T G.751 Ap...
  • Block Interrupt Status Register (Address = 0x05)
  • Block Interrupt Enable Register (Address = 0x04)
    • Table 10: Interrupt Service Routine Guide (for DS3 Applications)
    • Table 11: Interrupt Service Routine Guide (for E3, ITU-T G.832 Applications)
    • Table 12: Interrupt Service Routine Guide (for E3, ITU-T G.751 Applications)
    • 2.7.1 Automatic Reset of Interrupt Enable Bits
  • framer operating mode Register (Address = 0x00)
    • 2.7.2 One-Second Interrupts
  • 2.8 Interfacing the framer to an intel-type microprocessor
    • Table 13: Alternate Functions of Port 3 Pins
    • Table 14: Interrupt Service Routine Location (in Code Memory) for the INT0* and INT1* Interrupt I...
    • Figure 37. Schematic depicting how to interface the XRT72L54 DS3/E3 Framer IC to the 8051 Microco...
  • 2.9 Interfacing the Framer IC to a Motorola- type Microprocessor
    • Figure 38. Schematic Depicting how to interface the XRT72L54 DS3/E3 Framer IC to the MC68000 Micr...
    • Table 15: Auto-Vector Table for the MC68000 Microprocessor
• 3.0 The Line Interface and scan section
  • Figure 39. Schematic Depicting how to interface the XRT72L54 DS3/E3 Framer IC to the XRT73L04 DS3...
  • 3.1 Bit-Fields within the Line Interface Drive Register
  • LINE INTERFACE DRIVE Register (Address = 0x80)
    • Table 16: The Relationship between the states of RLOOP, LLOOP and the resulting loop-back mode wi...
  • 3.2 Bit-Fields within the Line Interface Scan Register
  • LINE INTERFACE sCAN Register (Address = 0x81)
• XRT72L54 Configuration
• 4.0 DS3 Operation of the XRT72L54
  • Framer Operating Mode Register (Address = 0x00)
  • 4.1 Description of the DS3 Frames and Associated Overhead Bits
    • Figure 40. DS3 Frame Format for C-bit Parity
    • Figure 41. DS3 Frame Format for M13
  • Framer Operating Mode Register (Address = 0x00)
    • Table 17: The Relationship between the content of Bit 2, (C-Bit Parity*/M13) within the Framer Op...
    • Table 18: C-bit Functions for the C-bit Parity DS3 Frame Format
    • 4.1.1 Frame Synchronization Bits (Applies to both M13 and C-bit Parity Framing Formats)
    • 4.1.2 Performance Monitoring/Error Detection Bits (Parity)
    • 4.1.3 Alarm and Signaling-Related Overhead Bits
    • Valid M-bits, F-bits, and P-bits
    • 4.1.4 The Data Link Related Overhead Bits
  • 4.2 The Transmit Section of the XRT72L54 (DS3 Mode Operation)
    • Figure 42. A Simple Illustration of the Transmit Section, within the XRT72L54, when it has been c...
    • 4.2.1 The Transmit Payload Data Input Interface Block
    • Figure 43. A Simple Illustration of the Transmit Payload Data Input Interface Block
    • Table 19: Listing and Description of the pins associated with the Transmit Payload Data Input Int...
    • Figure 44. Illustration of the Terminal Equipment being interfaced to the Transmit Payload Data I...
    • Figure 45. Behavior of the Terminal Interface signals between the Transmit Payload Data Input Int...
  • Framer Operating Mode Register (Address = 0x00)
    • Figure 46. Illustration of the Terminal Equipment being interfaced to the Transmit Payload Data I...
    • Figure 47. Behavior of the Terminal Interface signals between the XRT72L54 and the Terminal Equip...
  • Framer Operating Mode Register (Address = 0x00)
    • Figure 48. Illustration of the Terminal Equipment being interfaced to the Transmit Payload Data I...
    • Figure 49. Behavior of the Terminal Interface signals between the XRT72L54 and the Terminal Equip...
  • Framer Operating Mode Register (Address = 0x00)
    • Figure 50. Illustration of the Terminal Equipment being interfaced to the Transmit Payload Data I...
    • Figure 51. Behavior of the Terminal Interface signals between the XRT72L54 and the Terminal Equip...
  • Framer Operating Mode Register (Address = 0x00)
    • Figure 52. Illustration of the Terminal Equipment being interfaced to the Transmit Payload Data I...
    • Figure 53. Behavior of the Terminal Interface signals between the XRT72L54 and the Terminal Equip...
  • Framer Operating Mode Register (Address = 0x00)
    • Figure 54. Illustration of the Terminal Equipment being interfaced to the Transmit Payload Data I...
    • Figure 55. Behavior of the Terminal Interface signals between the XRT72L54 and the Terminal Equip...
  • Framer Operating Mode Register (Address = 0x00)
    • 4.2.2 The Transmit Overhead Data Input Interface
    • Figure 56. Simple Illustration of the Transmit Overhead Data Input Interface block
    • Table 20: A Listing of the Overhead bits within the DS3 frame, and their potential sources, withi...
    • Table 21: Description of Method 1 Transmit Overhead Input Interface Signals
    • Figure 57. Illustration of the Terminal Equipment being interfaced to the Transmit Overhead Data ...
    • Table 22: The Relationship between the Number of Rising Clock Edges in TxOHClk, (since TxOHFrame ...
    • Figure 58. Illustration of the signal that must occur between the Terminal Equipment and the XRT7...
    • Table 23: Description of Method 2 Transmit Overhead Input Interface Signals
    • Figure 59. Illustration of the Terminal Equipment being interfaced to the Transmit Overhead Data ...
    • Table 24: The Relationship between the Number of TxOHEnable pulses (since the last occurrence of ...
    • Figure 60. Behavior of Transmit Overhead Data Input Interface signals between the XRT72L54 and th...
    • 4.2.3 The Transmit DS3 HDLC Controller
  • Tx DS3 FEAC Register (Address = 0x32)
  • Transmit DS3 FEAC Configuration and Status Register (Address = 0x31)
  • Transmit DS3 FEAC Configuration and Status Register (Address = 0x31)
    • Figure 61. A Flow Chart depicting how to transmit a FEAC Message via the FEAC Transmitter
    • Figure 62. LAPD Message Frame Format
    • Table 25: The LAPD Message Type and the Corresponding value of the First Byte, within the Informa...
  • Transmit DS3 LAPD Configuration Register (Address = 0x33)
    • Table 26: Relationship between TxLAPD Msg Length and the LAPD Message Size
  • Transmit DS3 LAPD Configuration Register (Address = 0x33)
    • Table 27: Relationship between TxLAPD Msg Length and the LAPD Message Size
  • Transmit DS3 LAPD Status/Interrupt Register (Address = 0x34)
    • Figure 63. Flow Chart depict how to use the LAPD Transmitter
  • Framer Operating Mode Register (Address = 0x00)
  • Block Interrupt Enable Register (Address = 0x04)
    • 4.2.4 The Transmit DS3 Framer Block
    • Figure 64. A Simple Illustration of the Transmit DS3 Framer Block and the associated paths to oth...
  • Tx DS3 Configuration Register (Address = 0x30)
    • Table 28: The Relationship between the contents of Bit 7 (Tx Yellow Alarm) within the Tx DS3 Conf...
    • Table 29: The Relationship between the contents of Bit 6 (Tx X-Bits) within the Tx DS3 Configurat...
    • Table 30: The Relationship between the contents of Bit 5 (Tx Idle) within the Tx DS3 Configuratio...
    • Table 31: The Relationship between the contents of Bit 4 (Tx AIS Pattern) within the Tx DS3 Confi...
    • Table 32: The Relationship between the contents of Bit 3 (Tx LOS) within the Tx DS3 Configuration...
  • Tx DS3 M-Bit Mask Register, Address = 0x35
  • Tx DS3 F-Bit Mask1 Register, Address = 0x36
  • Tx DS3 F-Bit Mask2 Register, Address = 0x37
  • Tx DS3 F-Bit Mask3 Register, Address = 0x38
  • Tx DS3 F-Bit Mask4 Register, Address = 0x39
    • 4.2.5 The Transmit DS3 Line Interface Block
    • Figure 65. Approach to Interfacing the XRT72L54 Framer IC to the XRT73L04 DS3/E3/STS-1 Transmitte...
    • Figure 66. A Simple Illustration of the Transmit DS3 LIU Interface block
    • Figure 67. The Behavior of TxPOS and TxNEG signals during data transmission while the Transmit DS...
  • I/O Control Register (Address = 0x01)
    • Table 33: The Relationship between the content of Bit 3 (Unipolar/Bipolar*) within the UNI I/O Co...
    • Figure 68. Illustration of AMI Line Code
    • Figure 69. Illustration of two examples of B3ZS Encoding
  • I/O Control Register (Address = 0x01)
    • Table 34: The Relationship between Bit 4 (AMI/B3ZS*) within the I/O Control Register and the Bipo...
  • II/O Control Register (Address = 0x01)
    • Table 35: The Relationship between the contents of Bit 2 (TxLineClk Inv) within the I/O Control R...
    • Figure 70. Waveform/Timing Relationship between TxLineClk, TxPOS and TxNEG - TxPOS and TxNEG are ...
    • Figure 71. Waveform/Timing Relationship between TxLineClk, TxPOS and TxNEG - TxPOS and TxNEG are ...
    • 4.2.6 Transmit Section Interrupt Processing
  • Block Interrupt Enable Register (Address = 0x04)
  • Transmit DS3 FEAC Configuration & Status Register (Address = 0x31)
  • Transmit DS3 FEAC Configuration & Status Register (Address = 0x31)
  • TxDS3 LAPD Status and Interrupt Register (Address = 0x34)
  • TxDS3 LAPD Status and Interrupt Register (Address = 0x34)
  • 4.3 The Receive Section of the XRT72L54 (DS3 Mode Operation)
    • Figure 72. A Simple Illustration of the Receive Section of the XRT72L54, when it has been configu...
    • 4.3.1 The Receive DS3 LIU Interface Block
    • Figure 73. A Simple Illustration of the Receive DS3 LIU Interface Block
    • Figure 74. Behavior of the RxPOS, RxNEG and RxLineClk signals during data reception of Unipolar Data
  • II/O Control Register (Address = 0x01)
    • Table 36: The Relationship between the contents of Bit 2 (TxLineClk Inv) within the I/O Control R...
    • Figure 75. Illustration on how the Receive DS3 Framer (within the XRT72L54 Framer IC) being inter...
    • Figure 76. Illustration of AMI Line Code
    • Figure 77. Illustration of two examples of B3ZS Decoding
  • II/O Control Register (Address = 0x01)
    • Table 37: The Relationship between the contents of Bit 1 (RxLineClk Inv) of the I/O Control Regis...
    • Figure 78. Waveform/Timing Relationship between RxLineClk, RxPOS and RxNEG - When RxPOS and RxNEG...
    • Figure 79. Waveform/Timing Relationship between RxLineClk, RxPOS and RxNEG - When RxPOS and RxNEG...
    • 4.3.2 The Receive DS3 Framer Block
    • Figure 80. A Simple Illustration of the Receive DS3 Framer Block and the Associated Paths to the ...
    • Figure 81. The State Machine Diagram for the Receive DS3 Framer block's Frame Acquisition/Mainten...
  • Rx DS3 Configuration and Status Register, (Address = 0x10)
    • Table 38: The Relationship between the contents of Bit 2 (Framing on Parity) within the Rx DS3 Co...
  • Rx DS3 Configuration and Status Register, (Address = 0x10)
    • Table 39: The Relationship between the contents of Bit 1 (F-Sync Algo) within the Rx DS3 Configur...
  • Rx DS3 Configuration and Status Register, (Address = 0x10)
    • Table 40: The Relationship between the contents of Bit 0 (M-Sync Algo) within the Rx DS3 Configur...
  • Rx DS3 Configuration and Status Register, (Address = 0x10)
  • I/O Control Register (Address = 0x01)
  • PMON Framing Bit Error Event Count Register - MSB (Address = 0x52)
  • PMON Framing Bit Error Event Count Register - LSB (Address = 0x53)
  • Rx DS3 Configuration and Status Register, (Address = 0x10)
  • Rx DS3 Configuration and Status Register, (Address = 0x10)
  • Rx DS3 Configuration and Status Register, (Address = 0x10)
  • Rx DS3 Configuration and Status Register, (Address = 0x10)
  • Rx DS3 Configuration and Status Register, (Address = 0x10)
  • Rx DS3 Status Register (Address = 0x11)
  • Rx DS3 Interrupt Status Register (Address = 0x13)
  • RxDS3 Status Register (Address = 0x11)
  • RxDS3 Interrupt Status Register (Address = 0x13)
  • PMON Parity Error Event Count Register - MSB (Address = 0x54)
  • PMON Parity Error Event Count Register - LSB (Address = 0x55)
    • Figure 82. A Simple Illustration of the Locations of the Source, Mid-Network and Sink Terminal Eq...
    • Figure 83. Illustration of the Presumed Configuration of the Mid-Network Terminal Equipment
    • 4.3.3 The Receive HDLC Controller Block
  • Rx DS3 FEAC Interrupt Enable/Status Register (Address = 0x17)
  • Rx DS3 FEAC Register (Address = 0x16)
  • Rx DS3 FEAC Interrupt Enable/Status Register (Address = 0x17)
    • Figure 84. Flow Diagram depicting how the Receive FEAC Processor Functions
    • Figure 85. LAPD Message Frame Format
  • Rx DS3 LAPD Control Register (Address = 0x18)
  • Rx DS3 LAPD Status Register (Address = 0x19)
    • Table 41: The Relationship between RxLAPDType[1:0] and the resulting LAPD Message type and size
    • Figure 86. Flow Chart depicting the Functionality of the LAPD Receiver
    • 4.3.4 The Receive Overhead Data Output Interface
    • Figure 87. A Simple Illustration of the Receive Overhead Output Interface block
    • Table 42: Listing and Description of the Pin Associated with the Receive Overhead Data Output Int...
    • Figure 88. Illustration of how to interface the Terminal Equipment to the Receive Overhead Data O...
    • Table 43: The Relationship between the Number of Rising Clock Edges in RxOHClk, (since RxOHFrame ...
    • Figure 89. Illustration of the signals that are output via the Receive Overhead Output Interface ...
    • Table 44: Listing and Description of the Pin Associated with the Receive Overhead Data Output Int...
    • Figure 90. Illustration of how to interface the Terminal Equipment to the Receive Overhead Data O...
    • Table 45: The Relationship between the Number of RxOHEnable output pulses ((since RxOHFrame was l...
    • Figure 91. Illustration of the signals that are output via the Receive Overhead Data Output Inter...
    • 4.3.5 The Receive Payload Data Output Interface
    • Figure 92. A Simple illustration of the Receive Payload Data Output Interface block
    • Table 46: Listing and Description of the pin associated with the Receive Payload Data Output Inte...
    • Figure 93. Illustration of the XRT72L54 DS3/E3 Framer IC being interfaced to the Receive Terminal...
    • Figure 94. An Illustration of the behavior of the signals between the Receive Payload Data Output...
    • Figure 95. Illustration of the XRT72L54 DS3/E3 Framer IC being interfaced to the Receive Section ...
    • Figure 96. An Illustration of the Behavior of the signals between the Receive Payload Data Output...
    • 4.3.6 Receive Section Interrupt Processing
  • Block Interrupt Enable Register (Address = 0x04)
  • RxDS3 Interrupt Enable Register (Address = 0x12)
  • RxDS3 Interrupt Status Register (Address = 0x13)
  • RxDS3 Configuration & Status Register (Address = 0x10)
  • RxDS3 Interrupt Enable Register (Address = 0x12)
  • RxDS3 Interrupt Status Register (Address = 0x13)
  • RxDS3 Configuration & Status Register (Address = 0x10)
  • RxDS3 Interrupt Enable Register (Address = 0x12)
  • RxDS3 Interrupt Status Register (Address = 0x13)
  • RxDS3 Configuration & Status Register (Address = 0x10)
  • RxDS3 Interrupt Enable Register (Address = 0x12)
  • RxDS3 Interrupt Status Register (Address = 0x13)
  • RxDS3 Configuration & Status Register (Address = 0x10)
  • RxDS3 Interrupt Enable Register (Address = 0x12)
  • RxDS3 Interrupt Status Register (Address = 0x13)
  • RxDS3 Status Register (Address = 0x11)
  • RxDS3 Interrupt Enable Register (Address = 0x12)
  • RxDS3 Interrupt Status Register (Address = 0x13)
  • RxDS3 Interrupt Enable Register (Address = 0x12)
  • RxDS3 Interrupt Status Register (Address = 0x13)
  • RxDS3 Interrupt Enable Register (Address = 0x12)
  • RxDS3 Interrupt Status Register (Address = 0x13)
  • RxDS3 FEAC Interrupt Enable/Status Register (Address = 0x17)
  • RxDS3 FEAC Interrupt Enable/Status Register (Address = 0x17)
  • RxDS3 FEAC Interrupt Enable/Status Register (Address = 0x17)
  • RxDS3 FEAC Interrupt Enable/Status Register (Address = 0x17)
  • RxDS3 LAPD Control Register (Address = 0x18)
  • RxDS3 LAPD Control Register (Address = 0x18)
• 5.0 E3/ITU-T G.751 Operation of the XRT72L54
  • Framer Operating Mode Register (Address = 0x00)
  • 5.1 Description of the E3, ITU-T G.751 Frames and Associated Overhead Bits
    • Figure 97. Illustration of the E3, ITU-T G.751 Framing Format.
    • 5.1.1 Definition of the Overhead Bits
  • 5.2 The Transmit Section of the XRT72L54 (E3, ITU-T G.751 Mode Operation)
    • Figure 98. A Simple Illustration of the XRT72L54 Transmit Section when it has been configured to ...
    • 5.2.1 The Transmit Payload Data Input Interface Block
    • Figure 99. A Simple Illustration of the Transmit Payload Data Input Interface Block
    • Table 47: Listing and Description of the pins associated with the Transmit Payload Data Input Int...
    • Figure 100. Illustration of the Terminal Equipment being interfaced to the Transmit Payload Data ...
  • TxE3 Configuration Register (Address = 0x30)
    • Figure 101. Behavior of the Terminal Interface signals between the XRT72L54 Transmit Payload Data...
  • Framer Operating Mode Register (Address = 0x00)
    • Figure 102. Illustration of the Terminal Equipment being interfaced to the Transmit Payload Data ...
    • Figure 103. Behavior of the Terminal Interface signals between the XRT72L54 and the Terminal Equi...
  • Framer Operating Mode Register (Address = 0x00)
    • Figure 104. Illustration of the Terminal Equipment being interfaced to the Transmit Payload Data ...
    • Figure 105. Behavior of the Terminal Interface signals between the XRT72L54 and the Terminal Equi...
  • Framer Operating Mode Register (Address = 0x00)
    • Figure 106. Illustration of the Terminal Equipment being interfaced to the Transmit Payload Data ...
    • Figure 107. Behavior of the Terminal Interface signals between the XRT72L54 and the Terminal Equi...
  • Framer Operating Mode Register (Address = 0x00)
    • Figure 108. Illustration of the Terminal Equipment being interfaced to the Transmit Payload Data ...
    • Figure 109. Behavior of the Terminal Interface signals between the XRT72L54 and the Terminal Equi...
  • Framer Operating Mode Register (Address = 0x00)
    • Figure 110. Illustration of the Terminal Equipment being interfaced to the Transmit Payload Data ...
    • Figure 111. Behavior of the Terminal Interface signals between the XRT72L54 and the Terminal Equi...
  • Framer Operating Mode Register (Address = 0x00)
    • 5.2.2 The Transmit Overhead Data Input Interface
    • Figure 112. Simple Illustration of the Transmit Overhead Data Input Interface block
    • Table 48: A Listing of the Overhead bits within the E3 frame, and their potential sources, within...
    • Table 49: Description of Method 1 Transmit Overhead Input Interface Signals
    • Figure 113. Illustration of the Terminal Equipment being interfaced to the Transmit Overhead Data...
    • Table 50: The Relationship between the Number of Rising Clock Edges in TxOHClk, (since TxOHFrame ...
    • Figure 114. Illustration of the signal that must occur between the Terminal Equipment and the XRT...
    • Table 51: Description of Method 2 Transmit Overhead Input Interface Signals
    • Figure 115. Illustration of the Terminal Equipment being interfaced to the Transmit Overhead Data...
    • Table 52: The Relationship between the Number of TxOHEnable pulses (since the last occurrence of ...
    • Figure 116. Behavior of Transmit Overhead Data Input Interface signals between the XRT72L54 and t...
    • 5.2.3 The Transmit E3 HDLC Controller
    • Figure 117. LAPD Message Frame Format
    • Table 53: The LAPD Message Type and the Corresponding value of the First Byte, within the Informa...
  • TxE3 Configuration Register (Address = 0x30)
  • Transmit E3 LAPD Configuration Register (Address = 0x33)
    • Table 54: Relationship between TxLAPD Msg Length and the LAPD Message Size
  • TxE3 LAPD Configuration Register (Address = 0x33)
  • Transmit E3 LAPD Configuration Register (Address = 0x33)
  • TxE3 LAPD Status and Interrupt Register (Address = 0x34)
  • TxE3 LAPD Status and Interrupt Register (Address = 0x34)
    • Figure 118. Flow Chart Depicting how to use the LAPD Transmitter
  • Block Interrupt Enable Register (Address = 0x04)
    • 5.2.4 The Transmit E3 Framer Block
    • Figure 119. A Simple Illustration of the Transmit E3 Framer Block and the associated paths to oth...
  • TxE3 Configuration Register (Address = 0x30)
    • Table 55: The Relationship between the contents of Bit 2 (Tx AIS Enable) within the Tx E3 Configu...
    • Table 56: The Relationship between the contents of Bit 1 (Tx LOS) within the Tx E3 Configuration ...
  • TxE3 Configuration Register (Address = 0x30)
  • TxE3 Service Bits Register (Address = 0x35)
  • TxE3 Configuration Register (Address = 0x30)
  • TxE3 Configuration Register (Address = 0x30)
  • TxE3 FAS Error Mask Register - 0 (Address = 0x48)
  • TxE3 FAS Error Mask Register - 1 (Address = 0x49)
  • TxE3 BIP-4 Error Mask Register (Address = 0x4A)
    • 5.2.5 The Transmit E3 Line Interface Block
    • Figure 120. Approach to Interfacing the XRT72L54 Framer IC to the XRT73L04 DS3/E3/STS-1 LIU
    • Figure 121. A Simple Illustration of the Transmit E3 LIU Interface block
    • Figure 122. The Behavior of TxPOS and TxNEG signals during data transmission while the Transmit D...
  • I/O Control Register (Address = 0x01)
    • Table 57: The Relationship between the content of Bit 3 (Unipolar/Bipolar*) within the UNI I/O Co...
    • Figure 123. Illustration of AMI Line Code
    • Figure 124. Illustration of two examples of HDB3 Encoding
  • I/O Control Register (Address = 0x01)
    • Table 58: The Relationship between Bit 4 (AMI/ HDB3*) within the I/O Control Register and the Bip...
  • II/O Control Register (Address = 0x01)
    • Table 59: The Relationship between the contents of Bit 2 (TxLineClk Inv) within the I/O Control R...
    • Figure 125. Waveform/Timing Relationship between TxLineClk, TxPOS and TxNEG - TxPOS and TxNEG are...
    • Figure 126. Waveform/Timing Relationship between TxLineClk, TxPOS and TxNEG - TxPOS and TxNEG are...
    • 5.2.6 Transmit Section Interrupt Processing
  • Block Interrupt Enable Register (Address = 0x04)
  • TxE3 LAPD Status and Interrupt Register (Address = 0x34)
  • TxE3 LAPD Status and Interrupt Register (Address = 0x34)
  • 5.3 The Receive Section of the XRT72L54 (E3 Mode Operation)
    • Figure 127. A Simple Illustration of the Receive Section of the XRT72L54 configured to operate in...
    • 5.3.1 The Receive E3 LIU Interface Block
    • Figure 128. A Simple Illustration of the Receive E3 LIU Interface Block
    • Figure 129. Behavior of the RxPOS, RxNEG and RxLineClk signals during data reception of Unipolar ...
  • I/O Control Register (Address = 0x01)
    • Table 60: The Relationship between the contents of Bit 2 (TxLineClk Inv) within the I/O Control R...
    • Figure 130. Illustration on how a Channel of the Receive E3 Framer (within the XRT72L54 Framer IC...
    • Figure 131. Illustration of AMI Line Code
    • Figure 132. Illustration of two examples of HDB3 Decoding
  • II/O Control Register (Address = 0x01)
    • Table 61: The Relationship between the contents of Bit 1 (RxLineClk Inv) of the I/O Control Regis...
    • Figure 133. Waveform/Timing Relationship between RxLineClk, RxPOS and RxNEG - When RxPOS and RxNE...
    • Figure 134. Waveform/Timing Relationship between RxLineClk, RxPOS and RxNEG - When RxPOS and RxNE...
    • 5.3.2 The Receive E3 Framer Block
    • Figure 135. A Simple Illustration of the Receive E3 Framer Block and the Associated Paths to the ...
    • Figure 136. The State Machine Diagram for the Receive E3 Framer E3 Frame Acquisition/Maintenance ...
    • Figure 137. Illustration of the E3, ITU-T G.751 Framing Format
  • RxE3 Interrupt Status Register - 1 (Address = 0x14)
  • RxE3 Configuration & Status Register - 2 (Address = 0x11)
  • RxE3 Interrupt Status Register - 1 (Address = 0x14)
  • RxE3 Interrupt Status Register - 1 (Address = 0x14)
  • RxE3 Configuration & Status Register - 2 (Address = 0x11)
  • PMON Framing Bit/Byte Error Count Register - MSB (Address = 0x52)
  • PMON Framing Bit/Byte Error Count Register - LSB (Address = 0x53)
  • RxE3 Configuration & Status Register - 2 (Address = 0x11)
    • Table 62: The Relationship between the Logic State of the RxOOF and RxLOF output pins, and the Fr...
  • RxE3 Configuration & Status Register - 2 (Address = 0x11)
  • RxE3 Interrupt Status Register - 1 (Address = 0x14)
  • RxE3 Configuration & Status Register - 2 (Address = 0x11)
  • RxE3 Interrupt Status Register - 1 (Address = 0x14)
  • RxE3 Configuration & Status Register - 2 (Address = 0x11)
  • RxE3 Configuration & Status Register - 2 (Address = 0x11)
  • RxE3 Configuration & Status Register - 1 G.751 (Address = 0x10)
  • RxE3 Interrupt Status Register - 2 (Address = 0x15)
  • RxE3 Configuration & Status Register - 2 (Address = 0x11)
  • RxE3 Configuration & Status Register - 2 (Address = 0x11)
    • Figure 138. Illustration of the Local Receive E3 Framer block, receiving an E3 Frame (from the Re...
    • Figure 139. Illustration of the Local Receive E3 Framer block, transmitting an E3 Frame (to the R...
    • Figure 140. Illustration of the Local Receive E3 Framer block, receiving an E3 Frame (from the Re...
    • Figure 141. Illustration of the Local Receive E3 Framer block, transmitting an E3 Frame (to the R...
  • RxE3 Interrupt Status Register - 2 (Address = 0x15)
  • PMON Parity Error Count Register - MSB (Address = 0x54)
  • PMON Parity Error Count Register - LSB (Address = 0x55)
  • TxE3 Configuration Register (Address = 0x30)
  • RxE3 Interrupt Enable Register - 2 (Address = 0x13)
    • 5.3.3 The Receive HDLC Controller Block
    • Figure 142. LAPD Message Frame Format
  • RxE3 LAPD Control Register (Address = 0x18
  • RxE3 LAPD Status Register (Address = 0x19)
  • RxE3 LAPD Status Register (Address = 0x19)
  • RxE3 LAPD Status Register (Address = 0x19)
  • RxE3 LAPD Status Register (Address = 0x19)
  • RxE3 LAPD Status Register (Address = 0x19)
    • Table 63: The Relationship between the Contents of RxLAPDType[1:0] bit-fields and the PMDL Messag...
  • RxE3 LAPD Control Register (Address = 0x18
  • RxE3 LAPD Status Register (Address = 0x19)
    • Figure 143. Flow Chart depicting the Functionality of the LAPD Receiver
    • 5.3.4 The Receive Overhead Data Output Interface
    • Figure 144. A Simple Illustration of the Receive Overhead Output Interface block
    • Figure 145. Illustration of how to interface the Terminal Equipment to the Receive Overhead Data ...
    • Table 64: Listing and Description of the Pin Associated with the Receive Overhead Data Output Int...
    • Table 65: The Relationship between the Number of Rising Clock Edges in RxOHClk, (since RxOHFrame ...
    • Figure 146. Illustration of the signals that are output via the Receive Overhead Output Interface...
    • Table 66: Listing and Description of the Pin Associated with the Receive Overhead Data Output Int...
    • Figure 147. Illustration of how to interface the Terminal Equipment to the Receive Overhead Data ...
    • Table 67: The Relationship between the Number of RxOHEnable output pulses (since RxOHFrame was la...
    • Figure 148. Illustration of the signals that are output via the Receive Overhead Data Output Inte...
    • 5.3.5 The Receive Payload Data Output Interface
    • Figure 149. A Simple illustration of the Receive Payload Data Output Interface block
    • Table 68: Listing and Description of the pin associated with the Receive Payload Data Output Inte...
    • Figure 150. Illustration of the Terminal Equipment being interfaced to the Receive Payload Data I...
    • Figure 151. An Illustration of the behavior of the signals between the Receive Payload Data Outpu...
    • Figure 152. Illustration of the XRT72L54 DS3/E3 Framer IC being interfaced to the Receive Section...
    • Figure 153. Illustration of the signals that are output via the Receive Payload Data Output Inter...
    • 5.3.6 Receive Section Interrupt Processing
  • Block Interrupt Enable Register (Address = 0x04)
  • RxE3 Interrupt Enable Register - 1 (Address = 0x12)
  • RxE3 Interrupt Status Register - 1 (Address = 0x14)
  • RxE3 Configuration & Status Register - 2 (Address = 0x11)
  • RxE3 Interrupt Enable Register - 1 (Address = 0x12)
  • RxE3 Interrupt Status Register - 1 (Address = 0x14)
  • RxE3 Configuration & Status Register 2 (Address = 0x11)
  • RxE3 Interrupt Enable Register - 1 (Address = 0x12)
  • RxE3 Configuration & Status Register - 2 (Address = 0x11)
  • RxE3 Interrupt Enable Register - 1 (Address = 0x12)
  • RxE3 Configuration & Status Register - 2 (Address = 0x11)
  • RxE3 Interrupt ENABLE Register - 1 (Address = 0x12)
  • RxE3 Interrupt Status Register - 1 (Address = 0x14)
  • RxE3 Interrupt Enable Register - 2 (Address = 0x13)
  • RxE3 Interrupt Status Register - 2 (Address = 0x15)
  • RxE3 Configuration & Status Register - 2 (Address = 0x11)
  • RxE3 Interrupt Enable Register - 2 (Address = 0x13)
  • RxE3 Interrupt Status Register - 2 (Address = 0x15)
  • RxE3 Interrupt Enable Register - 2 (Address = 0x13)
  • RxE3 Interrupt Status Register - 2 (Address = 0x15)
  • RxE3 LAPD Control Register (Address = 0x18)
  • RxE3 LAPD Control Register (Address = 0x18)
• 6.0 E3/ITU-T G.832 Operation of the XRT72L54
  • Framer Operating Mode Register (Address = 0x00)
  • 6.1 Description of the E3, ITU-T G.832 Frames and Associated Overhead Bytes
    • Figure 154. Illustration of the E3, ITU-T G.832 Framing Format.
    • 6.1.1 Definition of the Overhead Bytes
  • Framer Operating Mode Register (Address = 0x00)
    • Table 69: Definition of the Trail Trace Buffer Bytes, within The E3, ITU-T G.832 Framing Format
  • The Maintenance and Adaptation (ma) byte format
    • Table 70: A Listing of the Various Payload Type Values and their corresponding Meaning
  • 6.2 The Transmit Section of the XRT72L54 (E3 Mode Operation)
    • Figure 155. A Simple Illustration of the Transmit Section, within the XRT72L54, when it has been ...
    • 6.2.1 The Transmit Payload Data Input Interface Block
    • Figure 156. A Simple Illustration of the Transmit Payload Data Input Interface Block
    • Table 71: Listing and Description of the pins associated with the Transmit Payload Data Input Int...
    • Figure 157. Illustration of the Terminal Equipment being interfaced to the Transmit Payload Data ...
    • Figure 158. Behavior of the Terminal Interface signals between the Transmit Payload Data Input In...
  • Framer Operating Mode Register (Address = 0x00)
    • Figure 159. Illustration of the Terminal Equipment being interfaced to the Transmit Payload Data ...
    • Figure 160. Behavior of the Terminal Interface signals between the XRT72L54 and the Terminal Equi...
  • Framer Operating Mode Register (Address = 0x00)
    • Figure 161. Illustration of the Terminal Equipment being interfaced to the Transmit Payload Data ...
    • Figure 162. Behavior of the Terminal Interface signals between the XRT72L54 and the Terminal Equi...
  • Framer Operating Mode Register (Address = 0x00)
    • Figure 163. Illustration of the Terminal Equipment being interfaced to the Transmit Payload Data ...
    • Figure 164. Behavior of the Terminal Interface signals between the XRT72L54 and the Terminal Equi...
  • Framer Operating Mode Register (Address = 0x00)
    • Figure 165. Illustration of the Terminal Equipment being interfaced to the Transmit Payload Data ...
    • Figure 166. Behavior of the Terminal Interface signals between the XRT72L54 and the Terminal Equi...
  • Framer Operating Mode Register (Address = 0x00)
    • Figure 167. Illustration of the Terminal Equipment being interfaced to the Transmit Payload Data ...
    • Figure 168. Behavior of the Terminal Interface signals between the XRT72L54 and the Terminal Equi...
  • Framer Operating Mode Register (Address = 0x00)
    • 6.2.2 The Transmit Overhead Data Input Interface
    • Figure 169. Simple Illustration of the Transmit Overhead Data Input Interface block
    • Table 72: A Listing of the Overhead bits within the E3 frame, and their potential sources, within...
    • Table 73: Description of Method 1 Transmit Overhead Input Interface Signals
    • Figure 170. Illustration of the Terminal Equipment being interfaced to the Transmit Overhead Data...
    • Table 74: The Relationship between the Number of Rising Clock Edges in TxOHClk, (since "TxOHFrame...
    • Figure 171. Illustration of the signal that must occur between the Terminal Equipment and the XRT...
    • Table 75: Description of Method 1 Transmit Overhead Input Interface Signals
    • Figure 172. Illustration of the Terminal Equipment being interfaced to the Transmit Overhead Data...
    • Table 76: The Relationship between the Number of TxOHEnable pulses (since the last occurrence of ...
    • Figure 173. Behavior of Transmit Overhead Data Input Interface signals between the XRT72L54 and t...
    • 6.2.3 The Transmit E3 HDLC Controller
    • Figure 174. LAPD Message Frame Format
    • Table 77: The LAPD Message Type and the Corresponding value of the First Byte, within the Informa...
  • Transmit E3 LAPD Configuration Register (Address = 0x33)
    • Table 78: Relationship between TxLAPD Msg Length and the LAPD Message Size
  • TxE3 Configuration Register (Address = 0x30)
  • TxE3 LAPD Configuration Register (Address = 0x33)
  • Transmit E3 LAPD Configuration Register (Address = 0x33)
  • TxE3 LAPD Status and Interrupt Register (Address = 0x34)
  • TxE3 LAPD Status and Interrupt Register (Address = 0x34)
    • Figure 175. Flow Chart depicting how to use the LAPD Transmitter (LAPD Transmitter is configured ...
    • Figure 176. Flow Chart depicting how to use the LAPD Transmitter (LAPD Transmitter is configured ...
  • Block Interrupt Enable Register (Address = 0x04)
    • 6.2.4 The Transmit E3 Framer Block
    • Figure 177. A Simple Illustration of the Transmit E3 Framer Block and the associated paths to oth...
  • TxE3 Configuration Register (Address = 0x30)
    • Table 79: The Relationship between the contents of Bit 2 (Tx AIS Enable) within the Tx E3 Configu...
    • Table 80: The Relationship between the contents of Bit 1 (Tx LOS) within the Tx E3 Configuration ...
    • 6.2.5 The Transmit E3 Line Interface Block
    • Figure 178. Approach to Interfacing the XRT72L54 Framer IC device to the XRT73L04 DS3/E3/STS-1 LIU
    • Figure 179. A Simple Illustration of the Transmit E3 LIU Interface block
    • Figure 180. The Behavior of TxPOS and TxNEG signals during data transmission while the Transmit D...
  • I/O Control Register (Address = 0x01)
    • Table 81: The Relationship between the content of Bit 3 (Unipolar/Bipolar*) within the UNI I/O Co...
    • Figure 181. Illustration of AMI Line Code
    • Figure 182. Illustration of two examples of HDB3 Encoding
  • I/O Control Register (Address = 0x01)
    • Table 82: The Relationship between Bit 4 (AMI/ HDB3*) within the I/O Control Register and the Bip...
  • II/O Control Register (Address = 0x01)
    • Table 83: The Relationship between the contents of Bit 2 (TxLineClk Inv) within the I/O Control R...
    • Figure 183. Waveform/Timing Relationship between TxLineClk, TxPOS and TxNEG - TxPOS and TxNEG are...
    • Figure 184. Waveform/Timing Relationship between TxLineClk, TxPOS and TxNEG - TxPOS and TxNEG are...
    • 6.2.6 Transmit Section Interrupt Processing
  • Block Interrupt Enable Register (Address = 0x04)
  • TxE3 LAPD Status and Interrupt Register (Address = 0x34)
  • TxE3 LAPD Status and Interrupt Register (Address = 0x34)
  • 6.3 The Receive Section of the XRT72L54 (E3 Mode Operation)
    • Figure 185. A Simple Illustration of the Receive Section of the XRT72L54, when it has been config...
    • 6.3.1 The Receive E3 LIU Interface Block
    • Figure 186. A Simple Illustration of the Receive E3 LIU Interface Block
    • Figure 187. Behavior of the RxPOS, RxNEG and RxLineClk signals during data reception of Unipolar ...
  • II/O Control Register (Address = 0x01)
    • Table 84: The Relationship between the contents of Bit 2 (TxLineClk Inv) within the I/O Control R...
    • Figure 188. Illustration on how the XRT72L54 Receive E3 Framer is interfaced to the XRT73L04 Line...
    • Figure 189. Illustration of AMI Line Code
    • Figure 190. Illustration of two examples of HDB3 Decoding
  • II/O Control Register (Address = 0x01)
    • Table 85: The Relationship between the contents of Bit 1 (RxLineClk Inv) of the I/O Control Regis...
    • Figure 191. Waveform/Timing Relationship between RxLineClk, RxPOS and RxNEG - When RxPOS and RxNE...
    • Figure 192. Waveform/Timing Relationship between RxLineClk, RxPOS and RxNEG - When RxPOS and RxNE...
    • 6.3.2 The Receive E3 Framer Block
    • Figure 193. A Simple Illustration of the Receive E3 Framer Block and the Associated Paths to the ...
    • Figure 194. The State Machine Diagram for the Receive E3 Framer E3 Frame Acquisition/Maintenance ...
    • Figure 195. Illustration of the E3, ITU-T G.832 Framing Format
  • RxE3 Interrupt Status Register - 1 (Address = 0x14)
  • RxE3 Configuration & Status Register 2 (Address = 0x11)
  • RxE3 Interrupt Status Register - 1 (Address = 0x14)
  • RxE3 Interrupt Status Register - 1 (Address = 0x14)
  • RxE3 Configuration & Status Register 2 (Address = 0x11)
  • PMON Framing Bit/Byte Error Count Register - MSB (Address = 0x52)
  • PMON Framing Bit/Byte Error Count Register - LSB (Address = 0x53)
  • RxE3 Configuration & Status Register 2 (Address = 0x11)
    • Table 86: The Relationship between the Logic State of the RxOOF and RxLOF output pins, and the Fr...
  • RxE3 Configuration & Status Register 2 (Address = 0x11)
  • RxE3 Interrupt Status Register - 1 (Address = 0x14)
  • RxE3 Configuration & Status Register 2 (Address = 0x11)
  • RxE3 Interrupt Status Register - 1 (Address = 0x14)
  • RxE3 Configuration & Status Register 2 (Address = 0x11)
  • RxE3 Configuration & Status Register 2 (Address = 0x11)
  • The Maintenance and Adaptation (ma) byte format
  • RxE3 Configuration & Status Register 1 - (E3, ITU-T G.832) (Address = 0x10)
  • RxE3 Interrupt Enable Register - 2 (Address = 0x13)
  • RxE3 Configuration & Status Register 2 (Address = 0x11)
  • RxE3 Configuration & Status Register 2 (Address = 0x11)
    • Figure 196. Illustration of the Local Receive E3 Framer block, receiving an E3 Frame (from the Re...
    • Figure 197. Illustration of the Local Receive E3 Framer block, transmitting an E3 Frame (to the R...
    • Figure 198. Illustration of the Local Receive E3 Framer block, receiving an E3 Frame (from the Re...
    • Figure 199. Illustration of the Local Receive E3 Framer block, transmitting an E3 Frame (to the R...
  • RxE3 Interrupt Status Register - 2 (Address = 0x15)
  • PMON Parity Error Count Register - MSB (Address = 0x54)
  • PMON Parity Error Count Register - LSB (Address = 0x55)
  • RxE3 Interrupt Status Register - 2 (Address = 0x15)
  • PMON FEBE Event Count Register - MSB (Address = 0x56)
  • PMON FEBE Event Count Register - LSB (Address = 0x57)
  • RxE3 Interrupt Status Register - 2 (Address = 0x15)
    • 6.3.3 The Receive HDLC Controller Block
    • Figure 200. LAPD Message Frame Format
  • RxE3 LAPD Control Register (Address = 0x18)
  • RxE3 LAPD Control Register (Address = 0x18)
  • RxE3 LAPD Status Register (Address = 0x19)
  • RxE3 LAPD Status Register (Address = 0x19)
  • RxE3 LAPD Status Register (Address = 0x19)
  • RxE3 LAPD Status Register (Address = 0x19)
  • RxE3 LAPD Status Register (Address = 0x19)
    • Table 87: The Relationship between the Contents of RxLAPDType[1:0] bit-fields and the PMDL Messag...
  • RxE3 LAPD Control Register (Address = 0x18)
  • RxE3 LAPD Status Register (Address = 0x19)
    • Figure 201. Flow Chart depicting the Functionality of the LAPD Receiver
    • Figure 202. Flow Chart depicting the Functionality of the LAPD Receiver (Continued)
    • 6.3.4 The Receive Overhead Data Output Interface
    • Figure 203. A Simple Illustration of the Receive Overhead Output Interface block
    • Figure 204. Illustration of how to interface the Terminal Equipment to the Receive Overhead Data ...
    • Table 88: Listing and Description of the Pin Associated with the Receive Overhead Data Output Int...
    • Table 89: The Relationship between the Number of Rising Clock Edges in RxOHClk, (since RxOHFrame ...
    • Figure 205. Illustration of the signals that are output via the Receive Overhead Output Interface...
    • Table 90: Listing and Description of the Pin Associated with the Receive Overhead Data Output Int...
    • Figure 206. Illustration of how to interface the Terminal Equipment to the Receive Overhead Data ...
    • Table 91: The Relationship between the Number of RxOHEnable output pulses (since RxOHFrame was la...
    • Figure 207. Illustration of the signals that are output via the Receive Overhead Data Output Inte...
    • 6.3.5 The Receive Payload Data Output Interface
    • Figure 208. A Simple illustration of the Receive Payload Data Output Interface block
    • Table 92: Listing and Description of the pin associated with the Receive Payload Data Output Inte...
    • Figure 209. Illustration of the Receive Payload Data Output Interface Block (of the XRT72L54 DS3/...
    • Figure 210. An Illustration of the behavior of the signals between the Receive Payload Data Outpu...
    • Figure 211. Illustration of the XRT72L54 DS3/E3 Framer IC being interfaced to the Receive Section...
    • Figure 212. Illustration of the signals that are output via the Receive Overhead Data Output Inte...
    • 6.3.6 Receive Section Interrupt Processing
  • Block Interrupt Enable Register (Address = 0x04)
  • RxE3 Interrupt Enable Register - 1 (Address = 0x12)
  • RxE3 Interrupt Status Register - 1 (Address = 0x14)
  • RxE3 Configuration & Status Register 2 (Address = 0x11)
  • RxE3 Interrupt Enable Register - 1 (Address = 0x12)
  • RxE3 Interrupt Status Register - 1 (Address = 0x14)
  • RxE3 Configuration & Status Register 2 (Address = 0x11)
  • RxE3 Interrupt Enable Register - 1 (Address = 0x12)
  • RxE3 Configuration & Status Register 2 (Address = 0x11)
  • RxE3 Interrupt ENABLE Register - 1 (Address = 0x12)
  • RxE3 Interrupt Status Register - 1 (Address = 0x14)
  • RxE3 Interrupt Enable Register - 1 (Address = 0x12)
  • RxE3 Interrupt Status Register - 1 (Address = 0x14)
  • RxE3 Configuration & Status Register 2 (Address = 0x11)
  • RxE3 Interrupt Enable Register - 2 (Address = 0x13)
  • RxE3 Interrupt Status Register - 2 (Address = 0x15)
  • RxE3 Interrupt Enable Register - 2 (Address = 0x13)
  • RxE3 Interrupt Status Register - 2 (Address = 0x15)
  • RxE3 Configuration & Status Register 2 (Address = 0x11)
  • RxE3 Interrupt Enable Register - 2 (Address = 0x13)
  • RxE3 Interrupt Status Register - 2 (Address = 0x15)
  • RxE3 Interrupt Enable Register - 2 (Address = 0x13)
  • RxE3 Interrupt Status Register - 2 (Address = 0x15)
  • RxE3 Interrupt Enable Register - 2 (Address = 0x13)
  • RxE3 Interrupt Status Register - 2 (Address = 0x15)
  • RxE3 Configuration & Status Register 1 (Address = 0x10)
  • RxE3 Interrupt Enable Register - 2 (Address = 0x13)
  • RxE3 Interrupt Status Register - 2 (Address = 0x15)
  • RxE3 LAPD Control Register (Address = 0x18)
  • RxE3 LAPD Control Register (Address = 0x18)
• 7.0 diagnostic operation of the xrt72L54 framer ic
  • Figure 213. Illustration of the Framer Local Loop-back path, within the XRT72L54 DS3/E3 Framer IC
• 8.0 High Speed HDLC Controller Mode of Operation
  • 8.1 Configuring the Channel to operate in the High Speed HDLC Controller Mode
    • Table 93: Address Locations of each of the HDLC CONTROL Registers within the XRT72L54 Device.
  • HDLC Control Register (Address = 0x82)
  • 8.2 Operating the High Speed HDLC Controller
    • 8.2.1 Operating the Transmit HDLC Controller Block
    • Table 94: Description of Each of the Transmit HDLC Controller Pins
    • Figure 214. A Simple Illustration of an Outbound HDLC Frame, as assembled by the Transmit HDLC Co...
    • Figure 215. A Simple Illustration of an Outbound HDLC Frame, as assembled by the Transmit HDLC Co...
    • 8.2.2 Operating the Receive HDLC Controller Block
    • Table 95: Description of Each of the Receive HDLC Controller Pins
• Ordering Information
• Package Dimensions
  • Revision History