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Exar
Corporation 48720 Kato Road, Fremont CA, 94538
(510) 668-7000
FAX (510) 668-7017
www.exar.com
XRT73LC03A
3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT
OCTOBER 2003
REV. 1.0.1
GENERAL DESCRIPTION
The XRT73LC03A, 3-Channel, DS3/E3/STS-1 Line
Interface Unit is a low power CMOS version of the
XRT73L03A and consists of three independent line
transmitters and receivers integrated on a single chip
designed for DS3, E3 or SONET STS-1 applications.
Each channel of the XRT73LC03A can be configured
to support the E3 (34.368 Mbps), DS3 (44.736 Mbps)
or the SONET STS-1 (51.84 Mbps) rates. Each
channel can be configured to operate in a mode/data
rate that is independent of the other channels.
In the transmit direction, each channel encodes input
data to either B3ZS (DS3/STS-1) or HDB3 (E3) for-
mat and converts the data into the appropriate pulse
shapes for transmission over coaxial cable via a 1:1
transformer.
In the receive direction, the XRT73LC03A performs
equalization on incoming signals, performs Clock Re-
covery, decodes data from either B3ZS or HDB3 for-
mat, converts the receive data into TTL/CMOS for-
mat, checks for LOS or LOL conditions and detects
and declares the occurrence of Line Code Violations.
FEATURES
Incorporates an improved Timing Recovery circuit
and is pin and functional compatible to XRT73L03A
Meets E3/DS3/STS-1 Jitter Tolerance Require-
ments
Contains a 4-Wire Microprocessor Serial Interface
Full Loop-Back Capability
Transmit and Receive Power Down Modes
Full Redundancy Support
Uses Minimum External components
Single +3.3V Power Supply
Low power CMOS design
5V tolerant I/O
-40C to +85C Operating Temperature Range
Available in a 120 pin LQFP package
APPLICATIONS
Digital Cross Connect Systems
CSU/DSU Equipment
Routers
Fiber Optic Terminals
Multiplexers
ATM Switches
F
IGURE
1. XRT73LC03A B
LOCK
D
IAGRAM
ENDECDIS
RLOS_(n)
LLB_(n)
RLB_(n)
TAOS_(n)
TPData_(n)
TNData_(n)
TxClk_(n)
TxLEV_(n)
TxOFF_(n)
Channel 2 - (n) = 2
AGC/
Equalizer
Serial
Processor
Interface
Peak
Detector
LOS Detector
Slicer
Clock
Recovery
Data
Recovery
Invert
Loop MUX
HDB3/
B3ZS
Decoder
LOSTHR_(n)
SDI
SDO
SClk
CS
REGR
RTIP_(n)
RRing_(n)
REQEN_(n)
Channel 0 - (n) = 0
Channel 1 - (n) = 1
Notes: 1. (n) = 0, 1, or 2 for respective Channels
2. Serial Processor Interface input pins are shared by the three Channels in HOST Mode and redefined in Hardware Mode.
Device
Monitor
MTIP_(n)
MRing_(n)
DMO_(n)
Transmit
Logic
Duty Cycle Adjust
TTIP_(n)
TRing_(n)
Pulse
Shaping
HDB3/
B3ZS
Encoder
E3_(n)
STS-1/DS3_(n)
Host/(HW)
RLOL_(n) EXClk_(n)
RxOFF
RxClkINV
RxClk_(n)
RPOS_(n)
RNEG_(n)
LCV_(n)
Tx
Control
XRT73LC03A
3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT
REV. 1.0.1
2
TYPICAL APPLICATIONS
TRANSMIT INTERFACE CHARACTERISTICS:
Accepts either Single-Rail or Dual-Rail data from
Terminal Equipment and generates a bipolar signal
from the line
Integrated Pulse Shaping Circuit
Built-in B3ZS/HDB3 Encoder (which can be dis-
abled)
Contains Transmit Clock Duty Cycle Correction Cir-
cuit on-chip
Generates pulses that comply with the ITU-T G.703
pulse template (E3 applications)
Generates pulses that comply with the DSX-3 pulse
template as specified in Bellcore GR-499
-CORE
and ANSI T1.102_1993
Generates pulses that comply with the STSX-1
pulse template as specified in Bellcore GR-253-
CORE
Transmitter can be turned off in order to support
redundancy designs
RECEIVE INTERFACE CHARACTERISTICS:
Integrated Adaptive Receive Equalization (optional)
and Timing Recovery
Declares and Clears the LOS defect per ITU-T
G.775 requirements (E3 and DS3 applications)
Meets Jitter Tolerance Requirements as specified in
ITU-T G.823_1993 (E3 Applications)
Meets Jitter Tolerance Requirements as specified in
Bellcore GR-499-CORE (DS3 Applications)
Declares Loss of Signal (LOS) and Loss of Lock
(LOL) Alarms
Built-in B3ZS/HDB3 Decoder (which can be dis-
abled)
Recovered Data can be muted while the LOS Con-
dition is declared
Outputs either Single-Rail or Dual-Rail data to the
Terminal Equipment
Receiver can be powered down in order to con-
serve power in redundancy designs
F
IGURE
2. M
ULTI
C
HANNEL
ATM A
PPLICATION
ATM
Switch/
SAR
XRT74L73
RPOS
RNEG
RxLineClk
XRT71D03
XRT73LC03
RRPOS
RRNEG
RRClk
RPOS
RNEG
RxClk
RPOS
RNEG
RxClk
RTIP
RRing
TTIP
TRing
TPOS
TNEG
TxLineClk
MClk
TPOS
TNEG
TxClk
3 Channel E3/DS3 ATM UNI
3 Channel E3/DS3 J/A
3 Channel E3/DS3 LIU
F
IGURE
3. M
ULTI
S
ERVICE
- F
RAME
R
ELAY
A
PPLICATION
Frame
Relay
XRT72L56
RPOS
RNEG
RxLineClk
XRT71D03
XRT73LC03
RRPOS
RRNEG
RRClk
RPOS
RNEG
RxClk
RPOS
RNEG
RxClk
RTIP
RRing
TTIP
TRing
TPOS
TNEG
TxLineClk
MClk
TPOS
TNEG
TxClk
6 Channel E3/DS3 Framer
2 x 3 Channel E3/DS3 J/A
2 x 3 Channel E3/DS3 LIU
XRT73LC03A
3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT
REV. 1.0.1
3
ORDERING INFORMATION
F
IGURE
4. P
IN
OUT
OF
THE
XRT73LC03A
IN
THE
120 P
IN
LQFP
PACKAGE
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
XRT73LC03A
R LO L_ 2
LC V _2
R LO S _ 2
R LO L_ 0
LC V _0
R LO S _ 0
R xD G N D _ 0
N C
N C
R P O S _0
R N E G _ 0
R xC lk _0
R xD V D D _ 0
E X C lk_ 0
R xD G N D _ 2
R P O S _2
R N E G _ 2
R xC lk _2
H O S T/(H W )
R xD V D D _ 2
A G N D _ 0
TxA G N D _0
D M O _ 0
TxA V D D _ 0
RE
G
R
/
(
Rx
Cl
k
I
N
V
)
S
T
S-
1/
D
S
3_
1
AGN
D
_
2
S
R
/
(
DR)
E3
_
1
NC
NC
L
O
S
T
HR_
1
LL
B
_
1
RL
B
_
1
Rx
A
V
DD_
1
RRi
n
g
_
1
RT
I
P
_
1
Rx
A
G
ND
_
1
RE
Q
E
N_
1
Rx
A
G
ND
_
2
RT
I
P
_
2
RRi
n
g
_
2
Rx
A
V
DD_
2
RL
B
_
2
LL
B
_
2
L
O
S
T
HR_
2
RE
Q
E
N_
0
Rx
A
G
ND
_
0
RT
I
P
_
0
RRi
n
g
_
0
Rx
A
V
DD_
0
RL
B
_
0
LL
B
_
0
L
O
S
T
HR_
0
IC
T
S
T
S-
1/
D
S
3_
0
S
D
O
/
(
E
3
_0)
S
D
I/(
R
x
O
F
F
_
0
)
S
C
l
k
/
(
R
x
O
F
F
_1)
CS
/
(
E
N
D
E
CD
I
S
)
TN
Da
t
a
_
1
TP
D
a
t
a
_
1
Tx
Cl
k
_
1
MR
i
n
g
_
1
MT
I
P
_
1
TA
O
S
_
1
TA
O
S
_
2
T
x
LEV_1
T
x
LEV_2
TTI
P
_
1
Tx
A
V
D
D
_
1
TRi
n
g
_
1
TxA
G
ND
_
1
TxA
G
ND
_
2
MR
i
n
g
_
2
MT
I
P
_
2
TxA
G
ND
_
2
TRi
n
g
_
2
Tx
A
V
D
D
_
2
TTI
P
_
2
DMO
_
2
Tx
A
V
D
D
_
2
TN
Da
t
a
_
2
TP
D
a
t
a
_
2
Tx
Cl
k
_
2
TxA
G
ND
_
0
TRi
n
g
_
0
Tx
A
V
D
D
_
0
TTI
P
_
0
MT
I
P
_
0
MR
i
n
g
_
0
TN
Da
t
a
_
0
TP
D
a
t
a
_
0
Tx
Cl
k
_
0
T
x
LEV_0
TA
O
S
_
0
EXDG ND
EXDVDD
EXClk_1
REQEN_2
STS1/DS3_2
E3_2
EXClk_2
RxOFF_2
RLOL_1
LCV_1
RLO S_1
RxDGND_1
RPO S_1
RNEG_1
RxClk_1
LOSM UTEN
RxDVDD_1
AGND_1
TxOFF_2
TxOFF_1
TxOFF_0
TxAGND_1
TxAVDD_1
DM O_1
P
ART
#
P
ACKAGE
O
PERATING
TEMPERATURE
R
ANGE
XRT73LC03AIV
120 Pin LQFP 14mm X 20mm
-40
o
C to +85
o
C
XRT73LC03A
3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT
REV. 1.0.1
I
TABLE OF CONTENTS
GENERAL DESCRIPTION ................................................................................................. 1
F
EATURES
.................................................................................................................................................... 1
APPLICATIONS ......................................................................................................................................... 1
T
YPICAL
A
PPLICATIONS
................................................................................................................................. 2
T
RANSMIT
I
NTERFACE
C
HARACTERISTICS
: ..................................................................................................... 2
R
ECEIVE
I
NTERFACE
C
HARACTERISTICS
: ....................................................................................................... 2
ORDERING INFORMATION ............................................................................................... 3
PIN DESCRIPTIONS (BY FUNCTION) .............................................................................. 4
T
RANSMIT
I
NTERFACE
................................................................................................................................... 4
R
ECEIVE
I
NTERFACE
..................................................................................................................................... 6
C
LOCK
I
NTERFACE
........................................................................................................................................ 7
O
PERATING
M
ODE
S
ELECT
........................................................................................................................... 7
C
ONTROL
AND
A
LARM
I
NTERFACE
................................................................................................................. 9
M
ICROPROCESSOR
I
NTERFACE
.................................................................................................................... 11
P
OWER
AND
G
ROUND
P
INS
......................................................................................................................... 13
N
O
C
ONNECTION
P
INS
................................................................................................................................ 14
ELECTRICAL CHARACTERISTICS ................................................................................ 15
A
BSOLUTE
M
AXIMUM
R
ATINGS
.................................................................................................................... 15
SYSTEM DESCRIPTION .................................................................................................. 24
T
HE
T
RANSMIT
S
ECTION
- C
HANNELS
0, 1
AND
2 ......................................................................................... 24
T
HE
R
ECEIVE
S
ECTION
- C
HANNELS
0, 1
AND
2 ........................................................................................... 24
T
HE
M
ICROPROCESSOR
S
ERIAL
I
NTERFACE
................................................................................................. 24
1.0 Selecting the Data Rate .................................................................................................................... 25
1.1 C
ONFIGURING
C
HANNEL
(
N
) ............................................................................................................................... 25
2.0 The Transmit Section ....................................................................................................................... 27
C
OMMAND
R
EGISTER
, CR4-(
N
) ...................................................................................................... 27
2.1 T
HE
T
RANSMIT
L
OGIC
B
LOCK
............................................................................................................................ 27
2.1.1 Accepting Dual-Rail Data from the Terminal Equipment ...................................................................... 27
2.1.2 Accepting Single-Rail Data from the Terminal Equipment ................................................................... 28
C
OMMAND
R
EGISTER
CR1-(
N
) ....................................................................................................... 28
2.2 T
HE
T
RANSMIT
C
LOCK
D
UTY
C
YCLE
A
DJUST
C
IRCUITRY
................................................................................... 29
2.3 T
HE
HDB3/B3ZS E
NCODER
B
LOCK
.................................................................................................................. 29
2.3.1 B3ZS Encoding .................................................................................................................................... 29
2.3.2 HDB3 Encoding .................................................................................................................................... 30
2.3.3 Disabling the HDB3/B3ZS Encoder ..................................................................................................... 30
C
OMMAND
R
EGISTER
CR2-(
N
) ....................................................................................................... 30
2.4 T
HE
T
RANSMIT
P
ULSE
S
HAPING
C
IRCUITRY
....................................................................................................... 31
2.4.1 Enabling the Transmit Line Build-Out Circuit ....................................................................................... 32
C
OMMAND
R
EGISTER
, CR1-(
N
) ...................................................................................................... 32
2.4.2 Disabling the Transmit Line Build-Out Circuit ....................................................................................... 32
C
OMMAND
R
EGISTER
, CR1-(
N
) ...................................................................................................... 33
2.4.3 Design Guideline for Setting the Transmit Line Build-Out Circuit ......................................................... 33
2.4.4 The Transmit Line Build-Out Circuit and E3 Applications .................................................................... 33
2.5 I
NTERFACING
THE
T
RANSMIT
S
ECTIONS
OF
THE
XRT73LC03A
TO
THE
L
INE
...................................................... 33
T
RANSFORMER
R
ECOMMENDATIONS
............................................................................................... 34
3.0 The Receive Section ......................................................................................................................... 35
3.1 I
NTERFACING
THE
R
ECEIVE
S
ECTIONS
OF
THE
XRT73LC03A
TO
THE
L
INE
........................................................ 35
3.2 T
HE
R
ECEIVE
E
QUALIZER
B
LOCK
...................................................................................................................... 36
3.2.1 Guidelines for Setting the Receive Equalizer ...................................................................................... 36
C
OMMAND
R
EGISTER
CR2-(
N
) ....................................................................................................... 37
3.3 C
LOCK
R
ECOVERY
PLL .................................................................................................................................... 38
3.3.1 The Training Mode ............................................................................................................................... 38
3.3.2 The Data/Clock Recovery Mode .......................................................................................................... 38
XRT73LC03A
3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT
REV. 1.0.1
II
3.4 T
HE
HDB3/B3ZS D
ECODER
............................................................................................................................. 38
3.4.1 B3ZS Decoding (DS3/STS-1 Applications) .......................................................................................... 38
3.4.2 HDB3 Decoding (E3 Applications) ....................................................................................................... 38
3.4.3 Configuring the HDB3/B3ZS Decoder ................................................................................................. 39
C
OMMAND
R
EGISTER
CR2-(
N
) ...................................................................................................... 39
3.5 LOS D
ECLARATION
/C
LEARANCE
....................................................................................................................... 39
3.5.1 The LOS Declaration/Clearance Criteria for E3 Applications ............................................................... 40
3.5.2 The LOS Declaration/Clearance Criteria for DS3 and STS-1 Applications .......................................... 41
C
OMMAND
R
EGISTER
CR0-(
N
) ...................................................................................................... 42
C
OMMAND
R
EGISTER
CR2-(
N
) ...................................................................................................... 42
C
OMMAND
R
EGISTER
CR0-(
N
) ...................................................................................................... 42
C
OMMAND
R
EGISTER
CR2-(
N
) ...................................................................................................... 42
3.5.3 Muting the Recovered Data while the LOS is being Declared ............................................................. 42
C
OMMAND
R
EGISTER
CR3-(
N
) ...................................................................................................... 43
3.6 R
OUTING
THE
R
ECOVERED
T
IMING
AND
D
ATA
I
NFORMATION
TO
THE
R
ECEIVING
T
ERMINAL
E
QUIPMENT
.............. 43
3.6.1 Routing Dual-Rail Format Data to the Receiving Terminal Equipment ................................................ 43
C
OMMAND
R
EGISTER
CR3-(
N
) ...................................................................................................... 45
3.6.2 Routing Single-Rail Format (Binary Data Stream) data to the Receive Terminal Equipment .............. 45
C
OMMAND
R
EGISTER
CR3-(
N
) ...................................................................................................... 45
3.7 S
HUTTING
OFF
THE
R
ECEIVE
S
ECTION
............................................................................................................. 46
C
OMMAND
R
EGISTER
CR3-(
N
) ...................................................................................................... 46
4.0 Diagnostic Features of the XRT73LC03A ...................................................................................... 47
4.1 T
HE
A
NALOG
L
OCAL
L
OOP
-B
ACK
M
ODE
............................................................................................................ 47
4.2 T
HE
D
IGITAL
L
OCAL
L
OOP
-B
ACK
M
ODE
. ........................................................................................................... 48
C
OMMAND
R
EGISTER
CR4-(
N
) ...................................................................................................... 48
C
OMMAND
R
EGISTER
CR4-(
N
) ...................................................................................................... 48
4.3 T
HE
R
EMOTE
L
OOP
-B
ACK
M
ODE
...................................................................................................................... 49
C
OMMAND
R
EGISTER
CR4-(n) ...................................................................................................... 49
4.4 T
X
OFF F
EATURES
........................................................................................................................................... 50
C
OMMAND
R
EGISTER
CR1-(
N
) ...................................................................................................... 50
4.5 T
HE
T
RANSMIT
D
RIVE
M
ONITOR
F
EATURES
....................................................................................................... 50
4.6 T
HE
TAOS (T
RANSMIT
A
LL
O
NE
S) F
EATURE
.................................................................................................... 51
5.0 The Microprocessor Serial Interface .............................................................................................. 51
5.1 D
ESCRIPTION
OF
THE
C
OMMAND
R
EGISTERS
.................................................................................................... 51
C
OMMAND
R
EGISTER
CR1-(
N
) ...................................................................................................... 51
5.2 D
ESCRIPTION
OF
B
IT
-F
IELDS
FOR
EACH
C
OMMAND
R
EGISTER
........................................................................... 53
5.2.1 Command Register - CR0-(n) .............................................................................................................. 53
C
OMMAND
R
EGISTER
CR
0-(
N
) ....................................................................................................... 53
C
OMMAND
R
EGISTER
CR1-(
N
) ...................................................................................................... 53
5.2.3 Command Register CR2-(n) ................................................................................................................ 54
C
OMMAND
R
EGISTER
CR2-(
N
) ...................................................................................................... 54
C
OMMAND
R
EGISTER
CR3-(
N
) ...................................................................................................... 54
C
OMMAND
R
EGISTER
CR4-(
N
) ...................................................................................................... 55
5.3 O
PERATING
THE
M
ICROPROCESSOR
S
ERIAL
I
NTERFACE
. ................................................................................... 56
ORDERING INFORMATION ............................................................................................. 58
PACKAGE DIMENSIONS ................................................................................................. 58
R
EVISION
H
ISTORY
..................................................................................................................................... 59
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