Exar
Corporation 48720 Kato Road, Fremont CA, 94538
(510) 668-7000
FAX (510) 668-7017
www.exar.com
XRT75L00
E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR
FEBRUARY 2004
REV. 1.0.2
GENERAL DESCRIPTION
The XRT75L00 is a single-channel fully integrated
Line Interface Unit (LIU) with Jitter Attenuator for E3/
DS3/STS-1 applications. It incorporates an
independent Receiver, Transmitter and Jitter
Attenuator in a single 52 pin TQFP package.
The XRT75L00 can be configured to operate in either
E3 (34.368 MHz), DS3 (44.736 MHz) or STS-1 (51.84
MHz) modes. The transmitter can be turned off (tri-
stated) for redundancy support and for conserving
power.
The XRT75L00's differential receiver provides high
noise interference margin and is able to receive the
data over 1000 feet of cable or with up to 12 dB of
cable attenuation.
The XRT75L00 incorporates an advanced crystal-
less jitter attenuator that can be selected either in the
transmit or receive path. The jitter attenuator
performance meets the ETSI TBR-24 and Bellcore
GR-499 specifications.
The XRT75L00 provides both Serial Microprocessor
Interface as well as Hardware mode for programming
and control.
The XRT75L00 supports local, remote and digital
loop-backs. The XRT75L00 also contains an on-
board Pseudo Random Binary Sequence (PRBS)
generator and detector with the ability to insert and
detect single bit error.
FEATURES
RECEIVER:
On chip Clock and Data Recovery circuit for high
input jitter tolerance.
Meets E3/DS3/STS-1 Jitter Tolerance
Requirements.
Detects and Clears LOS as per G.775.
Meets Bellcore GR-499 CORE Jitter Transfer
Requirements.
Receiver Monitor mode handles up to 20 dB flat
loss with 6 dB cable attenuation.
Compliant with jitter transfer template outlined in
ITU G.751, G.752, G.755 and GR-499-CORE,1995
standards.
Meets ETSI TBR 24 Jitter Transfer Requirements.
On chip B3ZS/HDB3 encoder and decoder that can
be either enabled or disabled.
On-chip clock synthesizer provides the appropriate
rate clock from a single 12.288 MHz Clock.
Provides low jitter output clock.
TRANSMITTER:
Compliant with Bellcore GR-499, GR-253 and ANSI
T1.102 Specification for transmit pulse
Tri-state Transmit output capability for redundancy
applications
Transmitter can be turned on or off.
JITTER ATTENUATOR:
On chip advanced crystal-less Jitter Attenuator.
Jitter Attenuator can be selected in Receive or
Transmit paths.
16 or 32 bits selectable FIFO size.
Meets the Jitter and Wander specifications
described in T1.105.03b,ETSI TBR-24, Bellcore
GR-253 and GR-499 standards.
Jitter Attenuator can be disabled.
CONTROL AND DIAGNOSTICS:
5 wire Serial Microprocessor Interface for control
and configuration.
Supports optional internal Transmit Driver
Monitoring.
PRBS error counter register to accumulate errors.
Hardware Mode for control and configuration.
Supports Local, Remote and Digital Loop-backs.
Single 3.3 V 5% power supply.
5 V Tolerant I/O.
Available in 52 pin TQFP.
-40C to 85C Industrial Temperature Range.
APPLICATIONS
E3/DS3 Access Equipment.
DSLAMs.
Digital Cross Connect Systems.
CSU/DSU Equipment.
Routers.
Fiber Optic Terminals.
XRT75L00
E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR
REV. 1.0.2
2
TRANSMIT INTERFACE CHARACTERISTICS
Accepts either Single-Rail or Dual-Rail data from Terminal Equipment and generates a bipolar signal to the
line.
Integrated Pulse Shaping Circuit.
Built-in B3ZS/HDB3 Encoder (which can be disabled).
Accepts Transmit Clock with duty cycle of 30%-70%.
Generates pulses that comply with the ITU-T G.703 pulse template for E3 applications.
Generates pulses that comply with the DSX-3 pulse template, as specified in Bellcore GR-499
-CORE
and
ANSI T1.102_1993.
Generates pulses that comply with the STSX-1 pulse template, as specified in Bellcore GR-253-CORE.
Transmitter can be turned off in order to support redundancy designs.
RECEIVE INTERFACE CHARACTERISTICS
Integrated Adaptive Receive Equalization for optimal Clock and Data Recovery.
Declares and Clears the LOS defect per ITU-T G.775 requirements for E3 and DS3 applications.
Meets Jitter Tolerance Requirements, as specified in ITU-T G.823_1993 for E3 Applications.
Meets Jitter Tolerance Requirements, as specified in Bellcore GR-499-CORE for DS3 Applications.
Declares Loss of Signal (LOS) and Loss of Lock (LOL) Alarms.
Built-in B3ZS/HDB3 Decoder (which can be disabled).
F
IGURE
1. B
LOCK
D
IAGRAM
OF
THE
XRT 75L00
HOST/HW
STS-1/DS3
E3
REQEN
RTIP
RRING
SR/DR
XRT75L03
RLB
RLOS
JATx/Rx
TPData
TNData
TxClk
TAOS
TxLEV
TxON
Note: Serial Processor Interface input pins are shared by in "Host" Mode and redefined in the "Hardware" Mode.
Device
Monitor
MTIP
MRING
DMO
Timing
Control
TTIP
TRING
Tx
Pulse
Shaping
HDB3/
B3ZS
Encoder
RLOL
RxON
RxClkINV
RxClk
RPOS
RNEG/
LCV
Tx
Control
Jitter
Attenuator
MUX
Line
Driver
LLB
Invert
Remote
LoopBack
HDB3/
B3ZS
Decoder
MUX
AGC/
Equalizer
Peak Detector
LOS
Detector
Slicer
Jitter
Attenuator
Serial
Processor
Interface
Local
LoopBack
Clock & Data
Recovery
Clock
Synthesizer
ExClk/12M
RESET
CS
SClk
INT
SDO
SDI
CLK_OUT
XRT75L00
REV. 1.0.2
E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR
3
Recovered Data can be muted while the LOS Condition is declared.
Outputs either Single-Rail or Dual-Rail data to the Terminal Equipment.
JITTER ATTENUATORS
The XRT75L00 includes a Jitter Attenuator that meets the Jitter requirements specified in the ETSI TBR-24,
Bellcore GR-499 and GR-253 standards. In addition, the jitter attenuator also meets the Jitter and Wander
specifications described in the ANSI T1.105.03b 1997, Bellcore GR-253 and GR-499 standards.
F
IGURE
2. P
IN
O
UT
OF
THE
XRT75L00
ORDERING INFORMATION
P
ART
N
UMBER
P
ACKAGE
O
PERATING
T
EMPERATURE
R
ANGE
XRT75L00IV
52 Pin TQFP
-40
C to +85
C
CLK_OUT
RPOS
RNEG (LCV)
RxClk
GND
Ref
AGND
Rext
Ref
AVDD
VDD
RLOS
RLOL
I
N
T
(LO
SMUT
)
S
D
O (Rx
M
ON)
TxLEV
TA
OS
T
x
AVDD
Tx
ON
Tx
A
G
ND
JA0
JA1
J
A
Tx
/R
x
SF
M_EN
RxAVDD
RRI
NG
RTI
P
RxAGND
XRT75L00
(top view)
40
41
42
43
44
45
46
47
48
49
50
51
52
26
25
24
23
22
21
20
19
18
17
16
15
14
1
2
3
4
5
6
7
8
9
10
11
12
13
39
38
37
36
35
34
33
32
31
30
29
28
27
DMO
MTIP
MRING
JaAGND
ExClk/12M
JaAVDD
TxClk
TPData
TNData
DGND
TTIP
TRING
DVDD
SCLK (TxClkINV)
SDI (RxON)
CS (RxClkINV)
REQEN
SR/DR
HOST/HW
E3
STS1/DS3
RLB
LLB
ICT
TEST
RESET
XRT75L00
E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR
REV. 1.0.2
I
TABLE OF CONTENTS
GENERAL DESCRIPTION.............................................................................................................. 1
F
EATURES
..................................................................................................................................................................... 1
A
PPLICATIONS
............................................................................................................................................................... 1
T
RANSMIT
I
NTERFACE
C
HARACTERISTICS
....................................................................................................................... 2
R
ECEIVE
I
NTERFACE
C
HARACTERISTICS
......................................................................................................................... 2
F
IGURE
1. B
LOCK
D
IAGRAM
OF
THE
XRT 75L00 ..................................................................................................................................... 2
J
ITTER
A
TTENUATORS
.................................................................................................................................................... 3
F
IGURE
2. P
IN
O
UT
OF
THE
XRT75L00 .................................................................................................................................................. 3
ORDERING INFORMATION .....................................................................................................................3
T
ABLE
OF
C
ONTENTS
I
PIN DESCRIPTIONS (BY FUNCTION) .......................................................................................... 4
T
RANSMIT
I
NTERFACE
.................................................................................................................................................... 4
R
ECEIVE
I
NTERFACE
...................................................................................................................................................... 6
C
LOCK
I
NTERFACE
......................................................................................................................................................... 8
O
PERATING
M
ODE
S
ELEC
T............................................................................................................................................ 9
C
ONTROL
AND
A
LARM
I
NTERFACE
.................................................................................................................................. 9
M
ICROPROCESSOR
S
ERIAL
INTERFACE - (HOST MODE)......................................................................................... 11
................................................................................................................................................................................... 13
J
ITTER
A
TTENUATOR
INTERFACE
.................................................................................................................................. 13
A
NALOG
P
OWER
AND
G
ROUND
.................................................................................................................................... 14
D
IGITAL
P
OWER
AND
G
ROUND
.................................................................................................................................... 14
1.0 ELECTRICAL CHARACTERISTICS ....................................................................................................15
T
ABLE
1: A
BSOLUTE
M
AXIMUM
R
ATINGS
............................................................................................................................................... 15
T
ABLE
2: DC E
LECTRICAL
C
HARACTERISTICS
:....................................................................................................................................... 15
2.0 TIMING CHARACTERISTICS ..............................................................................................................16
F
IGURE
3. T
YPICAL
INTERFACE
BETWEEN
TERMINAL
EQUIPMENT
AND
THE
XRT75L00 (
DUAL
-
RAIL
DATA
) ................................................. 16
F
IGURE
4. T
RANSMITTER
T
ERMINAL
I
NPUT
T
IMING
................................................................................................................................. 16
F
IGURE
5. R
ECEIVER
D
ATA
OUTPUT
AND
CODE
VIOLATION
TIMING
.......................................................................................................... 17
F
IGURE
6. T
RANSMIT
P
ULSE
A
MPLITUDE
TEST
CIRCUIT
FOR
E3, DS3
AND
STS-1 R
ATES
....................................................................... 17
3.0 LINE SIDE CHARACTERISTICS: ........................................................................................................18
3.1 E3 LINE SIDE PARAMETERS: ...................................................................................................................... 18
F
IGURE
7. P
ULSE
M
ASK
FOR
E3 (34.368
MBITS
/
S
)
INTERFACE
AS
PER
ITU
-
T
G.703 ............................................................................... 18
T
ABLE
3: E3 T
RANSMITTER
AND
RECEIVER
LINE
SIDE
SPECIFICATIONS
(T
A
= 250C
AND
VDD = 3.3 V 5%) .......................................... 18
F
IGURE
8. B
ELLCORE
GR-253 CORE T
RANSMIT
O
UTPUT
P
ULSE
T
EMPLATE
FOR
SONET STS-1 A
PPLICATIONS
................................... 19
T
ABLE
4: STS-1 P
ULSE
M
ASK
E
QUATIONS
........................................................................................................................................... 19
T
ABLE
5: STS-1 T
RANSMITTER
AND
R
ECEIVER
L
INE
S
IDE
S
PECIFICATIONS
(TA = 250C
AND
VDD =3.3V 5%)................................... 20
F
IGURE
9. T
RANSMIT
O
UPUT
P
ULSE
T
EMPLATE
FOR
DS3
AS
PER
B
ELLCORE
GR-499 ........................................................................... 20
T
ABLE
6: DS3 P
ULSE
M
ASK
E
QUATIONS
............................................................................................................................................... 21
T
ABLE
7: DS3 T
RANSMITTER
AND
R
ECEIVER
L
INE
S
IDE
S
PECIFICATIONS
(T
A
= 250C
AND
VDD = 3.3V 5%) ...................................... 21
F
IGURE
10. M
ICROPROCESSOR
S
ERIAL
I
NTERFACE
S
TRUCTURE
............................................................................................................ 22
F
IGURE
11. T
IMING
D
IAGRAM
FOR
THE
M
ICROPROCESSOR
S
ERIAL
I
NTERFACE
....................................................................................... 22
T
ABLE
8: M
ICROPROCESSOR
S
ERIAL
I
NTERFACE
T
IMINGS
( TA = 250C, VDD=3.3V 5%
AND
LOAD
= 10
P
F) ........................................ 23
4.0 THE TRANSMITTER SECTION: .........................................................................................................24
4.1 TRANSMIT CLOCK: ....................................................................................................................................... 24
4.2 B3ZS/HDB3 ENCODER: ................................................................................................................................. 24
4.2.1 B3ZS ENCODING: ...................................................................................................................................................... 24
F
IGURE
12. S
INGLE
-R
AIL
OR
NRZ D
ATA
F
ORMAT
(E
NCODER
AND
D
ECODER
ARE
E
NABLED
) .................................................................. 24
F
IGURE
13. D
UAL
-R
AIL
D
ATA
F
ORMAT
(
ENCODER
AND
DECODER
ARE
DISABLED
).................................................................................... 24
4.2.2 HDB3 ENCODING:...................................................................................................................................................... 25
F
IGURE
14. B3ZS E
NCODING
F
ORMAT
................................................................................................................................................. 25
F
IGURE
15. HDB3 E
NCODING
F
ORMAT
................................................................................................................................................. 25
4.3 TRANSMIT PULSE SHAPER: ........................................................................................................................ 26
4.3.1 GUIDELINES FOR USING TRANSMIT BUILD OUT CIRCUIT: ................................................................................. 26
4.3.2 INTERFACING TO THE LINE: .................................................................................................................................... 26
4.4 TRANSMIT DRIVE MONITOR: ....................................................................................................................... 26
4.5 TRANSMITTER SECTION ON/OFF: .............................................................................................................. 27
F
IGURE
16. T
RANSMIT
D
RIVER
M
ONITOR
SET
-
UP
................................................................................................................................... 27
5.0 THE RECEIVER SECTION ..................................................................................................................28
XRT75L00
E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR
REV. 1.0.2
II
5.1 AGC/EQUALIZER ........................................................................................................................................... 28
5.1.1 INTERFERENCE TOLERANCE.................................................................................................................................. 28
F
IGURE
17. I
NTERFERENCE
M
ARGIN
T
EST
S
ET
UP
FOR
DS3/STS-1 ...................................................................................................... 29
F
IGURE
18. I
NTERFERENCE
M
ARGIN
T
EST
S
ET
UP
FOR
E3. ................................................................................................................... 29
T
ABLE
9: I
NTERFERENCE
M
ARGIN
T
EST
R
ESULTS
................................................................................................................................. 29
5.2 CLOCK AND DATA RECOVERY: .................................................................................................................. 30
5.3 B3ZS/HDB3 DECODER: ................................................................................................................................ 30
5.4 LOS (LOSS OF SIGNAL) DETECTOR: ......................................................................................................... 30
5.4.1 DS3/STS-1 LOS CONDITION: .................................................................................................................................... 30
D
ISABLING
ALOS/DLOS D
ETECTOR
: ........................................................................................................................... 30
5.4.2 E3 LOS CONDITION:.................................................................................................................................................. 30
T
ABLE
10: T
HE
ALOS (A
NALOG
LOS) D
ECLARATION
AND
C
LEARANCE
T
HRESHOLDS
FOR
A
GIVEN
SETTING
OF
REQEN (DS3
AND
STS-1 A
P
-
PLICATIONS
).......................................................................................................................................................................... 30
F
IGURE
19. L
OSS
O
F
S
IGNAL
D
EFINITION
FOR
E3
AS
PER
ITU-T G.775 ................................................................................................ 31
F
IGURE
20. L
OSS
OF
S
IGNAL
D
EFINITION
FOR
E3
AS
PER
ITU-T G.775................................................................................................. 31
5.4.2.1 M
UTING
THE
R
ECOVERED
D
ATA
WITH
LOS
CONDITION
: ......................................................................................... 32
6.0 JITTER: ................................................................................................................................................ 33
6.1 JITTER TOLERANCE - RECEIVER: .............................................................................................................. 33
6.1.1 DS3/STS-1 JITTER TOLERANCE REQUIREMENTS:............................................................................................... 33
F
IGURE
21. J
ITTER
T
OLERANCE
M
EASUREMENTS
.................................................................................................................................. 33
6.1.2 E3 JITTER TOLERANCE REQUIREMENTS:............................................................................................................. 34
F
IGURE
22. I
NPUT
J
ITTER
T
OLERANCE
F
OR
DS3/STS-1 ...................................................................................................................... 34
F
IGURE
23. I
NPUT
J
ITTER
T
OLERANCE
FOR
E3 .................................................................................................................................... 34
6.2 JITTER TRANSFER - RECEIVER/TRANSMITTER: ...................................................................................... 35
6.3 JITTER GENERATION: .................................................................................................................................. 35
6.4 JITTER ATTENUATOR: ................................................................................................................................. 35
T
ABLE
11: J
ITTER
A
MPLITUDE
VERSUS
M
ODULATION
F
REQUENCY
(J
ITTER
T
OLERANCE
) ......................................................................... 35
T
ABLE
12: J
ITTER
T
RANSFER
S
PECIFICATIONS
...................................................................................................................................... 35
T
ABLE
13: J
ITTER
T
RANSFER
P
ASS
M
ASKS
........................................................................................................................................... 36
F
IGURE
24. J
ITTER
T
RANSFER
R
EQUIREMENTS
AND
J
ITTER
A
TTENUATOR
P
ERFORMANCE
...................................................................... 36
7.0 SERIAL HOST INTERFACE: ............................................................................................................... 37
T
ABLE
14: F
UNCTIONS
OF
SHARED
PINS
................................................................................................................................................ 37
T
ABLE
15: R
EGISTER
M
AP
AND
B
IT
N
AMES
........................................................................................................................................... 37
T
ABLE
16: R
EGISTER
M
AP
D
ESCRIPTION
.............................................................................................................................................. 39
T
ABLE
17: R
EGISTER
M
AP
D
ESCRIPTION
- G
LOBAL
............................................................................................................................... 43
8.0 DIAGNOSTIC FEATURES: ................................................................................................................. 44
8.1 PRBS GENERATOR AND DETECTOR: ........................................................................................................ 44
8.2 LOOPBACKS: ................................................................................................................................................ 44
8.2.1 ANALOG LOOPBACK:............................................................................................................................................... 44
F
IGURE
25. PRBS MODE ................................................................................................................................................................... 44
8.2.2 DIGITAL LOOPBACK:................................................................................................................................................ 45
F
IGURE
26. A
NALOG
L
OOPBACK
........................................................................................................................................................... 45
F
IGURE
27. D
IGITAL
L
OOPBACK
............................................................................................................................................................ 45
8.2.3 REMOTE LOOPBACK:............................................................................................................................................... 46
8.3 TRANSMIT ALL ONES (TAOS): .................................................................................................................... 46
F
IGURE
28. R
EMOTE
L
OOPBACK
........................................................................................................................................................... 46
F
IGURE
29. T
RANSMIT
A
LL
O
NES
(TAOS) ............................................................................................................................................ 46
O
RDERING
I
NFORMATION
............................................................................................................................................. 47
PACKAGE DIMENSIONS ............................................................................................................. 47
R
EVISION
H
ISTORY
...................................................................................................................................................... 48
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