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Exar
Corporation 48720 Kato Road, Fremont CA, 94538
(510) 668-7000
FAX (510) 668-7017
www.exar.com
XRT75L02D
TWO CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
NOVEMBER 2003
REV. 1.0.1
GENERAL DESCRIPTION
The XRT75L02D is a two-channel fully integrated
Line Interface Unit (LIU) with Sonet Desynchronizer
for E3/DS3/STS-1 applications. It incorporates
independent Receivers, Transmitters and Jitter
Attenuators in a single 100 pin TQFP package.
The XRT75L02D can be configured to operate in
either E3 (34.368 MHz), DS3 (44.736 MHz) or STS-1
(51.84 MHz) modes.The transmitter can be turned off
(tri-stated) for redundancy support and for conserving
power.
The XRT75L02D's differential receiver provides high
noise interference margin and is able to receive the
data over 1000 feet of cable or with up to 12 dB of
cable attenuation.
The XRT75L02D incorporates advanced crystal-less
jitter attenuators that can be selected either in the
transmit or receive path. The jitter attenuator
performance meets the ETSI TBR-24 and Bellcore
GR-499 specifications. Also, the jitter attenuator can
be used for clock smoothing in SONET STS-1 to DS3
de-mapping.
The XRT75L02D provides both Serial Microprocessor
Interface as well as Hardware mode for programming
and control.
The XRT75L02D supports local,remote and digital
loop-backs. The XRT75L02D also contains an on-
board Pseudo Random Binary Sequence (PRBS)
generator and detector with the ability to insert and
detect single bit error.
FEATURES
RECEIVER:
On chip Clock and Data Recovery circuit for high
input jitter tolerance.
Meets the jitter tolerance requirements as specified
in ITU-T G.823_1993 for E3 and Telcordia GR-499-
CORE for DS3 applications.
Detects and Clears LOS as per G.775.
Receiver Monitor mode handles up to 20 dB flat
loss with 6 dB cable attenuation.
On chip B3ZS/HDB3 encoder and decoder that can
either be enabled or disabled.
On-chip clock synthesizer generates the
appropriate rate clock from a single frequency
XTAL.
Provides low jitter clock outputs for either DS3,E3
or STS-1 rates.
On-chip clock synthesizer provides the appropriate
rate clock from a single 12.288 MHz Clock.
Provides low jitter output clock.
TRANSMITTER:
Compliant with Bellcore GR-499, GR-253 and ANSI
T1.102 Specification for transmit pulse
Tri-state Transmit output capability for redundancy
applications
Transmitters can be turned on or off.
JITTER ATTENUATOR:
On chip advanced crystal-less Jitter Attenuator.
Jitter Attenuator can be selected in Receive or
Transmit paths.
16 or 32 bits selectable FIFO size.
Meets the Jitter and Wander specifications
described in T1.105.03b,ETSI TBR-24, Bellcore
GR-253 and GR-499 standards.
Jitter Attenuators can be disabled.
CONTROL AND DIAGNOSTICS:
5 wire Serial Microprocessor Interface for control
and configuration.
Supports optional internal Transmit Driver
Monitoring.
PRBS error counter register to accumulate errors.
Hardware Mode for control and configuration.
Supports Local, Remote and Digital Loop-backs.
Single 3.3 V 5% power supply.
5 V Tolerant I/O.
Available in 100 pin TQFP.
-40C to 85C Industrial Temperature Range.
APPLICATIONS
E3/DS3 Access Equipment.
STS1-SPE to DS3 Mapper.
DSLAMs.
Digital Cross Connect Systems.
CSU/DSU Equipment.
Routers.
Fiber Optic Terminals.
XRT75L02D
REV. 1.0.1
TWO CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
2
TRANSMIT INTERFACE CHARACTERISTICS
Accepts either Single-Rail or Dual-Rail data from Terminal Equipment and generates a bipolar signal to the
line
Integrated Pulse Shaping Circuit.
Built-in B3ZS/HDB3 Encoder (which can be disabled).
Accepts Transmit Clock with duty cycle of 30%-70%.
Generates pulses that comply with the ITU-T G.703 pulse template for E3 applications.
Generates pulses that comply with the DSX-3 pulse template, as specified in Bellcore GR-499
-CORE
and
ANSI T1.102_1993.
Generates pulses that comply with the STSX-1 pulse template, as specified in Bellcore GR-253-CORE.
Transmitter can be turned off in order to support redundancy designs.
RECEIVE INTERFACE CHARACTERISTICS
Integrated Adaptive Receive Equalization for optimal Clock and Data Recovery.
Declares and Clears the LOS defect per ITU-T G.775 requirements for E3 and DS3 applications.
Meets Jitter Tolerance Requirements, as specified in ITU-T G.823_1993 for E3 Applications.
Meets Jitter Tolerance Requirements, as specified in Bellcore GR-499-CORE for DS3 Applications.
Declares Loss of Signal (LOS) and Loss of Lock (LOL) Alarms.
Built-in B3ZS/HDB3 Decoder (which can be disabled).
F
IGURE
1. B
LOCK
D
IAGRAM
OF
THE
XRT 75L02D
HOST/HW
STS-1/DS3
E3
REQEN
RTIP
RRING
SR/DR
XRT75L03
RLB
RLOS
JATx/Rx
TPOS
TNEG
TxClk
TAOS
TxLEV
TxON
Note: Serial Processor Interface input pins are shared by in "Host" Mode and redefined in the "Hardware" Mode.
Device
Monitor
MTIP
MRING
DMO
Timing
Control
TTIP
TRING
Tx
Pulse
Shaping
HDB3/
B3ZS
Encoder
RLOL
RxON
RxClkINV
RxClk
RPOS
RNEG/
LCV
Tx
Control
Jitter
Attenuator
MUX
Line
Driver
LLB
Invert
Remote
LoopBack
HDB3/
B3ZS
Decoder
MUX
AGC/
Equalizer
Peak Detector
LOS
Detector
Slicer
Jitter
Attenuator
Serial
Processor
Interface
Local
LoopBack
Clock & Data
Recovery
Clock
Synthesizer
E3Clk,DS3Clk,
STS-1Clk
RESET
CS
SClk
INT
SDO
SDI
CLK_OUT
XRT75L02D
TWO CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
REV. 1.0.1
3
Recovered Data can be muted while the LOS Condition is declared.
Outputs either Single-Rail or Dual-Rail data to the Terminal Equipment.
F
IGURE
2. P
IN
O
UT
OF
THE
XRT75L02D
ORDERING INFORMATION
P
ART
N
UMBER
P
ACKAGE
O
PERATING
T
EMPERATURE
R
ANGE
XRT75L02DIV
14mm x 14mm 100 Pin TQFP
-40
C to +85
C
XRT75L02D
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
TA
O
S
_
0
T
x
L
EV_
0
MR
I
N
G
_
0
MT
I
P
_
0
TR
I
N
G
_
0
TT
I
P
_
0
T
x
DV
DD_0
T
x
DG
ND_
0
DV
DD
E3
C
L
K
DG
N
D
DG
N
D
DS
3CL
K
DV
DD
DV
DD
ST
S1
C
L
K/
SF
M
C
L
K
DG
N
D
T
x
DG
ND_
1
T
x
DV
DD_1
TT
I
P
_
1
TR
I
N
G
_
1
MT
I
P
_
1
MR
I
N
G
_
1
T
x
L
EV_
1
TA
O
S
_
1
RE
Q
E
N_0
E3
_
0
ST
S1
/
D
S3
_
0
LL
B
_
0
RLB
_
0
Rx
A
V
D
D_
0
Rx
A
G
ND
_
0
RR
I
N
G
_
0
RT
I
P
_
0
AG
N
D
Rx
A
Rx
B
AVD
D
JA_
0
JA_
1
JAT
x
/
R
x
RT
I
P
_
1
RR
I
N
G
_
1
Rx
A
G
ND
_
1
Rx
A
V
D
D_
1
RLB
_
1
LL
B
_
1
ST
S1
/
D
S3
_
1
E3
_
1
RE
Q
E
N_1
TNEG_1
TPOS_1
TxCLK_1
DMO_1
CLKOUT_1
CLKOUT_EN
TxAGND_1
TxAVDD_1
JAAGND_1
JAAVDD_1
JADVDD_1
JADGND_1
DVDD_1
DGND_1
RxCLK_1
RPOS_1
RNEG/LCV_1
RLOS_1
RLOL_1
SDI/RxON
SCLK/TxCLKINV
CS/RxCLKINV
INT/LOSMUT
SDO/RxMON
HOST/HW
TNEG_0
TPOS_0
TxCLK_0
DMO_0
CLKOUT_0
TxON
TxMON
TxAGND_0
TxAVDD_0
JAAGND_0
JAAVDD_0
JADVDD_0
JADGND_0
RxDVDD_0
RxDGND_0
RxCLK_0
RPOS_0
RNEG/LCV_0
RLOS_0
RLOL_0
TEST
RESET
ICT
SFM_EN
SR/DR
XRT75L02D
TWO CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
REV. 1.0.1
I
TABLE OF CONTENTS
GENERAL DESCRIPTION................................................................................................. 1
F
EATURES
..................................................................................................................................................... 1
A
PPLICATIONS
............................................................................................................................................... 1
T
RANSMIT
I
NTERFACE
C
HARACTERISTICS
....................................................................................................... 2
R
ECEIVE
I
NTERFACE
C
HARACTERISTICS
......................................................................................................... 2
F
IGURE
1. B
LOCK
D
IAGRAM
OF
THE
XRT 75L02D............................................................................................................................ 2
F
IGURE
2. P
IN
O
UT
OF
THE
XRT75L02D ......................................................................................................................................... 3
ORDERING INFORMATION .................................................................................................................... 3
PIN DESCRIPTIONS (BY FUNCTION) ............................................................................ 4
T
RANSMIT
I
NTERFACE
.................................................................................................................................... 4
R
ECEIVE
I
NTERFACE
...................................................................................................................................... 6
C
LOCK
I
NTERFACE
......................................................................................................................................... 8
CONTROL AND ALARM INTERFACE........................................................................................................ 9
M
ODE
S
ELECT
............................................................................................................................................ 11
M
ICROPROCESSOR
S
ERIAL
INTERFACE - (HOST MODE)......................................................................... 11
J
ITTER
A
TTENUATOR
INTERFACE
.................................................................................................................. 12
A
NALOG
P
OWER
AND
G
ROUND
.................................................................................................................... 13
DIGITAL
P
OWER
AND
G
ROUND
...................................................................................................................... 13
1.0 ELECTRICAL CHARACTERISTICS ................................................................................................... 15
T
ABLE
1: A
BSOLUTE
M
AXIMUM
R
ATINGS
......................................................................................................................................... 15
T
ABLE
2: DC E
LECTRICAL
C
HARACTERISTICS
: ................................................................................................................................ 15
2.0 TIMING CHARACTERISTICS .............................................................................................................. 16
F
IGURE
3. T
YPICAL
INTERFACE
BETWEEN
TERMINAL
EQUIPMENT
AND
THE
XRT75L02D (
DUAL
-
RAIL
DATA
) ........................................ 16
F
IGURE
4. T
RANSMITTER
T
ERMINAL
I
NPUT
T
IMING
.......................................................................................................................... 16
F
IGURE
5. R
ECEIVER
D
ATA
OUTPUT
AND
CODE
VIOLATION
TIMING
................................................................................................... 17
F
IGURE
6. T
RANSMIT
I
NTERFACE
CIRCUIT
FOR
E3, DS3
AND
STS-1 R
ATES
.................................................................................... 17
3.0 LINE SIDE CHARACTERISTICS: ....................................................................................................... 18
3.1 E3 LINE SIDE PARAMETERS: ...................................................................................................................... 18
F
IGURE
7. P
ULSE
M
ASK
FOR
E3 (34.368
MBITS
/
S
)
INTERFACE
AS
PER
ITU
-
T
G.703......................................................................... 18
T
ABLE
3: E3 T
RANSMITTER
LINE
SIDE
OUTPUT
AND
RECEIVER
LINE
SIDE
INPUT
SPECIFICATIONS
....................................................... 18
F
IGURE
8. B
ELLCORE
GR-253 CORE T
RANSMIT
O
UTPUT
P
ULSE
T
EMPLATE
FOR
SONET STS-1 A
PPLICATIONS
............................ 19
T
ABLE
4: STS-1 P
ULSE
M
ASK
E
QUATIONS
..................................................................................................................................... 19
T
ABLE
5: STS-1 T
RANSMITTER
L
INE
S
IDE
O
UTPUT
AND
R
ECEIVER
L
INE
S
IDE
I
NPUT
S
PECIFICATIONS
(GR-253) .............................. 20
F
IGURE
9. T
RANSMIT
O
UPUT
P
ULSE
T
EMPLATE
FOR
DS3
AS
PER
B
ELLCORE
GR-499 ..................................................................... 20
T
ABLE
6: DS3 P
ULSE
M
ASK
E
QUATIONS
........................................................................................................................................ 21
T
ABLE
7: DS3 T
RANSMITTER
L
INE
S
IDE
O
UTPUT
AND
R
ECEIVER
L
INE
S
IDE
I
NPUT
S
PECIFICATIONS
(GR-499) ................................. 21
F
IGURE
10. M
ICROPROCESSOR
S
ERIAL
I
NTERFACE
S
TRUCTURE
..................................................................................................... 22
F
IGURE
11. T
IMING
D
IAGRAM
FOR
THE
M
ICROPROCESSOR
S
ERIAL
I
NTERFACE
................................................................................ 22
T
ABLE
8: M
ICROPROCESSOR
S
ERIAL
I
NTERFACE
T
IMINGS
( TA = 250C, VDD=3.3V 5%
AND
LOAD
= 10
P
F).................................. 23
4.0 THE TRANSMITTER SECTION: ......................................................................................................... 24
4.1 TRANSMIT CLOCK: ....................................................................................................................................... 24
4.2 B3ZS/HDB3 ENCODER: ................................................................................................................................ 24
4.2.1 B3ZS ENCODING: ...................................................................................................................................................... 24
F
IGURE
12. S
INGLE
-R
AIL
OR
NRZ D
ATA
F
ORMAT
(E
NCODER
AND
D
ECODER
ARE
E
NABLED
)............................................................ 24
F
IGURE
13. D
UAL
-R
AIL
D
ATA
F
ORMAT
(
ENCODER
AND
DECODER
ARE
DISABLED
) ............................................................................. 24
4.2.2 HDB3 ENCODING:...................................................................................................................................................... 25
4.3 TRANSMIT PULSE SHAPER: ........................................................................................................................ 25
F
IGURE
14. B3ZS E
NCODING
F
ORMAT
........................................................................................................................................... 25
F
IGURE
15. HDB3 E
NCODING
F
ORMAT
.......................................................................................................................................... 25
4.3.1 GUIDELINES FOR USING TRANSMIT BUILD OUT CIRCUIT: ................................................................................. 26
4.3.2 INTERFACING TO THE LINE:.................................................................................................................................... 26
4.4 TRANSMIT DRIVE MONITOR: ....................................................................................................................... 26
F
IGURE
16. T
RANSMIT
D
RIVER
M
ONITOR
SET
-
UP
. ........................................................................................................................... 26
4.5 TRANSMITTER SECTION ON/OFF: .............................................................................................................. 27
5.0 THE RECEIVER SECTION: ................................................................................................................. 28
5.1 AGC/EQUALIZER: .......................................................................................................................................... 28
5.1.1 INTERFERENCE TOLERANCE: ................................................................................................................................ 28
F
IGURE
17. I
NTERFERENCE
M
ARGIN
T
EST
S
ET
UP
FOR
DS3/STS-1................................................................................................ 28
XRT75L02D
REV. 1.0.1
TWO CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
II
5.2 CLOCK AND DATA RECOVERY: .................................................................................................................. 29
5.3 B3ZS/HDB3 DECODER: ................................................................................................................................. 29
F
IGURE
18. I
NTERFERENCE
M
ARGIN
T
EST
S
ET
UP
FOR
E3.............................................................................................................. 29
T
ABLE
9: I
NTERFERENCE
M
ARGIN
T
EST
R
ESULTS
........................................................................................................................... 29
5.4 LOS (LOSS OF SIGNAL) DETECTOR: .......................................................................................................... 30
5.4.1 DS3/STS-1 LOS CONDITION: .................................................................................................................................... 30
D
ISABLING
ALOS/DLOS D
ETECTION
:...........................................................................................................30
5.4.2 E3 LOS CONDITION:.................................................................................................................................................. 30
T
ABLE
10: T
HE
ALOS (A
NALOG
LOS) D
ECLARATION
AND
C
LEARANCE
T
HRESHOLDS
FOR
A
GIVEN
SETTING
OF
REQEN (DS3
AND
STS-1
A
PPLICATIONS
) ............................................................................................................................................................... 30
5.4.3 MUTING THE RECOVERED DATA WITH LOS CONDITION: ................................................................................... 31
F
IGURE
19. L
OSS
O
F
S
IGNAL
D
EFINITION
FOR
E3
AS
PER
ITU-T G.775 .......................................................................................... 31
F
IGURE
20. L
OSS
OF
S
IGNAL
D
EFINITION
FOR
E3
AS
PER
ITU-T G.775. ......................................................................................... 31
6.0 JITTER: ................................................................................................................................................32
6.1 JITTER TOLERANCE - RECEIVER: .............................................................................................................. 32
6.1.1 DS3/STS-1 JITTER TOLERANCE REQUIREMENTS: ............................................................................................... 32
F
IGURE
21. J
ITTER
T
OLERANCE
M
EASUREMENTS
............................................................................................................................ 32
6.1.2 E3 JITTER TOLERANCE REQUIREMENTS:............................................................................................................. 33
F
IGURE
22. I
NPUT
J
ITTER
T
OLERANCE
F
OR
DS3/STS-1 ................................................................................................................ 33
F
IGURE
23. I
NPUT
J
ITTER
T
OLERANCE
FOR
E3 .............................................................................................................................. 33
6.2 JITTER TRANSFER - RECEIVER/TRANSMITTER: ...................................................................................... 34
6.3 JITTER GENERATION: .................................................................................................................................. 34
6.4 JITTER ATTENUATOR: ................................................................................................................................. 34
T
ABLE
11: J
ITTER
A
MPLITUDE
VERSUS
M
ODULATION
F
REQUENCY
(J
ITTER
T
OLERANCE
)................................................................... 34
T
ABLE
12: J
ITTER
T
RANSFER
S
PECIFICATION
/R
EFERENCES
............................................................................................................. 34
7.0 SERIAL HOST INTERFACE: ...............................................................................................................35
T
ABLE
13: J
ITTER
T
RANSFER
P
ASS
M
ASKS
.................................................................................................................................... 35
F
IGURE
24. J
ITTER
T
RANSFER
R
EQUIREMENTS
AND
J
ITTER
A
TTENUATOR
P
ERFORMANCE
................................................................ 35
T
ABLE
14: F
UNCTIONS
OF
SHARED
PINS
......................................................................................................................................... 36
T
ABLE
15: R
EGISTER
M
AP
AND
B
IT
N
AMES
.................................................................................................................................... 36
T
ABLE
16: R
EGISTER
M
AP
D
ESCRIPTION
- G
LOBAL
......................................................................................................................... 37
T
ABLE
17: R
EGISTER
M
AP
AND
B
IT
N
AMES
- C
HANNEL
0 R
EGISTERS
.............................................................................................. 37
T
ABLE
18: R
EGISTER
M
AP
AND
B
IT
N
AMES
- C
HANNEL
1 R
EGISTERS
.............................................................................................. 38
T
ABLE
19: R
EGISTER
M
AP
D
ESCRIPTION
- C
HANNEL
0.................................................................................................................... 39
8.0 DIAGNOSTIC FEATURES: ..................................................................................................................43
8.1 PRBS GENERATOR AND DETECTOR: ........................................................................................................ 43
8.2 LOOPBACKS: ................................................................................................................................................. 43
8.2.1 ANALOG LOOPBACK:............................................................................................................................................... 43
F
IGURE
25. PRBS MODE ............................................................................................................................................................. 43
8.2.2 DIGITAL LOOPBACK: ................................................................................................................................................ 44
8.2.3 REMOTE LOOPBACK: ............................................................................................................................................... 44
F
IGURE
26. A
NALOG
L
OOPBACK
..................................................................................................................................................... 44
F
IGURE
27. D
IGITAL
L
OOPBACK
...................................................................................................................................................... 44
8.3 TRANSMIT ALL ONES (TAOS): .................................................................................................................... 45
F
IGURE
28. R
EMOTE
L
OOPBACK
.................................................................................................................................................... 45
F
IGURE
29. T
RANSMIT
A
LL
O
NES
(TAOS) ...................................................................................................................................... 45
9.0 THE SONET/SDH DE-SYNC FUNCTION WITHIN THE LIU ...............................................................46
9.1 BACKGROUND AND DETAILED INFORMATION - SONET DE-SYNC APPLICATIONS ............................ 46
F
IGURE
30. A S
IMPLE
I
LLUSTRATION
OF
A
DS3
SIGNAL
BEING
MAPPED
INTO
AND
TRANSPORTED
OVER
THE
SONET N
ETWORK
........ 47
9.2 MAPPING/DE-MAPPING JITTER/WANDER ................................................................................................. 48
9.2.1 HOW DS3 DATA IS MAPPED INTO SONET ............................................................................................................. 48
9.2.1.1 A B
RIEF
D
ESCRIPTION
OF
AN
STS-1 F
RAME
......................................................................................................... 48
F
IGURE
31. A S
IMPLE
I
LLUSTRATION
OF
THE
SONET STS-1 F
RAME
.............................................................................................. 49
F
IGURE
32. A S
IMPLE
I
LLUSTRATION
OF
THE
STS-1 F
RAME
S
TRUCTURE
WITH
THE
TOH
AND
THE
E
NVELOPE
C
APACITY
B
YTES
D
ESIGNATED
50
F
IGURE
33. T
HE
B
YTE
-F
ORMAT
OF
THE
TOH
WITHIN
AN
STS-1 F
RAME
.......................................................................................... 51
F
IGURE
34. T
HE
B
YTE
-F
ORMAT
OF
THE
TOH
WITHIN
AN
STS-1 F
RAME
.......................................................................................... 52
9.2.1.2 M
APPING
DS3
DATA
INTO
AN
STS-1 SPE ............................................................................................................ 53
F
IGURE
35. I
LLUSTRATION
OF
THE
B
YTE
S
TRUCTURE
OF
THE
STS-1 SPE....................................................................................... 53
F
IGURE
36. A
N
I
LLUSTRATION
OF
T
ELCORDIA
GR-253-CORE'
S
R
ECOMMENDATION
ON
HOW
MAP
DS3
DATA
INTO
AN
STS-1 SPE... 54
F
IGURE
37. A S
IMPLIFIED
"B
IT
-O
RIENTED
" V
ERSION
OF
T
ELCORDIA
GR-253-CORE'
S
R
ECOMMENDATION
ON
HOW
TO
MAP
DS3
DATA
INTO
AN
STS-1 SPE .............................................................................................................................................................. 54
9.2.2 DS3 FREQUENCY OFFSETS AND THE USE OF THE "STUFF OPPORTUNITY" BITS ......................................... 55
9.2.2.1 T
HE
I
DEAL
C
ASE
FOR
M
APPING
DS3
DATA
INTO
AN
STS-1 S
IGNAL
(
E
.
G
.,
WITH
NO
F
REQUENCY
O
FFSETS
) ............ 56
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