Exar
Corporation 48720 Kato Road, Fremont CA, 94538
(510) 668-7000
FAX (510) 668-7017
www.exar.com
XRT8010
312MHZ CLOCK & CRYSTAL MULTIPLIER WITH LVDS OUTPUTS
NOVEMBER 2003
REV. 1.0.2
DESCRIPTION
The XRT8010 is a monolithic analog phase locked
loop that provides a high frequency LVDS clock
output, using a low frequency crystal or reference
clock. It is designed for SONET/SDH and other low
jitter applications.The high performance of the IC
provides a very low jitter LVDS clock output up to 320
MHz, while operating at 3.3 volts. The XRT8010 has
a selectable 8x or 16x internal multiplier for an
external crystal or signal source. The Output Enable
pin provides a true disconnect for the LVDS output.
The very compact (4 x 4 mm) low inductance
package is ideal for high frequency operation.
APPLICATIONS
Gigabit Ethernet
SONET/SDH
SPI-4 Phase 2
8x or 16x Clock Multiplier for
s
Computer
s
Telecommunications Sytems
FEATURES
156 or 320 MHz Operating Range
Low Output Jitter:
s
0.0009 UI
RMS
typical @ 155.52 MHz, per
Telcordia GR-253-CORE for OC-3.
On Chip Crystal Oscillator Circuit
s
Optimized for 15 to 40 MHz crystals
s
Uses parallel fundamental mode
Selectable 8x or 16x multiplier
Selectable 1 or 2 LVDS output
LVDS output meets TIA/EIA 644A Specification
(2001)
3.3V Low power CMOS: <80 mW typical
-40C to +85C operating temperature
Extremely small 16-lead QFN package
F
IGURE
1. XRT8010 B
LOCK
D
IAGRAM
O
G N D
FS 1
O E
A G N D
P D
A G N D
(C ry stal)
FS 0
A G N D
15-40 M H z
C rys tal
X T A L1
X TA L2
O sc illator
C ircuit &
Input B uffer
V C O
C alibration Logic
P has e
D etec tor
C harge
P um p
Loop
Filter
V C O
S electable
1 or
2
D iv ider
LV D S O utput
F eedbac k D iv ider
8 or 16
V oltage R eferenc e
&
B ias G enerator
R
E X T
10k
A V
D D
A V
D D
O V
D D
+3.3V
1 2 - 2 0 p F
1 2 - 2 0 p F
X R T 801 0
O U TP
O U TN
XRT8010
312MHZ CLOCK & CRYSTAL MULTIPLIER WITH LVDS OUTPUTS
REV. 1.0.2
2
F
IGURE
2. P
IN
-O
UT OF THE
XRT8010 (T
OP
V
IEW
)
ORDERING INFORMATION
P
ART
N
UMBER
P
ACKAGE
T
YPE
O
PERATING
T
EMPERATURE
R
ANGE
XRT8010IL
16 LEAD QUAD FLAT NO LEAD
(4 mm x 4 mm, QFN)
-40C to +85C
1
2
3
4
12
11
10
9
16
15
14
13
5
6
7
8
XRT8010
XRT8010
312MHZ CLOCK & CRYSTAL MULTIPLIER WITH LVDS OUTPUTS
REV. 1.0.2
I
TABLE OF CONTENTS
DESCRIPTION....................................................................................................................1
APPLICATIONS ...........................................................................................................................................1
FEATURES ..................................................................................................................................................1
F
IGURE
1. XRT8010 B
LOCK
D
IAGRAM
............................................................................................................................................. 1
F
IGURE
2. P
IN
-O
UT OF THE
XRT8010 (T
OP
V
IEW
) ........................................................................................................................... 2
O
RDERING
I
NFORMATION
...................................................................................................................... 2
T
ABLE OF
C
ONTENTS
............................................................................................................I
ABSOLUTE MAXIMUM RATINGS
.........................................................................................................................3
ELECTRICAL CHARACTERISTICS
.......................................................................................................................3
T
ABLE
1: C
ATEGORY
II I
NTRINSIC
J
ITTER
P
ER
T
ELCORDIA
GR-253-CORE (
AT
155MH
Z
) .................................................................. 4
F
IGURE
3. LVDS O
UTPUT
W
AVEFORMS AND
T
EST
C
IRCUITS
............................................................................................................ 5
T
ABLE
2: F
REQUENCY
S
ELECTION
T
ABLE
......................................................................................................................................... 5
1.0 CALIBRATION .......................................................................................................................................6
2.0 CRYSTAL SELECTION .........................................................................................................................6
3.0 DATA AND PLOTS ................................................................................................................................6
T
ABLE
3: P
OWER
-
DOWN AND
O
UTPUT TRI
-
STATE SELECTION TABLE
................................................................................................... 6
F
IGURE
4. I
NTRINSIC
J
ITTER
C
ONNECTION
D
IAGRAM
......................................................................................................................... 7
F
IGURE
5. S
IMPLIFIED
B
LOCK
D
IAGRAM OF THE
XRT8010
AND
PECL R
ECEIVER
.............................................................................. 7
F
IGURE
6. LVDS O
UTPUT
@160 MH
Z
............................................................................................................................................. 8
F
IGURE
7. LVDS O
UTPUT
@ 320 MH
Z
............................................................................................................................................ 9
F
IGURE
8. XRT8010 P
HASE
N
OISE FOR
20 MH
Z
R
EFERENCE
C
RYSTAL
......................................................................................... 10
ORDERING INFORMATION.............................................................................................11
R
EVISIONS
...................................................................................................................................................12
XRT8010
312MHZ CLOCK & CRYSTAL MULTIPLIER WITH LVDS OUTPUTS
REV. 1.0.2
3
PIN DESCRIPTION
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
P
IN
N
AME
T
YPE
D
ESCRIPTION
1
AVDD
3.3V 10% Analog Supply for Crystal Oscillator
2
AGND
Analog Ground for Crystal Oscillator
3
XTAL1
I
Crystal pin 1 or external clock input
4
XTAL2
O
Crystal pin 2 (output drive for crystal)
5
AGND
Analog Ground
6
REXT
I
External Bias Resistor (10K
to ground)
7
OE
I
Output Enable, Active low (
Internal 50K
pull-down to ground)
8
PD
I
Power Down, Active High
(Internal 50K
pull-down to ground)
9
FS1
I
Frequency select "1"
(Internal 50K
pull-down to ground)
10
FS0
I
Frequency select "0"
(Internal 50K
pull-up to VDD)
11
AGND
Analog Ground
12
OGND
Output Ground for LVDS outputs
13
OUTN
O
LVDS negative output for 50
line
14
OUTP
O
LVDS positive output for 50
line
15
OVDD
3.3V 10% Digital Supply for LVDS Output buffer
16
AVDD
3.3V 10% Analog Supply
Supply voltage
-0.5 to 6.0 V
VIN
-0.5 to 6.0 V
Storage Temperature
-65C to + 150C
Operating Temperature
-40C to + 85C
ESD
2,000 volts
P
ARAMETER
S
YMBOL
M
IN
T
YP
M
AX
U
NIT
C
ONDITIONS
Supply Voltage
VDD
3.0
3.3
3.6
V
Supply current
IDD
20
25
mA
Input Digital High
VINH
2.0
V
Input Digital Low
VINL
0.8
V
Crystal Frequency
15
27
MHz
See Section 2,0 for Crystal Selection
Crystal Frequency
27
40
MHz
See Section 2,0 for Crystal Selection
XRT8010
REV. 1.0.2
312MHZ CLOCK & CRYSTAL MULTIPLIER WITH LVDS OUTPUTS
4
Power on Calibration time
5
ms
After VDD reaches 2.8V
N
OTE
: Calibration time
= 16,000 clock
cycles
Max Frequency Out
FOUT
140
170
MHz
156 MHz nominal FOUT (see Table 1)
Max Frequency Out
FOUT
285
340
MHz
312 MHz nominal FOUT (see Table 1)
Rise time
TR
300
ps
CL = 5pF, RL = 100
(20% - 80%)
Fall Time
TF
300
ps
CL = 5pF, RL = 100
(20% - 80%)
Duty cycle
45
55
%
LVDS output
Differential Output Skew
10
ps
See Figure 3
Output Loading
100
Output voltage Swing
250
450
mV
Differential (OUTP-OUTN)
Common Mode Voltage
VCM
1.2
V
Output short circuit current
-5.7
-8
mA
Current limit to ground, VDD or Vp to Vn
Cycle-to-Cycle Jitter
3
ps
rms, at 156 MHz, Input referred
Cycle-to-Cycle Jitter
3
ps
rms, at 312 MHz, Input referred
Intinsic Jitter
16
ps
rms, over 1,000 cycles, at 156 MHz
Intinsic Jitter
16
ps
rms, over 1,000 cycles, at 312 MHz
Spectral Density of Phase
Noise
L
(f)
P
ARAMETER
C
OVERSION
T
YPICAL
Single Side Band Phase Noise
L
(f)
320MHz @ 100Hz Offset
-77.75 dbc/Hz
320MHz @ 1kHz Offset
-100.69 dbc/Hz
320MHz @ 10kHz Offset
-95.38 dbc/Hz
320MHz @ 100kHz Offset
-99.40 dbc/Hz
320MHz @ 1MHz Offset
-105.05 dbc/Hz
320MHz @ 10MHz Offset
-119.03 dbc/Hz
T
ABLE
1: C
ATEGORY
II I
NTRINSIC
J
ITTER
P
ER
T
ELCORDIA
GR-253-CORE (
AT
155MH
Z
)
J
ITTER
B
ANDWIDTH
J
ITTER
(RMS)
J
ITTER
(UI
RMS
)
12kHz - 1.3MHz
5.74
0.0009
12kHz - 5MHz
7.89
0.0012
12kHz - 20MHz
8.99
0.0014
P
ARAMETER
S
YMBOL
M
IN
T
YP
M
AX
U
NIT
C
ONDITIONS
XRT8010
312MHZ CLOCK & CRYSTAL MULTIPLIER WITH LVDS OUTPUTS
REV. 1.0.2
5
F
IGURE
3. LVDS O
UTPUT
W
AVEFORMS AND
T
EST
C
IRCUITS
T
ABLE
2: F
REQUENCY
S
ELECTION
T
ABLE
FS0P
IN
10
FS1P
IN
9
C
RYSTAL
F
REQUENCY
I
NTERNAL
C
APACITOR
M
ULTIPLY
R
ATIO
O
UTPUT
D
IVIDE
F
REQUENCY
O
UTPUT
1
1
39.0 MHz
12 pF
8x
1
312 MHz
0
1
39.0 MHz
12 pF
8x
2
156 MHz
1
0
19.5 MHz
20 pF
16x
1
312 MHz
0
0
19.5 MHz
20 pF
16x
2
156 MHz
N
OTES
:
1.
Use Parallel Fundamental mode crystal
2.
FS0 has a 50K
pull-up resistor to VDD on chip
3.
FS1 has a 50K
pull-down resistor to ground on chip
XRT8010
REV. 1.0.2
312MHZ CLOCK & CRYSTAL MULTIPLIER WITH LVDS OUTPUTS
6
1.0
CALIBRATION
The XRT8010 synthesizer jitter performance is optimized by calibration of its Voltage Controlled Oscillator
(VCO) upon initial power application. This power ON calibration procedure is automatic and completely trans-
parent to the user. It is initiated automatically upon first application of VDD. In order to bring the center fre-
quency of the VCO close to the desired output frequency, the VCO bias current is adjusted via a current DAC
at initial power application. The center frequency of VCO is checked against input reference frequency and cal-
ibrated internally to the desired output frequency value. These bias voltage trim bits are then held in latches for
as long as the VDD is held above 2.7V (minimum specified operational value of VDD). The user should note
the following important facts about this calibration procedure for proper operation of the XRT8010:
For proper operation of the chip and to achieve lowest jitter, the user should follow layout guidelines as
described in the User Guide.
An input crystal of appropriate frequency should be connected at XTAL1 and XTAL2 pins before power is
applied to the chip.
All VDD pins should be tied to 3.3V 10% simultaneously.
The power supply should turn on without bouncing below 2.0V smoothly to its specified value in no more
than 50msec.
The calibration takes place during VDD ramp up between 2.6V to 3V values. Once the VDD reaches and
maintains 3.0V, the chip retains the calibrated VCO bias voltages in internal latches for proper operation.
To change a widely different value of crystal or input reference frequency, it is recommended to power
down the chip by bringing VDD to 0V and restarting after the change in frequency has occurred.
2.0
CRYSTAL SELECTION
It is recommended that a Fundamental Mode Crystal be used as the timing reference of the XRT8010. The fol-
lowing part has been qualified by EXAR:
CITIZEN Quartz Crystals
20 MHz : HCM49-20.000MABJT
40 MHz : HCM49-40.000MABJT
3.0
DATA AND PLOTS
All plots were recorded using the following parameters and test setup:
VDD = 3.3 V
2" 100
Differential Transmission Lines (from LVDS outputs to receiver inputs)
Fundamental Mode Crystal of 20 MHz
Vref = 1.5 V (PECL Receiver)
T
ABLE
3: P
OWER
-
DOWN AND
O
UTPUT TRI
-
STATE SELECTION TABLE
PD P
IN
8
OE P
IN
7
S
TATUS
N
OTES
1
X
Outputs tri-stated and chip Powered-down "X" = don't care
0
1
Output tri-stated
PD and OE have a 50K
pull-down resistor to ground
on chip
XRT8010
312MHZ CLOCK & CRYSTAL MULTIPLIER WITH LVDS OUTPUTS
REV. 1.0.2
7
F
IGURE
4. I
NTRINSIC
J
ITTER
C
ONNECTION
D
IAGRAM
F
IGURE
5. S
IMPLIFIED
B
LOCK
D
IAGRAM OF THE
XRT8010
AND
PECL R
ECEIVER
X R T 8 0 1 0
C h a n n e l 1
C h a n n e l 2
(u s e d a s T rig g e r)
M A X 9 1 1 1 E S A
T e k t r o n ix
T D S 7 4 0 4
T e k t r o n ix
P 6 3 3 0 D if f e r e n tia l P r o b e
T e k t r o n ix
P 6 2 4 5 T D S 5 0 0 / 6 0 0
O u t P
O u t N
2 0 . 0 M h z
C r y s t a l
XRT8010/20
Clock Synthesizer
LVDS-To-PECL
Receiver
100ohm Differential
Transmission Line
XRT8010
REV. 1.0.2
312MHZ CLOCK & CRYSTAL MULTIPLIER WITH LVDS OUTPUTS
8
F
IGURE
6. LVDS O
UTPUT
@160 MH
Z
XRT8010
312MHZ CLOCK & CRYSTAL MULTIPLIER WITH LVDS OUTPUTS
REV. 1.0.2
9
F
IGURE
7. LVDS O
UTPUT
@ 320 MH
Z
XRT8010
REV. 1.0.2
312MHZ CLOCK & CRYSTAL MULTIPLIER WITH LVDS OUTPUTS
10
F
IGURE
8. XRT8010 P
HASE
N
OISE FOR
20 MH
Z
R
EFERENCE
C
RYSTAL
XRT8010
312MHZ CLOCK & CRYSTAL MULTIPLIER WITH LVDS OUTPUTS
REV. 1.0.2
11
ORDERING INFORMATION
PACKAGE DIMENSIONS
P
ART
N
UMBER
P
ACKAGE
O
PERATING
T
EMPERATURE
R
ANGE
XRT8010IL
16 LEAD QUAD FLAT NO LEAD
(4 mm x 4 mm, QFN)
-40
C to +85
C
16 LEAD QUAD FLAT NO LEAD
(4 mm x 4 mm, 0.65 pitch QFN)
Note: The control dimension is in millimeter.
MIN
MAX
MIN
MAX
A
0.031
0.039
0.80
1.00
A1
0.000
0.002
0.00
0.05
A2
0.000
0.039
0.00
1.00
D
0.154
0.161
3.90
4.10
D1
0.144
0.152
3.65
3.85
D2
0.088
0.100
2.24
2.54
b
0.009
0.015
0.23
0.38
e
0.0256 BSC
0.65 BSC
L
0.014
0.030
0.35
0.75
0
12
0
12
SYMBOL
INCHES
MILLIMETERS
Rev. 1.01
Note: the actual center pad
is metallic and the size (D2)
is device-dependent w/ a
typical tolerance of 0.3mm
XRT8010
312MHZ CLOCK & CRYSTAL MULTIPLIER WITH LVDS OUTPUTS
REV. 1.0.2
12
NOTICE
EXAR Corporation reserves the right to make changes to the products contained in this publication in order
to improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of
any circuits described herein, conveys no license under any patent or other right, and makes no represen-
tation that the circuits are free of patent infringement. Charts and schedules contained here in are only for
illustration purposes and may vary depending upon a user's specific application. While the information in
this publication has been carefully checked; no responsibility, however, is assumed for inaccuracies.
EXAR Corporation does not recommend the use of any of its products in life support applications where
the failure or malfunction of the product can reasonably be expected to cause failure of the life support sys-
tem or to significantly affect its safety or effectiveness. Products are not authorized for use in such applica-
tions unless EXAR Corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury
or damage has been minimized; (b) the user assumes all such risks; (c) potential liability of EXAR Corpo-
ration is adequately protected under the circumstances.
Copyright 2003 EXAR Corporation
Datasheet November 2003.
Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited.
REVISIONS
P1.0.0 Original issue.
P1.0.1 Modified Electrical Characteristics. Modified Figures
1.0.0 Final release. Added Category II intrinsic jitter measurements per Telcordia GR-253-CORE.
1.0.1 Changed the Page Numbering.
1.0.2 Changed the Package Drawing and Dimensions.
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