Exar
Corporation 48720 Kato Road, Fremont CA, 94538
(510) 668-7000
FAX (510) 668-7017
www.exar.com
XRT8020
650 MHZ CLOCK & CRYSTAL MULTIPLIER WITH LVDS OUTPUTS
NOVEMBER 2003
REV. 1.0.2
DESCRIPTION
The XRT8020 is a monolithic analog phase locked
loop that provides a high frequency LVDS clock out-
put, using a low frequency crystal or reference clock.
It is designed for SONET/SDH and other low jitter ap-
plications.The high performance of the IC provides a
very low jitter LVDS clock output up to 650 MHz, while
operating at 3.3 volts. The XRT8020 has a selectable
8x, 16x or 32x internal multiplier for an external crys-
tal or signal source. The Output Enable pin provides
a true disconnect for the LVDS output. The very com-
pact (4 x 4 mm) low inductance package is ideal for
high frequency operation.
APPLICATIONS
Gigabit Ethernet
SONET/SDH
SPI - 4 Phase 2
8x, 16x or 32x Clock Multiplier for Computer and
Telecommunication Systems
FEATURES
575 MHz to 675 MHz operating range
Low Output Jitter: 9ps rms typical at 622 MHz
On Chip Crystal Oscillator Circuit
Optimized for 15 to 40 MHz crystals
Uses parallel fundamental mode crystal
Selectable 8x, 16x or 32x multiplier
Selectable
1 or
2 LVDS output
LVDS output meets TIA/EIA 644A Specification
(2001)
3.3V 10% Low power CMOS: 80 mW typical
-40C to +85C operating temperature
Extremely small 16-lead QFN package
F
IGURE
1. B
LOCK
D
IAGRAM OF THE
XRT8020
O
GND
FS1
OE
AGND
PD
AGND
(Crystal)
FS0
AGND
15-40 MHz
Crystal
XTAL1
XTAL2
Oscillator
Circuit &
Input Buffer
VCO
Calibration Logic
Phase
Detector
Charge
Pump
Loop
Filter
VCO
Selectable
1 or
2
Divider
LVDS Output
Feedback Divider
8, 16 or 32
Voltage Reference
&
Bias Generator
R
EXT
10k
AV
DD
AV
DD
OV
DD
+3.3V
12 - 20 pF
12 - 20 pF
XRT8020
OUTP
OUTN
XRT8020
650 MHZ CLOCK & CRYSTAL MULTIPLIER WITH LVDS OUTPUTS
REV. 1.0.2
2
ORDERING INFORMATION
F
IGURE
2. XRT8020 P
IN
L
OCATION
- (T
OP
V
IEW
)
P
ART
N
UMBER
P
ACKAGE
O
PERATING
T
EMPERATURE
R
ANGE
XRT8020IL
16 - Pin QFN
-40
C to +85
C
1
2
3
4
12
11
10
9
16
15
14
13
5
6
7
8
XRT8020
XRT8020
650 MHZ CLOCK & CRYSTAL MULTIPLIER WITH LVDS OUTPUTS
REV. 1.0.2
I
DESCRIPTION .................................................................................................................... 1
APPLICATIONS ......................................................................................................................................... 1
FEATURES ................................................................................................................................................ 1
Figure 1. Block Diagram of the XRT8020 ........................................................................................ 1
ORDERING INFORMATION ............................................................................................................... 2
Figure 2. XRT8020 Pin Location - (Top View) ................................................................................. 2
ABSOLUTE MAXIMUM RATINGS
....................................................................................................................... 3
ELECTRICAL CHARACTERISTICS
..................................................................................................................... 3
Figure 3. LVDS Output Waveforms and Test Circuits .................................................................... 5
1.0 Calibration ................................................................................................................................................. 5
T
ABLE
1: F
REQUENCY
S
ELECTION
T
ABLE
.............................................................................................. 5
T
ABLE
2: P
OWER
-
DOWN AND
O
UTPUT TRI
-
STATE SELECTION TABLE
....................................................... 5
2.0 Crystal selection ....................................................................................................................................... 6
3.0 data and plots ........................................................................................................................................... 6
Figure 4. Input Referenced Jitter Connection Diagram ................................................................. 6
Figure 5. Simplified Block Diagram of the XRT8020 and PECL Receiver .................................... 7
Figure 6. LVDS Differential Output .................................................................................................. 7
Figure 7. PECL Differential Output .................................................................................................. 8
Figure 8. PECL Single-Ended Outputs (Positive and Negative Output Referenced to Ground) 9
ORDERING INFORMATION ............................................................................................. 10
R
EVISIONS
................................................................................................................................................. 11
XRT8020
REV. 1.0.2
650 MHZ CLOCK & CRYSTAL MULTIPLIER WITH LVDS OUTPUTS
3
PIN DESCRIPTION
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
P
IN
N
AME
T
YPE
D
ESCRIPTION
1
AVDD
3.3V 10% Analog Supply for Crystal Oscillator
2
AGND
Analog Ground for Crystal Oscillator
3
XTAL1
I
Crystal pin 1 or external clock input
4
XTAL2
O
Crystal pin 2 (output drive for crystal)
5
AGND
Analog Ground
6
REXT
I
External Bias Resistor (10K
to ground)
7
OE
I
Output Enable, Active low (
Internal 50K
pull-down to ground)
8
PD
I
Power Down, Active High
(Internal 50K
pull-down to ground)
9
FS1
I
Frequency select "1"
(Internal 50K
pull-down to ground)
10
FS0
I
Frequency select "0"
(Internal 50K
pull-up to VDD)
11
AGND
Analog Ground
12
OGND
Output Ground for LVDS outputs
13
OUTN
O
LVDS negative output for 50
line
14
OUTP
O
LVDS positive output for 50
line
15
OVDD
3.3V 10% Digital Supply for LVDS Output buffer
16
AVDD
3.3V 10% Analog Supply
Supply voltage
-0.5 to 6.0 V
V
IN
-0.5 to 6.0 V
Storage Temperature
-65C to + 150C
Operating Temperature
-40C to + 85C
ESD
>2,000 volts
REXT (1%)
10k
P
ARAMETER
S
YMBOL
M
IN
T
YP
M
AX
U
NIT
C
ONDITIONS
Supply Voltage
V
DD
3.0
3.3
3.6
V
Supply current
I
DD
25
30
mA
VDD = 3.3V
Power Save Current
I
DD
6
mA
VDD = 3.3V, PD = 1, OEB = 0
Input Digital High
V
INH
2.0
V
Pins 7, 8, 9, 10
Input Digital Low
V
INL
0.8
V
Pins 7, 8, 9, 10
Crystal Frequency
15
27
MHz
See Section 2.0 for Crystal Selection
XRT8020
650 MHZ CLOCK & CRYSTAL MULTIPLIER WITH LVDS OUTPUTS
REV. 1.0.2
4
Crystal Frequency
27
40
MHz
See Section 2.0 for Crystal Selection
Clock Input Frequency
72
85
MHz
AC Coupled (FS0=1, FS1=1)
Power on Calibration time
5
ms
After VDD reaches 2.8V
N
OTE
: Calibration time = 16,000 clock cycles
Max Frequency Out
F
OUT
575
675
MHz
624 MHz nominal F
OUT
(See Table 1)
Max Frequency Out
F
OUT
285
340
MHz
312 MHz nominal F
OUT
(See Table 1)
Rise time
T
R
350
ps
CL = 5pF, RL = 100
, (20% - 80%)
Fall Time
T
F
350
ps
CL = 5pF, RL = 100
, (20% - 80%)
Duty cycle
45
55
%
LVDS output
Differential Output Skew
10
ps
See Figure 3
Output Loading
100
Output Voltage Swing
V
OUT
250
450
mV
Magnitude of (OUTP-OUTN)
Common Mode Voltage
V
CM
1.0
1.2
1.4
V
Output Short Circuit Current
-5.7
-10
mA
Current limit to ground, V
DD
or Vp to Vn
Cycle-to-Cycle Jitter
3
ps
rms, at 624 MHz
Cycle-to-Cycle Jitter
3
ps
rms, at 312 MHz
Accumulated Jitter
12
ps
rms, at 624 MHz
Accumulated Jitter
12
ps
rms, 312 MHz
Input Referenced Jitter
9
ps
rms at 622 MHz, See Figure 4
Input Referenced Jitter
9
ps
rms at 312 MHz, See Figure 4
P
ARAMETER
S
YMBOL
M
IN
T
YP
M
AX
U
NIT
C
ONDITIONS
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