Exar

Corporation 48720 Kato Road, Fremont CA, 94538

(510) 668-7000

FAX (510) 668-7017

www.exar.com

áç

PRELIMINARY

XRT83L30

SINGLE-CHANNEL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR

MAY 2003

REV. P1.3.0

GENERAL DESCRIPTION

The XRT83L30 is a fully integrated single-channel
long-haul and short-haul line interface unit for
T1(1.544Mbps) 100

, E1(2.048Mbps) 75

or 120

and J1 110

applications.

In long-haul applications the XRT83L30 accepts sig-
nals that have passed through cables from 0 feet to
over 6000 feet in length and have been attenuated by
0 to 45dB at 772kHz in T1 mode or 0 to 43dB at
1024kHz in E1 mode. In T1 applications, the
XRT83L30 can generate five transmit pulse shapes to
meet the short-haul Digital Cross-Connect (DSX-1)
template requirements as well as for Channel Service
Units (CSU) Line Build Out (LBO) filters of 0dB,
-7.5dB, -15dB and -22.5dB as required by FCC rules.
It also provides programmable transmit pulse genera-
tor that can be used for arbitrary output pulse shaping
allowing performance improvement over a wide vari-
ety of conditions.

The XRT83L30 provides both Serial Host micropro-
cessor interface and Hardware Mode for program-
ming and control. Both B8ZS and HDB3 encoding
and decoding functions are included and can be dis-
abled as required. On-chip crystal-less jitter attenua-
tor with a 32 or 64 bit FIFO can be placed either in the
receive or the transmit path with loop bandwidths of

less than 3Hz. The XRT83L30 provides a variety of
loop-back and diagnostic features as well as transmit
driver short circuit detection and receive loss of signal
monitoring. It supports internal impedance matching
for 75

100

110

and 120

for both transmitter

and receiver. For the receiver this is accomplished by
internal resistors or through the combination of one
single fixed value external resistor and programmable
internal resistors. In the absence of the power supply,
the transmit output and receive input are tri-stated al-
lowing for redundancy applications. The chip includes
an integrated programmable clock multiplier that can
synthesize T1 or E1 master clocks from a variety of
external clock sources.

APPLICATIONS

· T1 Digital Cross-Connects (DSX-1)

· ISDN Primary Rate Interface

· CSU/DSU E1/T1/J1 Interface

· T1/E1/J1 LAN/WAN Routers

· Public switching Systems and PBX Interfaces

· T1/E1/J1 Multiplexer and Channel Banks

FEATURES

(See Page 2)

IGURE

1. B

LOCK

IAGRAM

THE

XRT83L30 T1/E1/J1 LIU (H

OST

ODE

)

HW/HOST

INT

ICT

TXTEST[0:2]

INSBPV

TPOS / TDATA

TNEG / CODES

TCLK

QRPD

RCLK

RNEG / LCV

RPOS / RDATA

NLCD

RLOS

RTIP
RRING

MASTER CLOCK SYNTHESIZER

QRSS

PATTERN

GENERATOR

DMO

TTIP

TRING

TXON

HDB3/

B8ZS

ENCODER

TX/RX JITTER
ATTENUATOR

TIMING

CONTROL

TX FILTER

& PULSE

SHAPER

LINE
DRIVER

DRIVE

MONITOR

LOCAL

ANALOG

LOOPBACK

REMOTE

LOOPBACK

DIGITAL

LOOPBACK

HDB3/

B8ZS

DECODER

TX/RX JITTER
ATTENUATOR

TIMING &

DATA

RECOVERY

PEAK

DETECTOR

& SLICER

QRSS

DETECTOR

NETWORK

LOOP

DETECTOR

EQUALIZER

CONTROL

AIS

DETECTOR

LOS

DETECTOR

LBO[3:0]

LOOPBACK

ENABLE

SELECT

NLCD ENABLE

QRSS ENABLE

SDO
SCLK
SDI
RESET

Serial Interface

TEST

TAOS

ENABLE

MCLKE1
MCLKT1

MCLKOUT

AISD

XRT83L30

áç

SINGLE-CHANNEL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR

REV. P1.3.0

PRELIMINARY

FEATURES

· Fully integrated single-channel long-haul and short-

haul transceiver for E1,T1 or J1 applications.

· Adaptive Receive Equalizer for cable attenuation of

up to 45dB for T1 and 43dB for E1.

· Programmable Transmit Pulse Shaper for E1,T1 or

J1 short-haul interfaces.

· Five fixed transmit pulse settings for T1 short-haul

applications plus a fully programmable waveform
generator for transmit output pulse shaping.

· Programmable Transmit Line Build-Outs (LBO) for

T1 long-haul application from 0dB to -22.5dB in
three 7.5dB steps.

· Tri-State transmit output and receive input capabil-

ity for redundancy applications

· Selectable receiver sensitivity from 0 to 36dB or 0

to 45dB cable loss for T1 @772kHz and 0 to 43dB
for E1 @1024kHz.

· High receiver interference immunity

· Receive monitor mode handles 0 to 29dB resistive

attenuation along with 0 to 6dB of cable attenuation
for both T1 and E1 modes.

· Supports 75

and 120

(E1), 100

(T1) and 110

(J1) applications.

· Internal and external impedance matching for

,100

110

and 120

· Transmit return loss meets or exceeds ETSI 300

166 standard

· On-chip digital clock recovery circuit for high input

jitter tolerance

· Crystal-less digital jitter attenuator with 32-bit or 64-

bit FIFO Selectable either in transmit or receive
path

· On-chip frequency multiplier generates T1 or E1

Master clocks from variety of external clock sources

· On-chip transmit short-circuit protection and limit-

ing, and driver fail monitor output (DMO)

· Receive loss of signal (RLOS) output

· On-chip HDB3/B8ZS/AMI encoder/decoder

· QRSS pattern generation and detection for testing

and monitoring

· Error and Bipolar Violation Insertion and Detection

· Receiver Line Attenuation Indication Output in 1dB

steps

· Network Loop-Code Detection for automatic Loop-

Back Activation/Deactivation

· Transmit All Ones (TAOS) and In-Band Network

Loop Up and Down code generators

· Supports Analog, Remote, Digital and Dual Loop-

Back Modes

· Meets or exceeds T1 and E1 short-haul and long-

haul network access specifications in ITU G.703,

IGURE

2. B

LOCK

IAGRAM

THE

XRT83L30 T1/E1/J1 LIU (H

ARDWARE

ODE

)

HW/HOST

GAUGE
JASEL1
JASEL0

RXTSEL

TXTSEL

TERSEL1
TERSEL0

RXRES1
RXRES0

ICT

MCLKE1
MCLKT1

CLKSEL[2:0]

TXTEST[0:2]

INSBPV

TPOS / TDATA

TNEG / CODES

TCLK

QRPD

RCLK

RNEG / LCV

RPOS / RDATA

NLCD

RLOS

RTIP
RRING

MASTER CLOCK SYNTHESIZER

QRSS

PATTERN

GENERATOR

DMO

TTIP

TRING

TXON

HDB3/

B8ZS

ENCODER

TX/RX JITTER
ATTENUATOR

TIMING

CONTROL

TX FILTER

& PULSE

SHAPER

LINE
DRIVER

LOCAL

ANALOG

LOOPBACK

REMOTE

LOOPBACK

DIGITAL

LOOPBACK

HDB3/

B8ZS

DECODER

TX/RX JITTER
ATTENUATOR

TIMING &

DATA

RECOVERY

PEAK

DETECTOR

& SLICER

QRSS

DETECTOR

NETWORK

LOOP

DETECTOR

EQUALIZER

CONTROL

AIS

DETECTOR

LOS

DETECTOR

LBO[3:0]

LOOPBACK

ENABLE

SELECT

NLCD ENABLE

QRSS ENABLE

HARWARE CONTROL

TEST

JABW
TRATIO
SR/DR
EQC[4:0]
TCLKE
RCLKE
RXMUTE
ATAOS

DRIVE

MONITOR

DFM

MCLKOUT

LOOP1
LOOP0

AISD

RESET

TAOS

ENABLE

áç

XRT83L30

SINGLE-CHANNEL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR

PRELIMINARY

REV. P1.3.0

G.775, G.736 and G.823; TR-TSY-000499; ANSI
T1.403 and T1.408; ETSI 300-166 and AT&T Pub
62411

· Supports both Hardware and serial Microprocessor

interface for programming

· Programmable Interrupt

· Low power dissipation

· Logic inputs accept either 3.3V or 5V levels

· Single +3.3V Supply Operation

· 64 pin TQFP package

· -40°C to +85°C Temperature Range

ORDERING INFORMATION

ART

UMBER

ACKAGE

PERATING

EMPERATURE

ANGE

XRT83L30IV

64 Lead TQFP (14 x 20 x 1.4mm)

-40

C to +85

IGURE

3. P

THE

XRT83L30

RDA

VDD

RTI

I
N

TTIP

I
N

DPLL

GND

AGND
AVDD
LOOP0

LOOP1
SR / DR
ATAOS
TRATIO

EQC0 / INT
EQC1 / CS
EQC2 / SCLK
EQC3 / SDO

EQC4 / SDI
HW /HOST
CLKSEL0
CLKSEL1

CLKSEL2

TSEL

TSE

QRP

I
N

SBP

CDE

GAUGE

RXMUTE

RXRES1
RXRES0

RCLKE

TXTEST2
TXTEST1
TXTEST0

TCLKE

TXON

ICT

TCLK

TPOS / TDATA

TNEG / CODES

RLOS

RCLK

32
31
30

29
28
27

26
25
24
23

22
21
20
19

18
17

49
50
51

52
53
54

55
56
57
58

59
60
61
62

63
64

XRT83L30

áç

SINGLE-CHANNEL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR

REV. P1.3.0

PRELIMINARY

TABLE OF CONTENTS

GENERAL DESCRIPTION ................................................................................................. 1

PPLICATIONS

.............................................................................................................................................. 1

EATURES

.................................................................................................................................................... 1

Figure 1. Block Diagram of the XRT83L30 T1/E1/J1 LIU (Host Mode) ................................................. 1
Figure 2. Block Diagram of the XRT83L30 T1/E1/J1 LIU (Hardware Mode) ......................................... 2

EATURES

.................................................................................................................................................... 2

ORDERING INFORMATION ............................................................................................................... 3

Figure 3. Pin Out of the XRT83L30 .......................................................................................................... 3

TABLE OF CONTENTS ....................................................................................................... I
PIN DESCRIPTIONS BY FUNCTION ................................................................................. 4

ERIAL

NTERFACE

....................................................................................................................................... 4

ECEIVER

.................................................................................................................................................... 4

RANSMITTER

............................................................................................................................................... 6

ITTER

TTENUATOR

.................................................................................................................................... 8

LOCK

YNTHESIZER

.................................................................................................................................... 9

EDUNDANCY

SUPPORT

.............................................................................................................................. 11

ERMINATIONS

........................................................................................................................................... 11

ONTROL

FUNCTION

................................................................................................................................... 13

LARM

UNCTION

THER

........................................................................................................................... 14

OWER

AND

GROUND

................................................................................................................................. 16

FUNCTIONAL DESCRIPTION ......................................................................................... 17

ASTER

LOCK

ENERATOR

...................................................................................................................... 17

Figure 4. Two Input Clock Source ......................................................................................................... 17
Figure 5. One Input Clock Source ......................................................................................................... 17

RECEIVER ........................................................................................................................ 18

ECEIVER

NPUT

......................................................................................................................................... 18

ABLE

1: M

ASTER

LOCK

ENERATOR

...................................................................................................... 18

ECEIVE

ONITOR

ODE

........................................................................................................................... 19

ECEIVER

OSS

IGNAL

(RLOS) ........................................................................................................... 19

Figure 6. Simplified Diagram of -15dB T1/E1 Short Haul Mode and RLOS Condition ..................... 19
Figure 7. Simplified Diagram of -29dB T1/E1 Gain Mode and RLOS Condition ............................... 20
Figure 8. Simplified Diagram of -36dB T1/E1 Long Haul Mode and RLOS Condition ...................... 20

ECEIVE

HDB3/B8ZS D

ECODER

................................................................................................................ 21

ECOVERED

LOCK

(RCLK) S

AMPLING

DGE

............................................................................................ 21

Figure 9. Simplified Diagram of Extended RLOS mode (E1 Only) ..................................................... 21
Figure 10. Receive Clock and Output Data Timing ............................................................................. 21

ITTER

TTENUATOR

.................................................................................................................................. 22

APPED

LOCK

(JA M

UST

NABLED

THE

RANSMIT

ATH

) ................................................................. 22

ABLE

2: M

AXIMUM

IDTH

FOR

ULTIPLEXER

APPER

PPLICATIONS

............................................... 22

RBITRARY

ULSE

ENERATOR

.................................................................................................................. 23

TRANSMITTER ................................................................................................................. 23

IGITAL

ATA

ORMAT

............................................................................................................................... 23

RANSMIT

LOCK

(TCLK) S

AMPLING

DGE

................................................................................................ 23

Figure 11. Arbitrary Pulse Segment Assignment ................................................................................ 23

RANSMIT

HDB3/B8ZS E

NCODER

.............................................................................................................. 24

Figure 12. Transmit Clock and Input Data Timing ............................................................................... 24
T

ABLE

3: E

XAMPLES

HDB3 E

NCODING

................................................................................................. 24

ABLE

4: E

XAMPLES

B8ZS E

NCODING

.................................................................................................. 24

RIVER

AILURE

ONITOR

(DMO) .............................................................................................................. 25

RANSMIT

ULSE

HAPER

& L

INE

UILD

(LBO)

CIRCUIT

...................................................................... 25

ABLE

5: R

ECEIVE

QUALIZER

ONTROL

AND

RANSMIT

INE

UILD

-O

ETTINGS

.................................. 25

áç

XRT83L30

SINGLE-CHANNEL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR

PRELIMINARY

REV. P1.3.0

TRANSMIT AND RECEIVE TERMINATIONS .................................................................. 27

RECEIVER ............................................................................................................................................... 27

Internal Receive Termination Mode ................................................................................................................. 27

ABLE

6: R

ECEIVE

ERMINATION

ONTROL

................................................................................................ 27

Figure 13. Simplified Diagram for the Internal Receive and Transmit Termination Mode .............. 27
T

ABLE

7: R

ECEIVE

ERMINATIONS

............................................................................................................. 28

Figure 14. Simplified Diagram for T1 in the External Termination Mode (RXTSEL= 0) ................... 28

TRANSMITTER ........................................................................................................................................ 29

Transmit Termination Mode ............................................................................................................................. 29
External Transmit Termination Mode ............................................................................................................... 29

Figure 15. Simplified Diagram for E1 in External Termination Mode (RXTSEL= 0) ......................... 29
T

ABLE

8: T

RANSMIT

ERMINATION

ONTROL

............................................................................................. 29

ABLE

9: T

ERMINATION

ELECT

ONTROL

................................................................................................. 29

REDUNDANCY APPLICATIONS ............................................................................................................. 30

ABLE

10: T

RANSMIT

ERMINATION

ONTROL

........................................................................................... 30

ABLE

11: T

RANSMIT

ERMINATIONS

......................................................................................................... 30

TYPICAL REDUNDANCY SCHEMES ..................................................................................................... 31

Figure 16. Simplified Block Diagram of the Transmit Section for 1:1 & 1+1 Redundancy ............. 32
Figure 17. Simplified Block Diagram - Receive Section for 1:1 and 1+1 Redundancy .................... 32
Figure 18. Simplified Block Diagram - Transmit Section for N+1 Redundancy ............................... 33
Figure 19. Simplified Block Diagram - Receive Section for N+1 Redundancy ................................. 34

ATTERN

RANSMIT

AND

ETECT

UNCTION

............................................................................................... 35

RANSMIT

NES

(TAOS) .................................................................................................................... 35

ETWORK

OOP

ODE

ETECTION

AND

RANSMISSION

.............................................................................. 35

ABLE

12: P

ATTERN

TRANSMISSION

CONTROL

............................................................................................ 35

RANSMIT

AND

ETECT

UASI

-R

ANDOM

IGNAL

OURCE

(TDQRSS) ......................................................... 36

ABLE

13: L

OOP

-C

ODE

ETECTION

ONTROL

........................................................................................... 36

OOP

-B

ACK

ODES

................................................................................................................................... 38

OCAL

NALOG

OOP

-B

ACK

(ALOOP) ....................................................................................................... 38

ABLE

14: L

OOP

BACK

CONTROL

ARDWARE

MODE

.............................................................................. 38

ABLE

15: L

OOP

BACK

CONTROL

OST

MODE

........................................................................................ 38

Figure 20. Local Analog Loop-back signal flow .................................................................................. 38

EMOTE

OOP

-B

ACK

(RLOOP) ................................................................................................................. 39

Figure 21. Remote Loop-back mode with jitter attenuator selected in receive path ....................... 39
Figure 22. Remote Loop-back mode with jitter attenuator selected in Transmit path .................... 39

IGITAL

OOP

-B

ACK

(DLOOP) .................................................................................................................. 40

UAL

OOP

-B

ACK

...................................................................................................................................... 40

Figure 23. Digital Loop-back mode with jitter attenuator selected in Transmit path ...................... 40
Figure 24. Signal flow in Dual loop-back mode ................................................................................... 40

HOST MODE SERIAL INTERFACE OPERATION ........................................................... 41

SING

THE

ICROPROCESSOR

ERIAL

NTERFACE

...................................................................................... 41

Figure 25. Microprocessor Serial Interface Data Structure ................................................................ 42
T

ABLE

16: M

ICROPROCESSOR

EGISTER

DDRESS

................................................................................... 43

ABLE

17: M

ICROPROCESSOR

EGISTER

..................................................................................... 43

ABLE

18: M

ICROPROCESSOR

EGISTER

BIT

DESCRIPTION

.................................................................... 45

ABLE

19: M

ICROPROCESSOR

EGISTER

BIT

DESCRIPTION

.................................................................... 46

ABLE

20: M

ICROPROCESSOR

EGISTER

BIT

DESCRIPTION

.................................................................... 48

ABLE

21: M

ICROPROCESSOR

EGISTER

BIT

DESCRIPTION

.................................................................... 50

ABLE

22: M

ICROPROCESSOR

EGISTER

BIT

DESCRIPTION

.................................................................... 52

ABLE

23: M

ICROPROCESSOR

EGISTER

BIT

DESCRIPTION

.................................................................... 53

ABLE

24: M

ICROPROCESSOR

EGISTER

BIT

DESCRIPTION

.................................................................... 55

ABLE

25: M

ICROPROCESSOR

EGISTER

BIT

DESCRIPTION

.................................................................... 56

ABLE

26: M

ICROPROCESSOR

EGISTER

BIT

DESCRIPTION

.................................................................... 56

ABLE

27: M

ICROPROCESSOR

EGISTER

BIT

DESCRIPTION

.................................................................... 57

XRT83L30

áç

SINGLE-CHANNEL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR

REV. P1.3.0

PRELIMINARY

III

ABLE

28: M

ICROPROCESSOR

EGISTER

#10

BIT

DESCRIPTION

.................................................................. 57

ABLE

29: M

ICROPROCESSOR

EGISTER

#11

BIT

DESCRIPTION

.................................................................. 58

ABLE

30: M

ICROPROCESSOR

EGISTER

#12

BIT

DESCRIPTION

.................................................................. 58

ABLE

31: M

ICROPROCESSOR

EGISTER

#13

BIT

DESCRIPTION

.................................................................. 59

ABLE

32: M

ICROPROCESSOR

EGISTER

#14

BIT

DESCRIPTION

.................................................................. 59

ABLE

33: M

ICROPROCESSOR

EGISTER

#15

BIT

DESCRIPTION

.................................................................. 60

ABLE

34: M

ICROPROCESSOR

EGISTER

#16

BIT

DESCRIPTION

.................................................................. 61

ABLE

35: M

ICROPROCESSOR

EGISTER

#17

BIT

DESCRIPTION

.................................................................. 62

ABLE

36: M

ICROPROCESSOR

EGISTER

#18

BIT

DESCRIPTION

.................................................................. 63

LECTRICAL

HARACTERISTICS

................................................................................................................... 65

ABLE

37: A

BSOLUTE

AXIMUM

ATINGS

.................................................................................................. 65

ABLE

38: DC D

IGITAL

NPUT

AND

UTPUT

LECTRICAL

HARACTERISTICS

............................................... 65

ABLE

39: XRT83L30 P

OWER

ONSUMPTION

........................................................................................... 65

ABLE

40: E1 R

ECEIVER

LECTRICAL

HARACTERISTICS

........................................................................... 66

ABLE

41: T1 R

ECEIVER

LECTRICAL

HARACTERISTICS

........................................................................... 67

ABLE

42: E1 T

RANSMIT

ETURN

OSS

EQUIREMENT

.............................................................................. 67

ABLE

43: E1 T

RANSMITTER

LECTRICAL

HARACTERISTICS

..................................................................... 68

ABLE

44: T1 T

RANSMITTER

LECTRICAL

HARACTERISTICS

..................................................................... 68

Figure 26. ITU G.703 Pulse Template .................................................................................................... 69
T

ABLE

45: T

RANSMIT

ULSE

ASK

PECIFICATION

.................................................................................... 69

Figure 27. DSX-1 Pulse Template (normalized amplitude) ................................................................. 70
T

ABLE

46: DSX1 I

NTERFACE

SOLATED

ULSE

ASK

AND

ORNER

OINTS

............................................... 70

ABLE

47: AC E

LECTRICAL

HARACTERISTICS

.......................................................................................... 71

Figure 28. Transmit Clock and Input Data Timing ............................................................................... 71
Figure 29. Receive Clock and Output Data Timing ............................................................................. 72

PACKAGE DIMENSIONS ................................................................................................. 73

64 LEAD THIN QUAD FLAT PACK ............................................................................................. 73
(10

1.4

TQFP) ............................................................................................................. 73

REV

. 3.00 ...................................................................................................................................... 73

ORDERING INFORMATION ............................................................................................. 74

EVISION

ISTORY

..................................................................................................................................... 74

NOTES ............................................................................................................................................... 75

áç

XRT83L30

SINGLE-CHANNEL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR

PRELIMINARY

REV. P1.3.0

PIN DESCRIPTIONS BY FUNCTION

SERIAL INTERFACE

RECEIVER

IGNAL

AME

YPE

ESCRIPTION

HW/HOST

Mode Control Input
This pin is used for selecting Hardware or Host mode to control the device.
Leave this pin unconnected or tie "High" to select Hardware mode. For Host
mode, this pin must be tied "Low".

OTE

: Internally pulled "High" with a 50k

resistor.

SDI

EQC4

Serial Data Input
In Host mode, this pin is the data input for the Serial Interface.

Equalizer Control Input 4
Hardware mode, See "Control function" on page 13.

SDO

EQC3

Serial Data Output
In Host mode, this pin is the output "Read" data for the serial interface.

Equalizer Control Input 3
Hardware mode, See "Control function" on page 13.

SCLK

EQC2

Serial Interface Clock Input
In Host mode, this clock signal is used to control data "Read" or "Write" oper-
ation for the Serial Interface. Maximum clock frequency is 20MHz.

Equalizer Control Input 2
Hardware mode, See "Control function" on page 13.

EQC1

Chip Select Input
In Host mode, tie this pin "Low" to enable communication with the device via
the Serial Interface.

Equalizer Control Input 1
Hardware mode, See "Control function" on page 13.

INT

EQC0

Interrupt Output (active "Low")
In Host mode, this pin goes "Low" to indicate an alarm condition has
occurred within the device. Interrupt generation can be globally disabled by
setting the GIE bit to "0" in the command control register.

Equalizer Control Input 0
Hardware mode, See "Control function" on page 13.

OTE

: This pin is an open drain output and requires an external 10k

pull-up

resistor.

IGNAL

AME

YPE

ESCRIPTION

RLOS

Receiver Loss of Signal
This signal is asserted `High' for at least one RCLK cycle to indicate loss of
signal at the receive input.

RCLK

Receiver Clock Output

XRT83L30

áç

SINGLE-CHANNEL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR

REV. P1.3.0

PRELIMINARY

RNEG

LCV

Receiver Negative Data Output
In dual-rail mode, this signal is the receiver negative-rail output data.

Line Code Violation Output
In single-rail mode, this signal goes `High' for one RCLK cycle to indicate a
code violation is detected in the received data. If AMI coding is selected,
every bipolar violation received will cause this pin to go "High".

RPOS

RDATA

Receiver Positive Data Output
In dual-rail mode, this signal is the receive positive-rail output data sent to the
Framer.

Receiver NRZ Data Output
In single-rail mode, this signal is the receive NRZ format output data sent to
the Framer.

RTIP

Receiver Differential Tip Positive Input
Positive differential receive input from the line.

RRING

Receiver Differential Ring Negative Input
Negative differential receive input from the line.

RXMUTE

Receive Muting
In Hardware mode, connect this pin `High' to mute RPOS and RNEG outputs
to a "Low" state upon receipt of LOS condition to prevent data chattering.
Connect this pin to `Low' to disable muting function.

OTE

: Internally pulled "Low" with 50k

resistor.

RCLKE

Receive Clock Edge
In Hardware mode, with this pin set to `High' the output receive data is
updated on the falling edge of RCLK. With this pin tied `Low', output data is
updated on the rising edge of RCLK.

OTE

: Internally pulled "Low" with a 50k

resistor.

IGNAL

AME

YPE

ESCRIPTION

áç

XRT83L30

SINGLE-CHANNEL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR

PRELIMINARY

REV. P1.3.0

TRANSMITTER

IGNAL

AME

YPE

ESCRIPTION

TTIP

Transmitter Tip Output
Positive differential transmit output to the line.

TRING

Transmitter Ring Output
Negative differential transmit output to the line.

TPOS

TDATA

Transmitter Positive Data Input
In dual-rail mode, this signal is the positive-rail input data for the transmitter.

Transmitter Data Input
In single-rail mode, this pin is used as the NRZ input data for the transmitter.

OTE

: Internally pulled "Low" with a 50k

resistor.

TNEG

CODES

Transmitter Negative NRZ Data Input
In dual-rail mode, this signal is the negative-rail input data for the transmitter.
In single-rail mode, this pin can be left unconnected.

Coding Select
In Hardware mode and with single-rail mode selected, connecting this pin
"Low" enables HDB3 in E1 or B8ZS in T1 encoding and decoding. Connect-
ing this pin "High" selects AMI data format.

OTE

: Internally pulled "Low" with a 50k

resistor.

TCLK

Transmitter Clock Input
E1 rate at 2.048MHz ± 50ppm
T1 rate at 1.544MHz ± 32ppm

During normal operation, both in Host mode and Hardware mode, TCLK is
used for sampling input data at TPOS/TDATA and TNEG/CODES while
MCLK is used as the timing reference for the transmit pulse shaping circuit.

TCLKE

Transmit Clock Edge
In Hardware mode, with this pin set to a "High", transmit input data is sam-
pled at the rising edge of TCLK. With this pin tied "Low", input data are sam-
pled at the falling edge of TCLK.

OTE

: Internally pulled "Low" with a 50k

resistor.

TXON

Transmitter Turn On
In Hardware mode, setting this pin "High" turns on the Transmit Section. In
this mode, when TXON = "0", TTIP and TRING driver outputs will be tri-
stated.

OTES

1. Internally pulled "Low" with a 50k

resistor.

2. In Hardware mode only, the receiver is turned on at power-up.

XRT83L30

áç

SINGLE-CHANNEL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR

REV. P1.3.0

PRELIMINARY

TXTEST2
TXTEST1
TXTEST0

54
55
56

Transmit Test Pattern pin 2
Transmit Test Pattern pin 1
Transmit Test Pattern pin 0
TXTEST[2:0] pins are used to generate and transmit test patterns according
to the following table:

TAOS (Transmit All Ones): Activating this condition enables the transmis-
sion of an All Ones Pattern.TCLK must not be tied "Low".

TLUC (Transmit Network Loop-Up Code): Activating this condition
enables the Network Loop-Up Code of "00001" to be transmitted to the line.
When Network Loop-Up code is being transmitted, the XRT83L30 will ignore
the Automatic Loop-Code detection and Remote Loop-back activation
(NLCDE1="1", NLCDE0="1", if activated) in order to avoid activating Remote
Digital Loop-back automatically when the remote terminal responds to the
Loop-back request.

TLDC (Transmit Network Loop-Down Code): Activating this condition
enables the network Loop-Down Code of "001" to be transmitted to the line.

TDQRSS (Transmit/Detect Quasi-Random Signal): Setting TXTEST2="1",
regardless of the state of TXTEST1 and TXTEST0, enables Quasi-Random
Signal Source generation and detection. In a T1 system QRSS pattern is a

-1 pseudo-random bit sequence (PRBS) with no more than 14 consecu-

tive zeros. In a E1 system, QRSS is a 2

-1 PRBS pattern.

When TXTEST2 is "1" and TDQRSS is active, setting TXTEST0 to "1" inverts
the polarity of transmitted QRSS pattern. Resetting to "0" sends the QRSS
pattern with no inversion.

When TXTEST2 is "1" and TDQRSS is active, transitions of TXTEST1 from
"0" to "1" results in a bit error to be inserted in the transmitted QRSS pattern.
The state of this pin is sampled on the rising edge of TCLK. To ensure the
insertion of a bit error, this pin should be reset to a "0" before setting to a "1".

When TXTEST2 is "1", TXTEST1 and TXTEST0 affect the transmitted QRSS
bit pattern independently.

IGNAL

AME

YPE

ESCRIPTION

Transmit Data

TAOS

TLUC

TLDC

Test Pattern

TXTEST1

TXTEST0

TXTEST2

TDQRSS

TDQRSS & INVQRSS

TDQRSS & INSBER

TDQRSS & INVQRSS & INSBER

XRT83L30

áç

SINGLE-CHANNEL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR

REV. P1.3.0

PRELIMINARY

CLOCK SYNTHESIZER

IGNAL

AME

YPE

ESCRIPTION

MCLKE1

E1 Master Clock Input
This input signal is an independent 2.048MHz clock for E1 system with
required accuracy of better than ±50ppm and a duty cycle of 40% to 60%.
MCLKE1 is used in the E1 mode. Its function is to provide internal timing for
the PLL clock recovery circuit, transmit pulse shaping, jitter attenuator block,
reference clock during transmit all ones data and timing reference for the
microprocessor in Host mode operation.

MCLKE1 is also input to a programmable frequency synthesizer that under
the control of the CLKSEL[2:0] inputs can be used to generate a master
clock from an accurate external source. In systems that have only one mas-
ter clock source available (E1 or T1), that clock should be connected to both
MCLKE1 and MCLKT1 inputs for proper operation.

OTES

1. See pin descriptions for pins CLKSEL[2:0].

2. Internally pulled "Low" with a 50k

resistor.

MCLKT1

T1 Master Clock Input
This signal is an independent 1.544MHz clock for T1 systems with required
accuracy of better than ±50ppm and duty cycle of 40% to 60%. MCLKT1
input is used in the T1 mode.

OTES

1. See MCLKE1 description for further explanation for the usage of this

pin.

2. Internally pulled "Low" with a 50k

resistor.

MCLKOUT

Synthesized Master Clock Output
This signal is the output of the Master Clock Synthesizer PLL which is at T1
or E1 rate based on the mode of operation.

XRT83L30

áç

SINGLE-CHANNEL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR

REV. P1.3.0

PRELIMINARY

REDUNDANCY SUPPORT

TERMINATIONS

IGNAL

AME

YPE

ESCRIPTION

DMO

Driver Failure Monitor
This pin transitions "High" if a short circuit condition is detected in the trans-
mit driver, or no transmit output pulse is detected for more than 128 TCLK
cycles.

IGNAL

AME

YPE

ESCRIPTION

GAUGE

Twisted Pair Cable Wire Gauge Select
In Hardware mode, connect this pin "High" to select 26 Gauge wire. Connect
this pin "Low" to select 22 and 24 gauge wire.

OTE

: Internally pulled "Low" with a 50k

resistor.

TRATIO

Transmitter Transformer Ratio Select
In external termination mode, setting this pin "High" selects a transformer
ratio of 1:2 for the transmitter. A "Low" on this pin sets the transmitter trans-
former ratio to 1:2.45. In the internal termination mode the transmitter trans-
former ratio is permanently set to 1:2 and the state of this pin is ignored.

OTE

: Internally pulled "Low" with a 50k

resistor.

RXTSEL

Receiver Termination Select
In Hardware mode when this pin is "Low" the receive line termination is
determined only by the external resistor. When "High", the receive termina-
tion is realized by internal resistors or the combination of internal and exter-
nal resistors according to RXRES[1:0]. These conditions are described in the
following table:

OTE

: This pin is internally pulled "Low" with a 50k

resistor.

TXTSEL

Transmit Termination Select
In Hardware mode when this pin is "Low" the transmit line termination is
determined only by external resistor. When "High", the transmit termination is
realized only by an internal resistor. These conditions are summarized in the
following table:

OTE

: This pin is internally pulled "Low" with a 50k

resistor.

RXTSEL

RX Termination

External

Internal

TXTSEL

TX Termination

External

Internal

áç

XRT83L30

SINGLE-CHANNEL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR

PRELIMINARY

REV. P1.3.0

TERSEL1
TERSEL0

43
42

Termination Impedance Select pin 1
Termination Impedance Select pin 0
In the Hardware mode and in the Internal Termination mode (TXTSEL="1"
and/or RXTSEL="1") TERSEL[1:0] control the transmit and receive termina-
tion impedance according to the following table:

In the Internal Termination mode, the receive termination is realized com-
pletely by internal resistors or the combination of internal and one fixed exter-
nal resistor (see description for RXRES[1:0] pins). In the internal termination
mode the transformer ratio of 1:2 and 2:1 is required for the transmitter and
receiver respectively with the transmitter output AC coupled to the trans-
former.

OTE

: This pin is internally pulled "Low" with a 50k

resistor.

RXRES1
RXRES0

51
52

Receive External Resistor Control pin 1
Receive External Resistor Control pin 0
In Hardware mode, RXRES[1:0] pins selects the required value of the exter-
nal fixed resistor for the receiver according to the following table. This mode
is only available in the internal impedance mode by pulling RXTSEL "High".

OTE

: Internally pulled "Low" with 50k

resistor.

IGNAL

AME

YPE

ESCRIPTION

TERSEL1

Termination

TERSEL0

100

120

110

RXRES1

RX Fixed Resistor

No External Fixed Resistor

240

RXRES0

210

150

XRT83L30

áç

SINGLE-CHANNEL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR

REV. P1.3.0

PRELIMINARY

CONTROL FUNCTION

RESET

Hardware Reset (Active "Low")
When this pin is tied "Low" for more than 10µs, the device is put in the reset
state.
Pulling RESET "Low" while the ICT pin is also "Low" will put the chip in fac-
tory test mode. This condition should never happen during normal operation.

OTE

: Internally pulled "High" with a 50k

resistor.

SR/DR

Single-Rail/Dual-Rail Data Format
In Hardware mode, connect this pin "Low" to select transmit and receive
data format in dual-rail mode. In this mode, HDB3 or B8ZS encoder and
decoder are not available.
Connect this pin "High" to select single-rail data format.

OTE

: Internally pulled "Low" with a 50k

resistor.

LOOP1
LOOP0

29
30

Loop-back Control pin 1
Loop-back Control pin 0
In Hardware mode, LOOP[1:0] pins are used to control the Loop-back func-
tions according to the following table:

OTE

: Internally pulled "Low" with a 50k

resistor.

EQC4

SDI

Equalizer Control Input pin 4
In Hardware mode, this pin together with EQC[3:0] are used for controlling
the transmit pulse shaping, transmit line build-out (LBO), receive monitoring
and also to select T1, E1 or J1 modes of operation. See Table 5 for descrip-
tion of Transmit Equalizer Control bits.

Serial Data Input
Host mode, See "Serial Interface" on page 4.

EQC3

SDO

Equalizer Control Input pin 3
See EQC4/SDI description for further explanation for the usage of this pin.
Serial Data Output
Host mode, See "Serial Interface" on page 4.

EQC2

SCLK

Equalizer Control Input pin 2
See EQC4/SDI description for further explanation for the usage of this pin.
Serial Interface Clock Input
Host mode, See "Serial Interface" on page 4.

EQC1

Equalizer Control Input pin 1
See EQC4/SDI description for further explanation for the usage of this pin.
Chip Select Input
Host mode, See "Serial Interface" on page 4.

EQC0

INT

Equalizer Control Input pin 0
See EQC4/SDI description for further explanation for the usage of this pin.
Interrupt Output
Host mode, See "Serial Interface" on page 4.

LOOP1

LOOP0

MODE

Normal Mode

Local Loop-Back

Remote Loop-Back

Digital Loop-Back

áç

XRT83L30

SINGLE-CHANNEL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR

PRELIMINARY

REV. P1.3.0

ALARM FUNCTION/OTHER

IGNAL

AME

YPE

ESCRIPTION

ATAOS

Automatic Transmit "All Ones" Pattern
In Hardware mode, a "High" level on this pin enables the automatic transmis-
sion of an "All Ones" AMI pattern from the transmitter when the receiver has
detected an LOS condition. A "Low" level on this pin disables this function.

OTE

: This pin is internally pulled "Low" with a 50k

resistor.

ICT

In-Circuit Testing (active "Low")
When this pin is tied "Low", all output pins are forced to a "High" impedance
state for in-circuit testing.
Pulling RESET "Low" while ICT pin is also "Low" will put the chip in factory
test mode. This condition should never happen during normal operation.

OTE

: Internally pulled "High" with a 50k

resistor.

NLCDE1
NLCDE0

33
34

Network Loop Code Detection Enable pin 1
Network Loop Code Detection Enable pin 0
NLCDE[1:0] pins are used to control the Loop-Code detection according to
the following table:

When NLCDE1="0" and NCLDE0="1", or NLCDE1="1" and NLCDE0="0", the
chip is manually programed to monitor the receive data for the Loop-Up or
Loop-Down code respectively. When the presence of the "00001" or "001"
pattern is detected for more than 5 seconds, the NLCD pin is set to "1" and
the host has the option to activate the loop-back function manually.

Setting the NLCDE1="1" and NLCDE0="1" enables the Automatic Loop-
Code detection and Remote-Loop-Back activation mode. As this mode is ini-
tiated, the state of the NLCD pin is reset to "0" and the chip is programmed to
monitor the receive data for the Loop-Up Code. If the "00001" pattern is
detected for longer than 5 seconds, the NLCD pin is set to "1", Remote Loop-
Back is activated and the chip is automatically programed to monitor the
receive data for the Loop-Down code. The NLCD pin stays "High" even after
the chip stops receiving the Loop-Up code. The remote Loop-Back condition
is removed when the chip receives the Loop-Down code for more than 5 sec-
onds or if the Automatic Loop-Code detection mode is terminated.

INSBPV

Insert Bipolar Violation
When this pin transitions from "0" to "1", a bipolar violation is inserted in the
transmitted data stream. Bipolar violation can be inserted either in the QRSS
pattern, or input data when operating in single-rail mode. The state of this pin
is sampled on the rising edge of TCLK.

OTE

: To ensure the insertion of a bipolar violation, this pin should be reset

to a "0" prior to setting to a "1".

NLCDE1

NLCDE0

Function

Disable Loop-Code

Detection

Detect Loop-Up Code in

Receive Data

Automatic Loop-Code

Detection

Detect Loop-Down Code in

Receive Data

XRT83L30

áç

SINGLE-CHANNEL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR

REV. P1.3.0

PRELIMINARY

NLCD

Network Loop-Code Detection Output pin
This pin operates differently in the Manual or the Automatic Network Loop-
Code detection modes.

In the Manual Loop-Code detection mode (NLCDE1 ="0" and NLCDE0 ="1",
or NLCDE1 ="1" and NLCDE0 ="0") this pin gets set to "1" as soon as the
Loop-Up ("00001") or Loop-Down ("001") code is detected in the receive data
for longer than 5 seconds. The NLCD pin stays in the "1" state for as long as
the chip detects the presence of the Loop-Code in the receive data and it is
reset to "0" as soon as it stops receiving it.

When the Automatic Loop-Code detection mode (NLCDE1 ="1" and
NLCDE0 ="1") is initiated, the NLCD output pin is reset to "0" and the chip is
programmed to monitor the receive input data for the Loop-Up Code. The
NLCD pin is set to a "1" to indicate that the Network Loop Code is detected
for more than 5 seconds. Simultaneously the Remote Loop-Back condition is
automatically activated and the chip is programmed to monitor the receive
data for the Network Loop-Down Code. The NLCD pin stays in the "1" state
for as long as the Remote Loop-Back condition is in effect even if the chip
stops receiving the Loop-Up Code. Remote Loop-Back is removed if the chip
detects the "001" pattern for longer than 5 seconds in the receive data.
Detecting the "001" pattern also results in resetting the NLCD output pin.

AISD

Alarm Indication Signal Detect Output pin
This pin is set to "1" to indicate that an All Ones Signal is detected by the
receiver. The value of this pin is based on the current status of Alarm Indica-
tion Signal detector.

QRPD

Quasi-random Pattern Detection Output pin
This pin is set to "1" to indicate that the receiver is currently in synchroniza-
tion with the QRSS pattern. The value of this pin is based on the current sta-
tus of Quasi-random pattern detector.

IGNAL

AME

YPE

ESCRIPTION

XRT83L30

áç

ONE-CHANNEL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR

REV. P1.3.0

PRELIMINARY

FUNCTIONAL DESCRIPTION

The XRT83L30 is a fully integrated single channel long-haul and short-haul transceiver intended for T1, J1 or
E1 systems. Simplified block diagrams of the device are shown in

Figure 1

, Host mode and

Figure 2

Hardware mode. The XRT83L30 can receive signals that have been attenuated from 0 to 36dB at 772kHz (0 to
6000 feet cable loss) for T1 and from 0 to 43dB at 1024kHz for E1 systems.

In T1 applications, the XRT83L30 can generate five transmit pulse shapes to meet the short-haul Digital Cross-
connect (DSX-1) template requirement as well as four CSU Line Build-Out (LBO) filters of 0dB, -7.5dB, -15dB
and -22.5dB as required by FCC rules. It also provides programmable transmit output pulse generator that can
be used for output pulse shaping allowing performance improvement over a wide variety of conditions. The
operation and configuration of the XRT83L30 can be controlled through a serial microprocessor Host interface
or, by Hardware control.

MASTER CLOCK GENERATOR

Using a variety of external clock sources, the on-chip frequency synthesizer generates the T1 (1.544MHz) or
E1 (2.048MHz) master clocks necessary for the transmit pulse shaping and receive clock recovery circuit.

There are two master clock inputs MCLKE1 and MCLKT1. In systems where both T1 and E1 master clocks are
available these clocks can be connected to the respective pins.

In systems that have only one master clock source available (E1 or T1), that clock should be connected to both
MCLKE1 and MCLKT1 inputs for proper operation. T1 or E1 master clocks can be generated from 8kHz,
16kHz, 56kHz, 64kHz, 128kHz and 256kHz external clocks under the control of CLKSEL[2:0] inputs according
to

Table 1

OTE

: EQC[4:0] determine the T1/E1 operating mode. See

Table 5

for details.

IGURE

4. T

NPUT

LOCK

OURCE

IGURE

5. O

NPUT

LOCK

OURCE

M C LK E 1

M C LK T1

M C LK O U T

1.544M H z
or
2.048M H z

2.048M H z

+/-50ppm

1.544M H z

+/-50ppm

Tw o Input C lo ck S ources

M C LK E 1

M C LK T1

M C LK O U T

1.544M H z
or
2.048M H z

O ne Input C lock S ource

Input C lock O ptions

8kH z

16kH z
56kH z

64kH z

128kH z
256kH z

1.544M H z
2.048M H z

áç

XRT83L30

ONE-CHANNEL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR

PRELIMINARY

REV. P1.3.0

In Host mode the programming is achieved through the corresponding interface control bits, the state of the
CLKSEL[2:0] control bits and the state of the MCLKRATE interface control bit.

RECEIVER

RECEIVER INPUT

At the receiver input, a cable attenuated AMI signal can be coupled to the receiver through a capacitor or a 1:1
transformer. The input signal is first applied to a selective equalizer for signal conditioning. The maximum
equalizer gain is up to 36dB for T1 and 43dB for E1 modes. The equalized signal is subsequently applied to a
peak detector which in turn controls the equalizer settings and the data slicer. The slicer threshold for both E1
and T1 is typically set at 50% of the peak amplitude at the equalizer output. After the slicers, the digital
representation of the AMI signals are applied to the clock and data recovery circuit. The recovered data
subsequently goes through the jitter attenuator and decoder (if selected) for HDB3 or B8ZS decoding before
being applied to the RPOS/RDATA and RNEG/LCV pins. Clock recovery is accomplished by a digital phase-
locked loop (DPLL) which does not require any external components and can tolerate high levels of input jitter
that meets or exceeds the ITU-G.823 and TR-TSY000499 standards.

In Hardware mode only, this receive channel is turned on upon power-up and is always on. In Host mode, the
receiver can be turned on or off with the RXON bit.

See "Microprocessor Register #2 bit description" on

page 48.

ABLE

1: M

ASTER

LOCK

ENERATOR

MCLKE1

MCLKT1

CLKSEL2

CLKSEL1

CLKSEL0

MCLKRATE

ASTER

LOCK

2048

1544

2048

1544

2048

1544

2048

1544

2048

1544

2048

1544

2048

1544

2048

1544

128

2048

128

1544

256

2048

256

1544

XRT83L30

áç

ONE-CHANNEL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR

REV. P1.3.0

PRELIMINARY

RECEIVE MONITOR MODE

In applications where Monitor mode is desired, the equalizer can be configured in a gain mode which handles
input signals attenuated resistively up to 29dB, along with 0 to 6dB cable attenuation for both T1 and E1
applications, refer to

Table 5

for details. This feature is available in both Hardware and Host modes.

RECEIVER LOSS OF SIGNAL (RLOS)

For compatibility with ITU G.775 requirements, the RLOS monitoring function is implemented using both
analog and digital detection schemes. If the analog RLOS condition occurs, a digital detector is activated to
count for 32 consecutive zeros in E1 (4096 bits in Extended Los mode, EXLOS = "1") or 175 consecutive zeros
in T1 before RLOS is asserted. RLOS is cleared when the input signal rises +3dB (built in hysteresis) above
the point at which it was declared and meets 12.5% ones density of 4 ones in a 32 bit window, with no more
than 16 consecutive zeros for E1. In T1 mode, RLOS is cleared when the input signal rises +3dB (built in
hysteresis) above the point at which it was declared and contains 16 ones in a 128 bit window with no more
than 100 consecutive zeros in the data stream. When loss of signal occurs, RLOS register indication and
register status will change. If the RLOS register enable is set high (enabled), the alarm will trigger an interrupt
causing the interrupt pin (INT) to go low. Once the alarm status register has been read, it will automatically
reset upon read (RUR), and the INT pin will return high.

Analog RLOS

Setting the Receiver Input to -15dB T1/E1 Short Haul Mode

By setting the receiver input to -15dB T1/E1 short haul mode, the equalizer will detect the incoming amplitude
and make adjustments by adding gain up to a maximum of +15dB normalizing the T1/E1 input signal.

OTE

: This setting refers to cable loss (frequency), not flat loss (resistive).

Once the T1/E1 input signal has been normalized to 0dB by adding the maximum gain (+15dB), the receiver
will declare RLOS if the signal is attenuated by an additional -9dB. The total cable loss at RLOS declaration is
typically -24dB (-15dB + -9dB). A 3dB hysteresis was designed so that transients will not trigger the RLOS to
clear. Therefore, the RLOS will typically clear at a total cable attenuation of -21dB. See

Figure 6

for a simplified

diagram.

Setting the Receiver Input to -29dB T1/E1 Gain Mode

By setting the receiver input to -29dB T1/E1 gain mode, the equalizer will detect the incoming amplitude and
make adjustments by adding gain up to a maximum of +29dB normalizing the T1/E1 input signal.

OTE

: This is the only setting that refers to flat loss (resistive). All other modes refer to cable loss (frequency).

Once the T1/E1 input signal has been normalized to 0dB by adding the maximum gain (+29dB), the receiver
will declare RLOS if the signal is attenuated by an additional -9dB. The total cable loss at RLOS declaration is

IGURE

6. S

IMPLIFIED

IAGRAM

-15dB T1/E1 S

HORT

AUL

ODE

AND

RLOS C

ONDITION

N orm alize d up to +15dB M ax

D eclare L O S

C lear LO S

-9dB

+3dB

C lear LO S

D eclare L O S

+3dB

-9dB

áç

XRT83L30

ONE-CHANNEL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR

PRELIMINARY

REV. P1.3.0

typically -38dB (-29dB + -9dB). A 3dB hysteresis was designed so that transients will not trigger the RLOS to
clear. Therefore, the RLOS will typically clear at a total flat loss of -35dB. See

Figure 7

for a simplified diagram.

Setting the Receiver Input to -36dB T1/E1 Long Haul Mode

By setting the receiver input to -36dB T1/E1 long haul mode, the equalizer will detect the incoming amplitude
and make adjustments by adding gain up to a maximum of +36dB normalizing the T1 input signal. This setting
refers to cable loss (frequency), not flat loss (resistive). Once the T1/E1 input signal has been normalized to
0dB by adding the maximum gain (+36dB), the receiver will declare RLOS if the signal is attenuated by an
additional -9dB. The total cable loss at RLOS declaration is typically -45dB (-36dB + -9dB). A 3dB hysteresis
was designed so that transients will not trigger the RLOS to clear. Therefore, the RLOS will typically clear at a
total cable attenuation of -42dB. See

Figure 8

for a simplified diagram.

E1 Extended RLOS

E1: Setting the Receiver Input to Extended RLOS

By setting the receiver input to extended RLOS, the equalizer will detect the incoming amplitude and make
adjustments by adding gain up to a maximum of +43dB normalizing the E1 input signal. This setting refers to
cable loss (frequency), not flat loss (resistive). Once the E1 input signal has been normalized to 0dB by adding
the maximum gain (+43dB), the receiver will declare RLOS if the signal is attenuated by an additional -9dB.

IGURE

7. S

IMPLIFIED

IAGRAM

-29dB T1/E1 G

AIN

ODE

AND

RLOS C

ONDITION

IGURE

8. S

IMPLIFIED

IAGRAM

-36dB T1/E1 L

ONG

AUL

ODE

AND

RLOS C

ONDITION

N orm alize d up to +29dB M ax

D eclare L O S

C lear LO S

-9dB

+3dB

C lear LO S

D eclare L O S

+3dB

-9dB

N orm alize d up to +36dB M ax

D eclare L O S

C lear LO S

-9dB

+3dB

C lear LO S

D eclare L O S

+3dB

-9dB

XRT83L30

áç

ONE-CHANNEL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR

REV. P1.3.0

PRELIMINARY

The total cable loss at RLOS declaration is typically -52dB (-43dB + -9dB). A 3dB hysteresis was designed so
that transients will not trigger the RLOS to clear. Therefore, the RLOS will typically clear at a total cable
attenuation of -49dB. See

Figure 9

for a simplified diagram.

RECEIVE HDB3/B8ZS DECODER

The Decoder function is available in both Hardware and Host modes by controlling the TNEG/CODE pin or the
CODE interface bit. The decoder function is only active in single-rail Mode. When selected, receive data in this
mode will be decoded according to HDB3 rules for E1 and B8ZS for T1 systems. Bipolar violations that do not
conform to the coding scheme will be reported as Line Code Violation at the RNEG/LCV pin. The length of the
LCV pulse is one RCLK cycle for each code violation. Excessive number of zeros in the receive data stream is
also reported as an error at the same output pin. If AMI decoding is selected in single rail mode, every bipolar
violation in the receive data stream will be reported as an error at the RNEG/LCV pin.

RECOVERED CLOCK (RCLK) SAMPLING EDGE

This feature is available in both Hardware and Host modes. In Host mode, the sampling edge of RCLK output
can be changed through the interface control bit RCLKE. If a "1" is written in the RCLKE interface bit, receive
data output at RPOS/RDATA and RNEG/LCV are updated on the falling edge of RCLK. Writing a "0" to the
RCLKE register, updates the receive data on the rising edge of RCLK. In Hardware mode the same feature is
available under the control of the RCLKE pin.

IGURE

9. S

IMPLIFIED

IAGRAM

XTENDED

RLOS

MODE

(E1 O

NLY

)

IGURE

10. R

ECEIVE

LOCK

AND

UTPUT

ATA

IMING

N orm alize d up to +45dB M ax

D eclare L O S

C lear LO S

-9dB

+3dB

C lear LO S

D eclare L O S

+3dB

-9dB

RCLK

RPOS

RNEG

áç

XRT83L30

ONE-CHANNEL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR

PRELIMINARY

REV. P1.3.0

JITTER ATTENUATOR

To reduce phase and frequency jitter in the recovered clock, the jitter attenuator can be placed in the receive
signal path. The jitter attenuator uses a data FIFO (First In First Out) with a programmable depth that can vary
between 2x32 and 2x64. The jitter attenuator can also be placed in the transmit signal path or disabled
altogether depending upon system requirements. The jitter attenuator, other than using the master clock as
reference, requires no external components. With the jitter attenuator selected, the typical throughput delay
from input to output is 16 bits for 32 bit FIFO size or 32 bits for 64 bit FIFO size. When the read and write
pointers of the FIFO in the jitter attenuator are within two bits of over-flowing or under-flowing, the bandwidth of
the jitter attenuator is widened to track the short term input jitter, thereby avoiding data corruption. When this
situation occurs, the jitter attenuator will not attenuate input jitter until the read/write pointer's position is outside
the two bits window. Under normal condition, the jitter transfer characteristic meets the narrow bandwidth
requirement as specified in ITU- G.736, ITU- I.431 and AT&T Pub 62411 standards.

In T1 mode the Jitter Attenuator Bandwidth is always set to 3Hz. In E1 mode, the bandwidth can be reduced
through the JABW control signal. When JABW is set "High" the bandwidth of the jitter attenuator is reduced
from 10Hz to 1.5Hz. Under this condition the FIFO length is automatically set to 64 bits and the 32 bits FIFO
length will not be available in this mode.

GAPPED CLOCK (JA MUST BE ENABLED IN THE TRANSMIT PATH)

The XRT83L30 LIU is ideal for multiplexer or mapper applications where the network data crosses multiple
timing domains. As the higher data rates are de-multiplexed down to T1 or E1 data, stuffing bits are removed
which can leave gaps in the incoming data stream. If the jitter attenuator is enabled in the transmit path, the
32-Bit or 64-Bit FIFO is used to smooth the gapped clock into a steady T1 or E1 output. The maximum gap
width is shown in Table 2.

OTE

: If the LIU is used in a loop timing system, the jitter attenuator should be enabled in the receive path.

ABLE

2: M

AXIMUM

IDTH

FOR

ULTIPLEXER

APPER

PPLICATIONS

FIFO D

EPTH

AXIMUM

IDTH

32-Bit

20 UI

64-Bit

50 UI

XRT83L30

áç

ONE-CHANNEL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR

REV. P1.3.0

PRELIMINARY

ARBITRARY PULSE GENERATOR

In T1 mode only, the arbitrary pulse generator divides the pulse into eight individual segments. Each segment
is set by a 7-Bit binary word by programming the appropriate register. This allows the system designer to set
the overshoot, amplitude, and undershoot for a unique line build out. The MSB (bit 7) is a sign-bit. If the sign-bit
is set to "1", the segment will move in a positive direction relative to a flat line (zero) condition. If this sign-bit is
set to "0", the segment will move in a negative direction relative to a flat line condition. A pulse with numbered
segments is shown in Figure 11.

OTE

: By default, the arbitrary segments are programmed to 0x00h. The transmitter output will result in an all zero pattern

to the line.

TRANSMITTER

DIGITAL DATA FORMAT

Both the transmitter and receiver can be configured to operate in dual or single-rail data formats. This feature is
available under both Hardware and Host control modes. The dual or single-rail data format is determined by
the state of the SR/DR pin in Hardware mode or SR/DR interface bit in the Host mode. In single-rail mode,
transmit clock and NRZ data are applied to TCLK and TPOS/TDATA pins respectively. In single-rail and
Hardware mode the TNEG/CODE input can be used as the CODES function. With TNEG/CODE tied "Low",
HDB3 or B8ZS encoding and decoding are enabled for E1 and T1 modes respectively. With TNEG/CODE tied
"High", the AMI coding scheme is selected. In both dual or single-rail modes of operations, the transmitter
converts digital input data to a bipolar format before being transmitted to the line.

TRANSMIT CLOCK (TCLK) SAMPLING EDGE

Serial transmit data at TPOS/TDATA and TNEG/CODE are clocked into the XRT83L30 under the
synchronization of TCLK. With a "0" written to the TCLKE interface bit, or by pulling the TCLKE pin "Low", input
data is sampled on the falling edge of TCLK. The sampling edge is inverted with a "1" written to TCLKE
interface bit, or by connecting the TCLKE pin "High".

IGURE

11. A

RBITRARY

ULSE

EGMENT

SSIGNMENT

Segment

0xn8

0xn9

0xna

0xnb

0xnc

0xnd

0xne

0xnf

áç

XRT83L30

ONE-CHANNEL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR

PRELIMINARY

REV. P1.3.0

TRANSMIT HDB3/B8ZS ENCODER

The Encoder function is available in both Hardware and Host modes basis by controlling the TNEG/CODE pin
or CODES interface bit. The encoder is only available in single-rail mode. In E1 mode and with HDB3 encoding
selected, any sequence with four or more consecutive zeros in the input serial data from TPOS/TDATA, will be
removed and replaced with 000V or B00V, where "B" indicates a pulse conforming with the bipolar rule and "V"
representing a pulse violating the rule. An example of HDB3 Encoding is shown in

Table 3

. In a T1 system, an

input data sequence with eight or more consecutive zeros will be removed and replaced using the B8ZS
encoding rule. An example of Bipolar with 8 Zero Substitution (B8ZS) encoding scheme is shown in

Table 4

Writing a "

" into the CODES interface bit or connecting the TNEG/CODE pin to a "High" level selects the AMI

coding for both E1 or T1 systems.

IGURE

12. T

RANSMIT

LOCK

AND

NPUT

ATA

IMING

ABLE

3: E

XAMPLES

HDB3 E

NCODING

UMBER

PULSE

BEFORE

NEXT

ZEROS

EXT

BITS

Input

0000

HDB3 (case1)

odd

000V

HDB3 (case2)

even

B00V

ABLE

4: E

XAMPLES

B8ZS E

NCODING

ASE

RECEDING

ULSE

EXT

8 B

ITS

Input

00000000

B8ZS

000VB0VB

AMI Output

000+ -0- +

ASE

Input

00000000

B8ZS

000VB0VB

AMI Output

000- +0+ -

TCLK

TPOS/TDATA

TNEG

XRT83L30

áç

ONE-CHANNEL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR

REV. P1.3.0

PRELIMINARY

DRIVER FAILURE MONITOR (DMO)

The driver monitor circuit is used to detect transmit driver failure by monitoring the activities at TTIP and
TRING. Driver failure may be caused by a short circuit in the primary transformer or system problems at the
transmit input. If the transmitter has no output for more than 128 clock cycles, the corresponding DMO pin goes
"High" and remains "High" until a valid transmit pulse is detected. In Host mode, the failure of the transmit
channel is reported in the corresponding interface bit. If the DMOIE bit is also enabled, any transition on the
DMO interface bit will generate an interrupt. The driver failure monitor is supported in both Hardware and Host
modes.

TRANSMIT PULSE SHAPER & LINE BUILD OUT (LBO) CIRCUIT

The transmit pulse shaper circuit uses the high speed clock from the Master timing generator to control the
shape and width of the transmitted pulse. The internal high-speed timing generator eliminates the need for a
tightly controlled transmit clock (TCLK) duty cycle. With the jitter attenuator not in the transmit path, the
transmit output will generate no more than 0.025Unit Interval (UI) peak-to-peak jitter. In Hardware mode, the
state of the EQC[4:0] pins determine the transmit pulse shape. In Host mode transmit pulse shape can be
controlled using the interface bits EQC[4:0]. The chip supports five fixed transmit pulse settings for T1 Short-
haul applications plus a fully programmable waveform generator for arbitrary transmit output pulse shapes.
Transmit Line Build-Outs for T1 long-haul application are supported from 0dB to -22.5dB in three 7.5dB steps.
The choice of the transmit pulse shape and LBO under the control of the interface bits are summarized in

Table 5

. For CSU LBO transmit pulse design information, refer to ANSI T1.403-1993 Network-to-Customer

Installation specification, Annex-E.

OTE

: EQC[4:0] determine the T1/E1 operating mode of the XRT83L30. When EQC4 = "1" and EQC3 = "1", the XRT83L30

is in the E1 mode, otherwise it is in the T1/J1 mode.

ABLE

5: R

ECEIVE

QUALIZER

ONTROL

AND

RANSMIT

INE

UILD

-O

ETTINGS

EQC4 EQC3

EQC2

EQC1

EQC0

E1/T1 M

ODE

& R

ECEIVE

ENSITIVITY

RANSMIT

LBO

ABLE

ODING

T1 Long Haul/36dB

0dB

100

/ TP

B8ZS

T1 Long Haul/36dB

-7.5dB

100

/ TP

B8ZS

T1 Long Haul/36dB

-15dB

100

/ TP

B8ZS

T1 Long Haul/36dB

-22.5dB

100

/ TP

B8ZS

T1 Long Haul/45dB

0dB

100

/ TP

B8ZS

T1 Long Haul/45dB

-7.5dB

100

/ TP

B8ZS

T1 Long Haul/45dB

-15dB

100

/ TP

B8ZS

T1 Long Haul/45dB

-22.5dB

100

/ TP

B8ZS

T1 Short Haul/15dB

0-133 ft./ 0.6dB

100

/ TP

B8ZS

T1 Short Haul/15dB

133-266 ft./ 1.2dB

100

/ TP

B8ZS

T1 Short Haul/15dB

266-399 ft./ 1.8dB

100

/ TP

B8ZS

T1 Short Haul/15dB

399-533 ft./ 2.4dB

100

/ TP

B8ZS

T1 Short Haul/15dB

533-655 ft./ 3.0dB

100

/ TP

B8ZS

T1 Short Haul/15dB

Arbitrary Pulse

100

/ TP

B8ZS

XRT83L30

áç

ONE-CHANNEL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR

REV. P1.3.0

PRELIMINARY

TRANSMIT AND RECEIVE TERMINATIONS

The XRT83L30 is a versatile LIU that can be programmed to use one Bill of Materials (BOM) for worldwide
applications for T1, J1 and E1. For specific applications the internal terminations can be disabled to allow the
use of existing components and/or designs.

RECEIVER

NTERNAL

ECEIVE

ERMINATION

ODE

In Hardware mode, RXTSEL (Pin 44) can be tied "High" to select internal termination mode or tied "Low" to
select external termination mode. By default the XRT83L30 is set for external termination mode at power up or
at Hardware reset.

In Host mode, bit 7 in the appropriate register, (

Table 20, "Microprocessor Register #1, Bit Description," on

page 47

), is set "High" to select the internal termination mode for the receive channel.

If the internal termination mode (RXTSEL = "1") is selected, the effective impedance for E1, T1 or J1 can be
achieved either with an internal resistor or a combination of internal and external resistors as shown in

Table 7

ABLE

6: R

ECEIVE

ERMINATION

ONTROL

RXTSEL

RX TERMINATION

EXTERNAL

INTERNAL

IGURE

13. S

IMPLIFIED

IAGRAM

FOR

THE

NTERNAL

ECEIVE

AND

RANSMIT

ERMINATION

ODE

TTIP

TRING

1:2

, 100

110

or 120

0.68

int

TTIP

TRING

Line Driver

RTIP

RRING

1:1

RTIP

RRING

Equalizer

int

TPOS

TNEG

TCLK

RPOS

RNEG

RCLK

, 100

110

or 120

XRT83L30

áç

ONE-CHANNEL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR

REV. P1.3.0

PRELIMINARY

TRANSMITTER

RANSMIT

ERMINATION

ODE

In Hardware mode, TXTSEL (Pin 45) can be tied "High" to select internal termination mode or tied "Low" for
external termination. In Host mode, bit 6 in the appropriate register is set "High" to select the internal
termination mode for the transmit channel, see

Table 19, "Microprocessor Register #1 bit description," on

page 46

For internal termination, the transformer turns ratio is always 1:2. In internal mode, no external resistors are
used. An external capacitor of 0.68

F is used for proper operation of the internal termination circuitry, see

Figure 13

XTERNAL

RANSMIT

ERMINATION

ODE

By default the XRT83L30 is set for external termination mode at power up or at Hardware reset.

When external transmit termination mode is selected, the internal termination circuitry is disabled. The value of
the external resistors is chosen for a specific application according to the turns ratio selected by TRATIO (Pin
26) in Hardware mode or bit 0 in the appropriate register in Host mode, see

Table 10

and

Table 21,

"Microprocessor Register #3 bit description," on page 50

Figure 14

is a simplified block diagram for T1 (100

)

in the external termination mode.

Figure 15

is a simplified block diagram for E1 (75

) in the external

termination mode.

IGURE

15. S

IMPLIFIED

IAGRAM

FOR

XTERNAL

ERMINATION

ODE

(RXTSEL= 0)

ABLE

8: T

RANSMIT

ERMINATION

ONTROL

TXTSEL

TX TERMINATION

RANSFORMER

ATIO

EXTERNAL

1:2.45

INTERNAL

1:2

ABLE

9: T

ERMINATION

ELECT

ONTROL

TERSEL1

TERSEL0

TERMINATION

100

110

120

9.1

TTIP

TRING

RTIP

RRING

XRT83L30 LIU

1:2

1:1

áç

XRT83L30

ONE-CHANNEL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR

PRELIMINARY

REV. P1.3.0

Table 11

summarizes the transmit terminations.

REDUNDANCY APPLICATIONS

Telecommunication system design requires signal integrity and reliability. When a T1/E1 primary line card has
a failure, it must be swapped with a backup line card while maintaining connectivity to a backplane without
losing data. System designers can achieve this by implementing common redundancy schemes with the
XRT83L30 Line Interface Unit (LIU). The XRT83L30 offers features that are tailored to redundancy applications
while reducing the number of components and providing system designers with solid reference designs. These
features allow system designers to implement redundancy applications that ensure reliability. The Internal
Impedance mode eliminates the need for external relays when using the 1:1 and 1+1 redundancy schemes.

ABLE

10: T

RANSMIT

ERMINATION

ONTROL

TRATIO

URNS

ATIO

1:2

1:2.45

ABLE

11: T

RANSMIT

ERMINATIONS

TERSEL1

TERSEL0

TXTSEL

TRATIO

int

ext

EXTERNAL

SET

CONTROL

BITS

n, R

ext

AND

ext

ARE

SUGGESTED

SETTINGS

INTERNAL

100

2.45

3.1

0.68

110

2.45

3.1

27.5

0.68

2.45

6.2

9.1

18.75

0.68

120

2.45

6.2

9.1

0.68

XRT83L30

áç

ONE-CHANNEL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR

REV. P1.3.0

PRELIMINARY

PROGRAMMING CONSIDERATIONS

In many applications switching the control of the transmitter outputs and the receiver line impedance to
hardware control will provide faster transmitter ON/OFF switching.

In Host Mode, there are two bits in register 18 (12H) that control the transmitter outputs and the Rx line
impedance select, TXONCNTL (Bit 5) and TERCNTL (Bit 4).

Setting bit-5 (TXONCNTL) to a "1" transfers the control of the Transmit On/Off function to the TXON Hardware
control pin (pin 58).

Setting bit-4 (TERCNTL) to a "1" transfers the control of the Rx line impedance select (RXTSEL) to the
RXTSEL Hardware control pin (pin 44).

Either mode works well with redundancy applications. The user can determine which mode has the fastest
switching time for a unique application.

TYPICAL REDUNDANCY SCHEMES

·1:1 One backup card for every primary card (Facility Protection)

·1+1 One backup card for every primary card (Line Protection)

·N+1One backup card for N primary cards

1:1 REDUNDANCY

A 1:1 facility protection redundancy scheme has one backup card for every primary card. When using 1:1
redundancy, the backup card has its transmitters tri-stated and its receivers in high impedance. This eliminates
the need for external relays and provides one bill of materials for all interface modes of operation. The transmit
and receive sections of the LIU device are described separately.

1+1 REDUNDANCY

A 1+1 line protection redundancy scheme has one backup card for every primary card, and the receivers on
the backup card are monitoring the receiver inputs. Therefore, the receivers on both cards need to be active.
The transmit outputs require no external resistors. The transmit and receive sections of the LIU device are
described separately.

TRANSMIT 1:1 & 1+1 REDUNDANCY

For 1:1 and 1+1 redundancy, the transmitters on the primary and backup card should be programmed for
Internal Impedance mode. The transmitters on the backup card should be tri-stated. Select the appropriate
impedance for the desired mode of operation, T1/E1/J1. A 0.68uF capacitor is used in series with TTIP for
blocking DC bias. See

Figure 16

for a simplified block diagram of the transmit section for 1:1 and 1+1

redundancy scheme.

OTE

: For simplification, the over voltage protection circuitry was omitted.

áç

XRT83L30

ONE-CHANNEL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR

PRELIMINARY

REV. P1.3.0

RECEIVE 1:1 & 1+1 REDUNDANCY

For 1:1 and 1+1 redundancy, the receivers on the primary card should be programmed for Internal Impedance
mode. The receivers on the backup card should be programmed for External Impedance mode. Since there is
no external resistor in the circuit, the receivers on the backup card will be high impedance. This key design
feature eliminates the need for relays and provides one bill of materials for all interface modes of operation.
Select the impedance for the desired mode of operation, T1/E1/J1. To swap the primary card, set the backup
card to Internal Impedance mode, then the primary card to External Impedance mode. See

Figure 17

for a

simplified block diagram of the receive section for a 1:1 and 1+1 redundancy scheme.

OTE

: For simplification, the over voltage protection circuitry was omitted.

IGURE

16. S

IMPLIFIED

LOCK

IAGRAM

THE

RANSMIT

ECTION

FOR

1:1 & 1+1 R

EDUNDANCY

IGURE

17. S

IMPLIFIED

LOCK

IAGRAM

- R

ECEIVE

ECTION

FOR

1:1

AND

1+1 R

EDUNDANCY

T1/E1 Line

Backplane Interface

Primary Card

Backup Card

XRT83L30

Line Interface Card

0.68

TxTSEL=1, Internal

1:2

RxTSEL=0, External

RxTSEL=1, Internal

Backplane Interface

Primary Card

Backup Card

XRT83L30

Line Interface Card

T1/E1 Line

1:1

XRT83L30

áç

ONE-CHANNEL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR

REV. P1.3.0

PRELIMINARY

N+1 REDUNDANCY

N+1 redundancy has one backup card for N primary cards. Due to impedance mismatch and signal contention,
external relays are necessary when using this redundancy scheme. The advantage of relays is that they create
complete isolation between the primary cards and the backup card. This allows all transmitters and receivers
on the primary cards to be configured in internal impedance mode, providing one bill of materials for all
interface modes of operation. The transmit and receive sections of the XRT83L30 are described separately.

TRANSMIT

For N+1 redundancy, the transmitters on all cards should be programmed for internal impedance mode
providing one bill of materials for T1/E1/J1. The transmitters on the backup card do not have to be tri-stated. To
swap the primary card, close the desired relays, and tri-state the transmitters on the failed primary card. A
0.68

F capacitor is used in series with TTIP for blocking DC bias. See

Figure 18

for a simplified block diagram

of the transmit section for an N+1 redundancy scheme.

OTE

: For simplification, the over voltage protection circuitry was omitted.

IGURE

18. S

IMPLIFIED

LOCK

IAGRAM

- T

RANSMIT

ECTION

FOR

N+1 R

EDUNDANCY

Backplane Interface

Primary Card

XRT83L30

Line Interface Card

0.68

T1/E1 Line

Primary Card

XRT83L30

Primary Card

XRT83L30

Backup Card

XRT83L30

T1/E1 Line

TxTSEL=1, Internal

1:2

0.68

1:2

XRT83L30

áç

ONE-CHANNEL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR

REV. P1.3.0

PRELIMINARY

PATTERN TRANSMIT AND DETECT FUNCTION

Several test and diagnostic patterns can be generated and detected by the chip. In Hardware mode the
channel can be programmed to transmit an All Ones pattern by applying a "High" level to the corresponding
TAOS pin. In Host mode, the three interface bits TXTEST[2:0] control the pattern generation and detection
according to

Table 12

TRANSMIT ALL ONES (TAOS)

This feature is available in both Hardware and Host modes. When the Hardware pins or interface bits
TXTEST2="0", TXTEST1="0" and TXTEST0="1", the transmitter ignores input from TPOS/TDATA and TNEG
pins and sends a continuous AMI encoded all ones signal to the line using TCLK clock as the reference. When
TCLK is not available, MCLK is used. In addition, when the Hardware pin or the interface bit ATAOS is
activated, the chip will automatically transmit the All Ones data when the receiver detects an RLOS condition.
The operation of this feature requires that TCLK not be tied "Low".

NETWORK LOOP CODE DETECTION AND TRANSMISSION

This feature is available in both Hardware and Host modes. When the Hardware pins or interface bits
TXTEST2="0", TXTEST1="1" and TXTEST0="0" the chip is enabled to transmit the "00001" Network Loop-Up
Code from a request for a loop-back condition from the remote terminal. Simultaneously setting the interface
bits NLCDE1="0" and NLCDE0="1" enables the Network Loop-Up code detection in the receiver. If the "00001"
Network Loop-Up code is detected in the receive data for longer than 5 seconds, the NLCD bit in the interface
register is set indicating that the remote terminal has activated remote Loop-back and the chip is receiving its
own transmitted data. When Network Loop-Up code is being transmitted the XRT83L30 will ignore the Auto-
matic Loop-Code detection and Remote Loop-back activation (NLCDE1="1", NLCDE0="1", if activated) in
order to avoid activating Remote Digital Loop-back automatically when the remote terminal responds to the
Loop-back request.

When TXTEST2="0", TXTEST1="1" and TXTEST0="1" the chip is enabled to transmit the Network Loop-Down
Code "001" from the transmitter requesting the remote terminal the removal of the Loop-Back condition.

In both Hardware and Host modes the receiver is capable of monitoring the contents of the receive data for
the presence of Loop-Up or Loop-Down code from the remote terminal. The Hardware pins or interface bits

ABLE

12: P

ATTERN

TRANSMISSION

CONTROL

TXTEST2

TXTEST1

TXTEST0

EST

ATTERN

Transmit Data

TAOS

TLUC

TLDC

TDQRSS

TDQRSS & INVQRSS

TDQRSS & INSBER

TDQRSS & INVQRSS & INSBER

áç

XRT83L30

ONE-CHANNEL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR

PRELIMINARY

REV. P1.3.0

NLCDE[1:0] control the Loop-Code detection according to Table 13

Setting the Hardware pins or interface bits NLCDE1="0" and NLCDE0="1" activates the detection of the Loop-
Up code in the receive data. If the "00001" Network Loop-Up code is detected in the receive data for longer
than 5 seconds the NLCD interface bit is set to "1" and stays in this state for as long as the receiver continues
to receive the Network Loop-Up Code. In this mode if the NLCD interrupt is enabled, the chip will initiate an
interrupt on every transition of NLCD. The host has the option to ignore the request from the remote terminal,
or to respond to the request and manually activate Remote Loop-Back. The host can subsequently activate the
detection of the Loop-Down Code by setting NLCDE1="1" and NLCDE0="0". In this case, receiving the "001"
Loop-Down Code for longer than 5 seconds will set the NLCD bit to "1" and if the NLCD interrupt is enabled,
the chip will initiate an interrupt on every transition of NLCD. The host can respond to the request from the
remote terminal and remove Loop-Back condition. In the manual Network Loop-Up (NLCDE1="0" and
NLCDE0="1") and Loop-Down (NLCDE1="1" and NLCDE0="0") Code detection modes, the NLCD pin or
interface bit will be set to "1" upon receiving the corresponding code in excess of 5 seconds in the receive data.
In Host mode the chip will initiate an interrupt any time the status of the NLCD bit changes and the Network
Loop-code interrupt is enabled.

Setting the Hardware pins or interface bits NLCDE1="1" and NLCDE0="1" enables the automatic Loop-Code
detection and Remote Loop-Back activation mode if, TXTEST[2:0] is NOT equal to "110". As this mode is
initiated, the state of the NLCD pin or interface bit is reset to "0" and the chip is programmed to monitor the
receive input data for the Loop-Up Code. If the "00001" Network Loop-Up Code is detected in the receive data
for longer than 5 seconds in addition to setting the NLCD pin or interface bit, Remote loop-back is automatically
activated. The chip stays in remote loop-back even if it stops receiving the "00001" pattern. After the chip
detects the Loop-Up code, sets the NLCD pin (bit) and enters Remote loop-back, it automatically starts
monitoring the receive data for the Loop-Down code. In this mode however, the NLCD pin (bit) stays set even if
the receiver stops receiving the Loop-Up code, which is an indication to the host that the Remote loop-back is
still in effect. Remote loop-back is removed if the chip detects the "001" Loop-Down code for longer than 5
seconds. Detecting the "001" code also results in resetting the NLCD pin (bit) and initiating an interrupt. The
Remote loop-back can also be removed by taking the chip out of the Automatic detection mode by
programming it to operate in a different state. The chip will not respond to remote loop-back request if an
Analog loop-back is activated locally. When programmed in Automatic detection mode the NLCD pin (bit) stays
"High" for the whole time the Remote loop-back is activated and in the Host mode it initiates an interrupt any
time the status of the NLCD bit changes provided the Network Loop-code interrupt is enabled.

TRANSMIT AND DETECT QUASI-RANDOM SIGNAL SOURCE (TDQRSS)

The XRT83L30 includes a QRSS pattern generation and detection block for diagnostic purposes that can be
activated only in the Host mode by setting the interface bits TXTEST2="1", TXTEST1="0" and TXTEST0="0".

For T1 systems, the QRSS pattern is a 2

-1pseudo-random bit sequence (PRBS) with no more than 14

consecutive zeros. For E1 systems, the QRSS pattern is 2

-1 PRBS with an inverted output. With QRSS and

Analog Local Loop-Back enabled simultaneously, and by monitoring the status of the QRPD interface bit, all
main functional blocks within the transceiver can be verified.

When the receiver achieves QRSS synchronization with fewer than 4 errors in a 128 bits window, QRPD
changes from "Low" to "High". After pattern synchronization, any bit error will cause QRPD to go "Low" for one
clock cycle. If the QRPDIE bit is enabled, any transition on the QRPD bit will generate an interrupt.

ABLE

13: L

OOP

-C

ODE

ETECTION

ONTROL

NLCDE1

NLCDE0

CONDITION

Disable Loop-Code Detection

Detect Loop-Up Code in Receive Data

Detect Loop-Down Code in Receive Data

Automatic Loop-Code detection and Remote Loop-Back Activation

áç

XRT83L30

ONE-CHANNEL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR

PRELIMINARY

REV. P1.3.0

LOOP-BACK MODES

The XRT83L30 supports several Loop-Back modes under both Hardware and Host control. In Hardware
mode the two LOOP[1:0] pins control the Loop-Back functions according to

Table 14

In Host mode the Loop-Back functions are controlled by the three LOOP[2:0] interface bits. The LIU can be
programmed according to

Table 15

LOCAL ANALOG LOOP-BACK (ALOOP)

With Local Analog Loop-Back activated, the transmit data at TTIP and TRING are looped-back to the analog
input of the receiver. External inputs at RTIP/RRING in this mode are ignored while valid transmit data
continues to be sent to the line. Local Analog Loop-Back exercises most of the functional blocks of the
XRT83L30 including the jitter attenuator which can be selected in either the transmit or receive paths. Local
Analog Loop-Back is shown in

Figure 20

In this mode, the jitter attenuator (if selected) can be placed in the transmit or receive path.

ABLE

14: L

OOP

BACK

CONTROL

ARDWARE

MODE

LOOP1

LOOP0

OOP

BACK

ODE

None

Analog

Remote

Digital

ABLE

15: L

OOP

BACK

CONTROL

OST

MODE

LOOP2

LOOP1

LOOP0

OOP

BACK

ODE

None

Dual

Analog

Remote

Digital

IGURE

20. L

OCAL

NALOG

OOP

BACK

SIGNAL

FLOW

Data &

Clock

Recovery

Decoder

TPOS

TNEG

TCLK

RCLK

RPOS

RNEG

Encoder

Timing
Control

TTIP

TRING

RTIP

RRING

XRT83L30

áç

ONE-CHANNEL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR

REV. P1.3.0

PRELIMINARY

REMOTE LOOP-BACK (RLOOP)

With Remote Loop-Back activated, receive data after the jitter attenuator (if selected in the receive path) is
looped back to the transmit path using RCLK as transmit timing. In this mode transmit clock and data are
ignored, while RCLK and receive data will continue to be available at their respective output pins. Remote
Loop-Back with jitter attenuator selected in the receive path is shown in

Figure 21

In the Remote Loop-Back mode if the jitter attenuator is selected in the transmit path, the receive data from the
Clock and Data Recovery block is looped back to the transmit path and is applied to the jitter attenuator using
RCLK as transmit timing. In this mode the transmit clock and data are also ignored, while RCLK and received
data will continue to be available at their respective output pins. Remote Loop-Back with the jitter attenuator
selected in the transmit path is shown in

Figure 22

IGURE

21. R

EMOTE

OOP

BACK

MODE

WITH

JITTER

ATTENUATOR

SELECTED

RECEIVE

PATH

IGURE

22. R

EMOTE

OOP

BACK

MODE

WITH

JITTER

ATTENUATOR

SELECTED

RANSMIT

PATH

Decoder

Timing
Control

Data &

Clock

Recovery

TPOS

TNEG

TCLK

RCLK

RPOS

RNEG

Encoder

TTIP

TRING

RTIP

RRING

Decoder

Timing

Control

Clock &

Data

Recovery

TPOS

TNEG

TCLK

RCLK

RPOS

RNEG

Encoder

TTIP

TRING

RTIP

RRING

áç

XRT83L30

ONE-CHANNEL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR

PRELIMINARY

REV. P1.3.0

DIGITAL LOOP-BACK (DLOOP)

Digital Loop-Back or Local Loop-Back allows the transmit clock and data to be looped back to the
corresponding receiver output pins through the encoder/decoder and jitter attenuator. In this mode, receive
data and clock are ignored, but the transmit data will be sent to the line uninterrupted. This loop back feature
allows users to configure the line interface as a pure jitter attenuator. The Digital Loop-Back signal flow is
shown in

Figure 23

DUAL LOOP-BACK

Figure 24

depicts the data flow in dual-loopback. In this mode, selecting the jitter attenuator in the transmit path

will have the same result as placing the jitter attenuator in the receive path. In dual Loop-Back mode the
recovered clock and data from the line are looped back through the transmitter to the TTIP and TRING without
passing through the jitter attenuator. The transmit clock and data are looped back through the jitter attenuator
to the RCLK and RPOS/RDATA and RNEG pins.

IGURE

23. D

IGITAL

OOP

BACK

MODE

WITH

JITTER

ATTENUATOR

SELECTED

RANSMIT

PATH

IGURE

24. S

IGNAL

FLOW

UAL

LOOP

BACK

MODE

Decoder

Timing
Control

Data &

Clock

Recovery

TPOS

TNEG

TCLK

RCLK

RPOS

RNEG

Encoder

TTIP

TRING

RTIP

RRING

Decoder

Timing
Control

Data &

Clock

Recovery

TPOS

TNEG

TCLK

RCLK

RPOS

RNEG

Encoder

TTIP

TRING

RTIP

RRING

XRT83L30

áç

ONE-CHANNEL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR

REV. P1.3.0

PRELIMINARY

HOST MODE SERIAL INTERFACE OPERATION

XRT83L30 has a simple four wire Serial Interface that is compatible with many of the microcontrollers available
in the market. The Host mode operation is enabled by connecting pin 20 (HW/HOST) to a "Low". The Serial
Interface provides a total of 32 "Read/Write" 8-bit registers that consists of the following signals:

Chip Select (Active "Low")

SCLK

Serial Clock

SDI

Serial Data Input

SDO

Serial Data Output

USING THE MICROPROCESSOR SERIAL INTERFACE

The following instructions for using the Microprocessor Serial Interface are best understood by referring to the
diagram in Figure 25.

In order to use the Serial interface, a clock signal must be applied to the SCLK input pin. The maximum SCLK
clock frequency is 20MHz. A Read or Write operation can then be initiated by asserting the active-low Chip
Select (CS) input pin. For proper operation the CS must be asserted "Low" at least 50ns prior to the first rising
edge of the SCLK. Once the CS pin has been asserted, the Read/Write Operation and the target register can
be specified through the Serial Interface by writing eight serial bits into the SDI input. Each bit will be clocked
on the rising edge of SCLK.The function of the eight bits are identified and described below:

Bit 1:

R/W (Read/Write) Bit

This bit is clocked into the SDI input on the first rising edge of the SCLK after CS has been asserted. This bit
indicates whether the current operation is a "Read" or a "Write". A "1" in this bit specifies a Read operation,
whereas a "0" specifies a "Write" operation.

áç

XRT83L30

ONE-CHANNEL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR

PRELIMINARY

REV. P1.3.0

Bit 2 through 6:The five (5) Address Values (labeled A0, A1, A2, A3 and A4)

The next five rising edges of the SCLK signal, clock in the 5-bit address value for the Read or Write operation.
These five bits define the register address within XRT83L30 that the user has selected to read data from or
write data to. The address bits must be supplied to the SDI input in ascending order with LSB (Least Significant
Bit) first.

Bit 7:

(A5)

The next bit A5 must be set to "0" as shown in Figure 25.

Bit 8:

(A6)

The value of A6 is a "don't care".

Once the first eight bits have been written into the Serial interface, the subsequent action depends on the
whether the current operation is a "Read" or "Write" instruction.

Read Operation

With the last address bit "A4" written into the SDI input, the "Read" operation will proceed through an idle
period lasting two SCLK periods. On the rising edge of the 9th SCLK the serial data output (SDO) becomes
active (see Figure 25). At this point the user can begin reading the 8-bit data (D0 through D7) stored in the
interface register at address [A4,A3,A2,A1,A0], in ascending order (LSB first), on the falling edge of SCLK.

Write Operation

With the last address bit (A4) written into the SDI input, the "Write" operation will proceed through an idle
period lasting two SCLK periods. Prior to the rising edge of the 9th SCLK, the user must begin to apply the
eight bit data word to the SDI input. The Serial Interface will latch this data on the rising edge of SCLK. The
serial data (D0 through D7) should enter the SDI input in ascending order with the LSB first.

Serial Interface Register Description

The serial Interface consists of 32 8-bit register locations. The Microprocessor register address map and Bit
map are described in Table 16 and Table 17 respectively. The function of the individual bits are described in
Table 18 through Table 36.

IGURE

25. M

ICROPROCESSOR

ERIAL

NTERFACE

ATA

TRUCTURE

R/W

SCLK

SDI

S D O

High Z

XRT83L30

áç

ONE-CHANNEL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR

REV. P1.3.0

PRELIMINARY

ABLE

16: M

ICROPROCESSOR

EGISTER

DDRESS

EGISTER

UMBER

EGISTER

DDRESS

UNCTION

HEX

BINARY

0 - 18

0x00 - 0x12

00000 - 10010

Command and Control Registers

19 - 21

0x13 - 0x15

10011 - 10101

Reserved

22 - 29

0x16 - 0x1D

10110 - 11101

R/W registers reserved for testing purpose

0x1E

11110

Device "ID"

0x1F

11111

Device "Revision ID"

ABLE

17: M

ICROPROCESSOR

EGISTER

. #

DDRESS

YPE

Control Registers

00000

Hex 0x00

R/W

Reserved

EQC4

EQC3

EQC2

EQC1

EQC0

00001

Hex 0x01

R/W

RXTSEL

TXTSEL

TERSEL1

TERSEL0

JASEL1

JASEL0

JABW

FIFOS

00010

Hex 0x02

R/W

RXON

TXTEST2

TXTEST1

TXTEST0

TXON

LOOP2

LOOP1

LOOP0

00011

Hex 0x03

R/W

NLCDE1

NLCDE0

CODES

RXRES1

RXRES0

INSBPV

Reserved

TRATIO

00100

Hex 0x04

R/W

GIE

DMOIE

FLSIE

LCVIE

NLCDIE

AISDIE

RLOSIE

QRPDIE

00101

Hex 0x05

Reserved

DMO

FLS

LCV

NLCD

AISD

RLOS

QRPD

00110

Hex 0x06

RUR

Reserved

DMOIS

FLSIS

LCVIS

NLCDIS

AISDIS

RLOSIS

QRPDIS

00111

Hex 0x07

Reserved

CLOS5

CLOS4

CLOS3

CLOS2

CLOS1

CLOS0

01000

Hex 0x08

R/W

B6S1

B5S1

B4S1

B3S1

B2S1

B1S1

B0S1

01001

Hex 0x09

R/W

B6S2

B5S2

B4S2

B3S2

B2S2

B1S2

B0S2

01010

Hex 0x0A

R/W

B6S3

B5S3

B4S3

B3S3

B2S3

B1S3

B0S3

01011

Hex 0x0B

R/W

B6S4

B5S4

B4S4

B3S4

B2S4

B1S4

B0S4

01100

Hex 0x0C

R/W

B6S5

B5S5

B4S5

B3S5

B2S5

B1S5

B0S5

01101

Hex 0x0D

R/W

B6S6

B5S6

B4S6

B3S6

B2S6

B1S6

B0S6

01110

Hex 0x0E

R/W

B6S7

B5S7

B4S7

B3S7

B2S7

B1S7

B0S7

áç

XRT83L30

ONE-CHANNEL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR

PRELIMINARY

REV. P1.3.0

ABLE

19: M

ICROPROCESSOR

EGISTER

BIT

DESCRIPTION

EGISTER

DDRESS

00001

UNCTION

EGISTER

YPE

ESET

ALUE

AME

RXTSEL

Receiver Termination Select: In Host mode, this bit is used to
select between the internal and external line termination modes
for the receiver according to the following table:

R/W

TXTSEL

Transmit Termination Select: In Host mode, this bit is used to
select between the internal and external line termination modes
for the transmitter according to the following table:

R/W

TERSEL1

Termination Impedance Select bit 1:

In the Host mode and in the internal termination mode (TXT-
SEL="1" and RXTSEL="1"), TERSEL[1:0] control the transmit
and receive termination impedance according to the following
table:

In the internal termination mode, the receiver termination of each
receiver is realized completely by internal resistors or by the
combination of internal and one fixed resistor (see description for
RXRES[1:0] bits).

In the internal termination mode, the transmitter output should be
AC coupled to the transformer.

R/W

TERSEL0

Termination Impedance Select bit 0:

See description of bit D5 for the function of this bit.

R/W

RXTSEL

RX Termination

External

Internal

TXTSEL

TX Termination

External

Internal

100

110

120

Termination

TERSEL1

TERSEL0

áç

XRT83L30

ONE-CHANNEL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR

PRELIMINARY

REV. P1.3.0

ABLE

20: M

ICROPROCESSOR

EGISTER

BIT

DESCRIPTION

EGISTER

DDRESS

00010

UNCTION

EGISTER

YPE

ESET

ALUE

AME

RXON

Receiver ON: Writing a "1" into this bit location turns on the
Receive Section. Writing a "0" shuts off the Receiver Section. In
this mode, RTIP and RRING driver outputs will be tri-stated for
power reduction or redundancy applications. Default is "0", off.

R/W

TXTEST2

Transmit Test Pattern bit 2: This bit together with TXTEST1 and
TXTEST0 are used to generate and transmit test patterns
according to the following table:

TDQRSS (Transmit/Detect Quasi-Random Signal): This con-
dition, when activated, enables Quasi-Random Signal Source

generation and detection. In a T1 system QRSS pattern is a 2

1 pseudo-random bit sequence (PRBS) with no more than 14

consecutive zeros. In a E1 system, QRSS is a 2

-1 PRBS pat-

tern.

TAOS (Transmit All Ones): Activating this condition enables the
transmission of an All Ones Pattern. TCLK must not be tied
"Low".

TLUC (Transmit Network Loop-Up Code): Activating this con-
dition enables the Network Loop-Up Code of "00001" to be trans-
mitted to the line. When Network Loop-Up code is being
transmitted, the XRT83L30 will ignore the Automatic Loop-Code
detection and Remote Loop-Back activation (NLCDE1 ="1",
NLCDE0 ="1", if activated) in order to avoid activating Remote
Digital Loop-Back automatically when the remote terminal
responds to the Loop-Back request.

TLDC (Transmit Network LOOP-Down Code): Activating this
condition enables the network Loop-Down Code of "001" to be
transmitted to the line.

R/W

TXTEST1

Transmit Test pattern bit 1: See description of bit D6 for the
function of this bit.

R/W

Transmit Data

TAOS

TLUC

TLDC

Test Pattern

TXTEST1

TXTEST0

TXTEST2

TDQRSS

TDQRSS & INVQRSS

TDQRSS & INSBER

TDQRSS & INVQRSS & INSBER

áç

XRT83L30

ONE-CHANNEL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR

PRELIMINARY

REV. P1.3.0

ABLE

21: M

ICROPROCESSOR

EGISTER

BIT

DESCRIPTION

EGISTER

DDRESS

00011

UNCTION

EGISTER

YPE

ESET

ALUE

AME

NLCDE1

Network Loop Code Detection Enable bit 1:

This bit together with NLCDE0, Control the Loop-Code detection
according to the following table:

When NLCDE1="0" and NCLDE0="1", or NLCDE1="1" and
NLCDE0="0", the chip is manually programed to monitor the
receive data for the Loop-Up or Loop-Down code respectively.
When the presence of the "00001" or "001" pattern is detected for
more than 5 seconds, the status of the NLCD bit is set to "1" and
if the NLCD interrupt is enabled an interrupt is initiated. The Host
has the option to control the Loop-Back function manually.

Setting the NLCDE1="1" and NLCDE0="1" enables the Auto-
matic Loop-Code detection and Remote-Loop-Back activation
mode. As this mode is initiated, the state of the NLCD interface
bit is reset to "0" and the chip is programmed to monitor the
receive data for the Loop-Up Code. If the "00001" pattern is
detected for longer than 5 seconds, the NLCD bit is set to "1",
Remote Loop-Back is activated and the chip is automatically pro-
gramed to monitor the receive data for the Loop-Down code. The
NLCD bit stays set even after the chip stops receiving the Loop-
Up code. The remote Loop-Back condition is removed when the
chip receives the Loop-Down code for more than 5 seconds or if
the Automatic Loop-Code detection mode is terminated.

R/W

NLCDE0

Network Loop Code Detection Enable bit 0: See description
of bit D7 for the function of this bit.

R/W

CODES

ENCODING and DECODING SELECT:

Writing a "0" to this bit selects HDB3 or B8ZS encoding and
decoding. Writing a "1" selects an AMI coding scheme.This bit is
only active when single-rail mode is selected.

R/W

NLCDE1

NLCDE0

Function

Disable Loop-Code

Detection

Detect Loop-Up Code in

Receive Data

Automatic Loop-Code

Detection

Detect Loop-Down Code in

Receive Data

áç

XRT83L30

ONE-CHANNEL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR

PRELIMINARY

REV. P1.3.0

ABLE

22: M

ICROPROCESSOR

EGISTER

BIT

DESCRIPTION

EGISTER

DDRESS

00100

UNCTION

EGISTER

YPE

ESET

ALUE

AME

GIE

Global Interrupt Enable: Writing a "1" into this bit, globally
enables interrupt generation on the INT pin. Writing a "0" into this
bit, globally masks all interrupt requests.

R/W

DMOIE

DMO Interrupt Enable: Writing a "1" to this bit enables DMO
interrupt generation, writing a "0" masks it.

R/W

FLSIE

FIFO Limit Status Interrupt Enable: Writing a "1" to this bit
enables interrupt generation when the FIFO limit is within 3 bits,
writing a "0" to masks it.

R/W

LCVIE

Line Code Violation Interrupt Enable: Writing a "1" to this bit
enables Line Code Violation interrupt generation, writing a "0"
masks it.

R/W

NLCDIE

Network Loop-Code Detection Interrupt Enable: Writing a "1"
to this bit enables Network Loop-code detection interrupt genera-
tion, writing a "0" masks it.

R/W

AISDIE

AIS Detection Interrupt Enable: Writing a "1" to this bit enables
Alarm Indication Signal detection interrupt generation, writing a
"0" masks it.

R/W

RLOSIE

Receive Loss of Signal Interrupt Enable: Writing a "1" to this
bit enables Loss of Receive Signal interrupt generation, writing a
"0" masks it.

R/W

QRPDIE

QRSS Pattern Detection Interrupt Enable: Writing a "1" to this
bit enables QRSS pattern detection interrupt generation, writing
a "0" masks it.

R/W

áç

XRT83L30

ONE-CHANNEL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR

PRELIMINARY

REV. P1.3.0

NLCD

Network Loop-Code Detection:

This bit operates differently in the Manual or the Automatic Net-
work Loop-Code detection modes.

In the Manual Loop-Code detection mode (NLCDE1 ="0" and
NLCDE0 ="1", or NLCDE1 ="1" and NLCDE0 ="0") this bit gets
set to "1" as soon as the Loop-Up ("00001") or Loop-Down
("001") code is detected in the receive data for longer than 5 sec-
onds. The NLCD bit stays in the "1" state for as long as the chip
detects the presence of the Loop-Code in the receive data and it
is reset to "0" as soon as it stops receiving it. In this mode if the
NLCD interrupt is enabled the chip will initiate an interrupt on
every transition of the NLCD.

When the Automatic Loop-Code detection mode (NLCDE1 ="1"
and NLCDE0 ="1") is initiated, the state of the NLCD interface bit
is reset to "0" and the chip is programmed to monitor the receive
input data for the Loop-Up Code. This bit is set to a "1" to indicate
that the Network Loop Code is detected for more than 5 seconds.
Simultaneously the Remote Loop-Back condition is automatically
activated and the chip is programmed to monitor the receive data
for the Network Loop-Down Code. The NLCD bit stays in the "1"
state for as long as the Remote Loop-Back condition is in effect
even if the chip stops receiving the Loop-Up Code. Remote
Loop-Back is removed if the chip detects the "001" pattern for
longer than 5 seconds in the receive data. Detecting the "001"
pattern also results in resetting the NLCD interface bit and initiat-
ing an interrupt provided the NLCD interrupt enable bit it active.
When programmed in the Automatic detection mode, the NLCD
interface bit stays "High" for the entire time the Remote Loop-
Back is active and initiates an interrupt anytime the status of the
NLCD bit changes. In this mode the host can monitor the state of
the NLCD bit to determine if the Remote Loop-Back is activated.

AISD

Alarm Indication Signal Detect: This bit is set to a "1" to indi-
cate All Ones Signal is detected by the receiver. The value of this
bit is based on the current status of Alarm Indication Signal
detector. If the AISDIE bit is enabled, any transition on this bit will
generate an Interrupt.

RLOS

Receive Loss of Signal: This bit is set to a "1" to indicate that
the receive input signal is lost. The value of this bit is based on
the current status of the receive input signal. If the RLOSIE bit is
enabled, any transition on this bit will generate an Interrupt.

QRPD

Quasi-random Pattern Detection: This bit is set to a "1" to indi-
cate the receiver is currently in synchronization with QRSS pat-
tern. The value of this bit is based on the current status of Quasi-
random pattern detector of. If the QRPDIE bit is enabled, any
transition on this bit will generate an Interrupt.

ABLE

23: M

ICROPROCESSOR

EGISTER

BIT

DESCRIPTION

áç

XRT83L30

ONE-CHANNEL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR

PRELIMINARY

REV. P1.3.0

ABLE

25: M

ICROPROCESSOR

EGISTER

BIT

DESCRIPTION

EGISTER

DDRESS

00111

UNCTION

EGISTER

YPE

ESET

ALUE

AME

Reserved

CLOS5

Cable Loss bit 5: CLOS[5:0] are the six bits receiver for selec-
tive equalizer setting which is also a binary word that represents
the cable attenuation indication within ±1dB. CLOS5 is the most
significant bit (MSB) and CLOS0 is the least significant bit (LSB).

CLOS4

Cable Loss bit 4: See description of D5 for function of this bit.

CLOS3

Cable Loss bit 3: See description of D5 for function of this bit.

CLOS2

Cable Loss bit 2: See description of D5 for function of this bit.

CLOS1

Cable Loss bit 1: See description of D5 for function of this bit.

CLOS0

Cable Loss bit 0: See description of D5 for function of this bit.

ABLE

26: M

ICROPROCESSOR

EGISTER

BIT

DESCRIPTION

EGISTER

DDRESS

01000

UNCTION

EGISTER

YPE

ESET

ALUE

AME

Reserved

R/W

D6-D0

B6S1 - B0S1 Arbitrary Transmit Pulse Shape, Segment 1

The shape of the transmitted pulse can be made user program-
mable by selecting "Arbitrary Pulse" mode, see Table 5. The arbi-
trary pulse is divided into eight time segments whose combined
duration is equal to one period of MCLK.

This 7 bit number represents the amplitude of the arbitrary pulse
during the first time segment. B6S1 -B0S1 is in signed magni-
tude format with B6S1 as the sign bit and B0S1 as the least sig-
nificant bit (LSB).

R/W

XRT83L30

áç

ONE-CHANNEL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR

REV. P1.3.0

PRELIMINARY

ABLE

27: M

ICROPROCESSOR

EGISTER

BIT

DESCRIPTION

EGISTER

DDRESS

01001

UNCTION

EGISTER

YPE

ESET

ALUE

AME

Reserved

R/W

D6-D0

B6S2 - B0S2 Arbitrary Transmit Pulse Shape, Segment 2

This 7 bit number represents the amplitude of the arbitrary pulse
during the second time segment. B6S2 -B0S2 is in signed mag-
nitude format with B6S2 as the sign bit and B0S2 as the least
significant bit (LSB).

R/W

ABLE

28: M

ICROPROCESSOR

EGISTER

#10

BIT

DESCRIPTION

EGISTER

DDRESS

01010

UNCTION

EGISTER

YPE

ESET

ALUE

AME

Reserved

R/W

D6-D0

B6S3 - B0S3 Arbitrary Transmit Pulse Shape, Segment 3

This 7 bit number represents the amplitude of the arbitrary pulse
during the thrd time segment. B6S3 -B0S3 is in signed magni-
tude format with B6S3 as the sign bit and B0S3 as the least sig-
nificant bit (LSB).

R/W

áç

XRT83L30

ONE-CHANNEL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR

PRELIMINARY

REV. P1.3.0

ABLE

29: M

ICROPROCESSOR

EGISTER

#11

BIT

DESCRIPTION

EGISTER

DDRESS

01011

UNCTION

EGISTER

YPE

ESET

ALUE

AME

Reserved

R/W

D6-D0

B6S4 - B0S4 Arbitrary Transmit Pulse Shape, Segment 4

This 7 bit number represents the amplitude of the arbitrary pulse
during the fourth time segment. B6S4 -B0S4 is in signed magni-
tude format with B6S4 as the sign bit and B0S4 as the least sig-
nificant bit (LSB).

R/W

ABLE

30: M

ICROPROCESSOR

EGISTER

#12

BIT

DESCRIPTION

EGISTER

DDRESS

01100

UNCTION

EGISTER

YPE

ESET

ALUE

AME

Reserved

R/W

D6-D0

B6S5 - B0S5 Arbitrary Transmit Pulse Shape, Segment 5

This 7 bit number represents the amplitude of the arbitrary pulse
during the fith time segment. B6S5 -B0S5 is in signed magni-
tude format with B6S5 as the sign bit and B0S5 as the least sig-
nificant bit (LSB).

R/W

XRT83L30

áç

ONE-CHANNEL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR

REV. P1.3.0

PRELIMINARY

ABLE

31: M

ICROPROCESSOR

EGISTER

#13

BIT

DESCRIPTION

EGISTER

DDRESS

01101

UNCTION

EGISTER

YPE

ESET

ALUE

AME

Reserved

R/W

D6-D0

B6S6 - B0S6 Arbitrary Transmit Pulse Shape, Segment 6

This 7 bit number represents the amplitude of the arbitrary pulse
during the sixth time segment. B6S6 -B0S6 is in signed magni-
tude format with B6S6 as the sign bit and B0S6 as the least sig-
nificant bit (LSB).

R/W

ABLE

32: M

ICROPROCESSOR

EGISTER

#14

BIT

DESCRIPTION

EGISTER

DDRESS

01110

UNCTION

EGISTER

YPE

ESET

ALUE

AME

Reserved

R/W

D6-D0

B6S7 - B0S7 Arbitrary Transmit Pulse Shape, Segment 7

This 7 bit number represents the amplitude of the arbitrary pulse
during the seventh time segment. B6S7 -B0S7 is in signed mag-
nitude format with B6S7 as the sign bit and B0S7 as the least
significant bit (LSB).

R/W

áç

XRT83L30

ONE-CHANNEL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR

PRELIMINARY

REV. P1.3.0

ABLE

35: M

ICROPROCESSOR

EGISTER

#17

BIT

DESCRIPTION

EGISTER

DDRESS

10001

AME

UNCTION

EGISTER

YPE

ESET

ALUE

Reserved

R/W

CLKSEL2

Clock Select Inputs for Master Clock Synthesizer bit 2: In
Host mode, CLKSEL[2:0] are input signals to a programmable
frequency synthesizer that can be used to generate a master
clock from an external accurate clock source according to the fol-
lowing table:

In Hardware mode the state of these bits are ignored and the
master frequency PLL is controlled by the corresponding Hard-
ware pins.

R/W

CLKSEL1

Clock Select inputs for Master Clock Synthesizer bit 1: See
description of bit D6 for function of this bit.

R/W

CLKSEL0

Clock Select inputs for Master Clock Synthesizer bit 0: See
description of bit D6 for function of this bit.

R/W

2048

1544

M C L K E 1

k H z

128

256

128

2048

1544

M C L K T 1

k H z

1544

2048

1544

2048

C L K O U T

k H z

1544

2048

1544

2048

1544

2048

1544

2048

1544

2048

1544

2048

1544

C L K S E L 0

C L K S E L 1

C L K S E L 2

1544

2048

1544

M C L K R A T E

XRT83L30

áç

ONE-CHANNEL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR

REV. P1.3.0

PRELIMINARY

MCLKRATE

Master Clock Rate Select: The state of this bit programs the
Master Clock Synthesizer to generate the T1/J1 or E1 clock. The
Master Clock Synthesizer will generate the E1 clock when
MCLKRATE = "0", and the T1/J1 clock when MCLKRATE = "1".

R/W

RXMUTE

Receive Output Mute: Writing a "1" to this bit, mutes receive
outputs at RPOS/RDATA and RNEG/LCV pins to a "0" state.

OTE

: RCLK is not muted.

R/W

EXLOS

Extended LOS: Writing a "1" to this bit extends the number of
zeros at the receive input before RLOS is declared to 4096 bits.

Writing a "0" reverts to the normal mode (175+75 bits for T1 and
32 bits for E1).

R/W

ICT

In-Circuit-Testing: Writing a "1" to this bit configures all the out-
put pins of the chip in "High" impedance mode for In-Circuit-Test-
ing. Setting ICT bit to "1" is equivalent to connecting the
Hardware ICT pin to ground.

R/W

ABLE

36: M

ICROPROCESSOR

EGISTER

#18

BIT

DESCRIPTION

EGISTER

DDRESS

10010

AME

UNCTION

EGISTER

YPE

ESET

ALUE

GAUGE1

Wire Gauge Selector Bit 1

This bit along with bit D6 are used to select wire gauge size as
shown in the table below.

R/W

GAUGE0

Wire Gauge Selector Bit 0

See bit D7.

R/W

TXONCNTL

Transmit On Control.

In Host mode, setting this bit to "1" transfers the control of the
Transmit On/Off function to the TXON Hardware control pin.

OTE

: This provides a faster On/Off capability for redundancy

application.

R/W

TERCNTL

Termination Control:

In Host mode, setting this bit to "1" transfers the control of the
RXTSEL to the RXTSEL Hardware control pin.

OTE

: This provides a faster On/Off capability for redundancy

application.

R/W

ABLE

35: M

ICROPROCESSOR

EGISTER

#17

BIT

DESCRIPTION

GAUGE1

GAUGE0

Wire Size

22 and 24 Gauge

26 Gauge

24 Gauge

22 Gauge

XRT83L30

áç

ONE-CHANNEL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR

REV. P1.3.0

PRELIMINARY

ELECTRICAL CHARACTERISTICS

ABLE

37: A

BSOLUTE

AXIMUM

ATINGS

Storage Temperature...............-65°C to +150°C

Operating Temperature............. -40°C to +85°C

Supply Voltage............................-0.5V to +3.8V

Vin................................................-0.5 to +5.5V

ABLE

38: DC D

IGITAL

NPUT

AND

UTPUT

LECTRICAL

HARACTERISTICS

VDD=3.3V±5%, T

=25°C,

UNLESS

OTHERWISE

SPECIFIED

ARAMETER

YMBOL

NITS

Power Supply Voltage

VDD

3.13

3.3

3.46

Input High Voltage

2.0

5.0

Input Low Voltage

-0.5

0.8

Output High Voltage @ IOH = 2.0mA

2.4

Output Low Voltage @IOL = 2.0mA

0.4

Input Leakage Current (except Input pins
with Pull-up or Pull- down resistor).

±10

Input Capacitance

5.0

Output Load Capacitance

ABLE

39: XRT83L30 P

OWER

ONSUMPTION

VDD=3.3V±5%, T

=25°C,

UNLESS

OTHERWISE

SPECIFIED

ODE

UPPLY

OLTAGE

MPEDANCE

TERMINATION

ESISTOR

RANSFORMER

ATIO

NIT

EST

ONDITIONS

ECEIVER

RANSMITTER

3.3V

6.2

2:1

1:2.42

150

210

50% "1's"

100% "1's"

3.3V

9.1

2:1

1:2

150

180

50% "1's"

100% "1's"

3.3V

120

6.2

2:1

1:2.42

140

145

50% "1's"

100% "1's"

3.3V

120

9.1

2:1

1:2

130

135

50% "1's"

100% "1's"

3.3V

100

2:1

1:2.42

200

285

50% "1's"

100% "1's"

áç

XRT83L30

ONE-CHANNEL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR

PRELIMINARY

REV. P1.3.0

3.3V

100

2:1

1:2

230

310

50% "1's"

100% "1's"

----

3.3V

----

Transmitter off

ABLE

40: E1 R

ECEIVER

LECTRICAL

HARACTERISTICS

VDD=3.3V±5%, T

= -40°

85°C,

UNLESS

OTHERWISE

SPECIFIED

ARAMETER

NIT

EST

ONDITIONS

Receiver loss of signal:

Number of consecutive zeros before
RLOS is set

Input signal level at RLOS

RLOS De-asserted

12.5

% ones

Cable attenuation @1024KHz

ITU-G.775, ETSI 300 233

Receiver Sensitivity

(Short Haul with cable loss)

With nominal pulse amplitude of 3.0V
for 120

and 2.37V for 75

applica-

tion. With -18dB interference signal
added.

Receiver Sensitivity

(Long Haul with cable loss)

With nominal pulse amplitude of 3.0V
for 120

and 2.37V for 75

applica-

tion. With -18dB interference signal
added.

Input Impedance

Input Jitter Tolerance:

1 Hz

10kHz-100kHz

>64

0.4

UIpp

ITU G.823

Recovered Clock Jitter

Transfer Corner Frequency

Peaking Amplitude

0.5

kHz

ITU G.736

Jitter Attenuator Corner Frequency
(-3dB curve) (JABW=0)

(JABW=1)

1.5

ITU G.736

Return Loss:

51kHz - 102kHz

102kHz - 2048kHz

2048kHz - 3072kHz

ITU-G.703

ABLE

39: XRT83L30 P

OWER

ONSUMPTION

VDD=3.3V±5%, T

=25°C,

UNLESS

OTHERWISE

SPECIFIED

ODE

UPPLY

OLTAGE

MPEDANCE

TERMINATION

ESISTOR

RANSFORMER

ATIO

NIT

EST

ONDITIONS

ECEIVER

RANSMITTER

áç

XRT83L30

ONE-CHANNEL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR

PRELIMINARY

REV. P1.3.0

ABLE

43: E1 T

RANSMITTER

LECTRICAL

HARACTERISTICS

VDD=3.3V±5%, T

= -40°

85°C,

UNLESS

OTHERWISE

SPECIFIED

ARAMETER

NIT

EST

ONDITIONS

AMI Output Pulse Amplitude:

Application

120

Application

2.13

2.70

2.37

3.0

2.60

3.30

Transformer with 1:2 ratio and 9.1

resistor in series with each end of pri-
mary.

Output Pulse Width

224

244

264

Output Pulse Width Ratio

0.95

1.05

ITU-G.703

Output Pulse Amplitude Ratio

0.95

1.05

ITU-G.703

Jitter Added by the Transmitter Out-
put

0.025

0.05

UIpp

Broad Band with jitter free TCLK
applied to the input.

Output Return Loss:

51kHz -102kHz

102kHz-2048kHz

2048kHz-3072kHz

ETSI 300 166, CHPTT

ABLE

44: T1 T

RANSMITTER

LECTRICAL

HARACTERISTICS

VDD=3.3V±5%, T

= -40°

85°C,

UNLESS

OTHERWISE

SPECIFIED

ARAMETER

NIT

EST

ONDITIONS

AMI Output Pulse Amplitude:

2.4

3.0

3.60

Tansformer with 1:2.45 ratio and mea-
sured at DSX-1

Output Pulse Width

338

350

362

ANSI T1.102

Output Pulse Width Imbalance

ANSI T1.102

Output Pulse Amplitude Imbalance

+200

ANSI T1.102

Jitter Added by the Transmitter Out-
put

0.025

0.05

UIpp

Broad Band with jitter free TCLK
applied to the input.

Output Return Loss:

51kHz -102kHz

102kHz-2048kHz

2048kHz-3072kHz

áç

XRT83L30

SINGLE-CHANNEL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR

PRELIMINARY

REV. P1.3.0

ORDERING INFORMATION

REVISION HISTORY

Rev. A1.0.0 Advanced version.

Rev. P1.1.0 Preliminary release.

Rev. P1.2.0 Modified microprocessor tables, moved various functions. Added GHCI_n, SL_1, SL_0, EQG_1
EQG_0, GAUGE1 and GAUGE0 to Control Global Register 18. Separated Microprocessor description table by
register number. Moved absolute maximum and DC electrical characteristics before AC electrical characteris-
tics. Replaced TBD's in electrical ables. Reformated table of contents.

Rev. P1.2.1 Renamed FIFO pin to GAUGE, edited definition and edited defintion of JASEL[1:0] to reflect the
FIFO size is selected by the jitter attenuator select.

Rev. P1.2.2 Redefined bits D3, D2 and D0 of register 1, in combination these bits set the jitter attenuator path
and FIFO size.

Rev. P1.2.3 Added definitions to dual function pins in the pin description section.

Rev P1.2.4 Added JABW, JASEL1 and JASEL0 table in pin list and Jitter attenuator section. Corrected typos in
features, figures 7, 8, 9 and 11. Added Jitter attenuator tables in microprocessor register tables.

Rev. P1.2.5 Table 18, 23, 24, 25 change GCHIE to GIE, GHCI and GCHIS to Reserved. Corrected package
outline drawing.

Rev. P1.2.6 TERCNTL (pin 46) function removed. Bit 7 of Microprocessor Register #2 was INSBER, is now re-
served. Bit 1 of Microprocessor Register #3 was INVQRSS, is now reserved. New description for bits D6 - D0
in Tables 27 - 34 Microprocessor Registers.

Rev. P1.2.7 Expanded information on Receive Redundancy. 2 tables and 1 figure.

Rev. P1.2.8 Edited section on RLOS

Rev. P1.2.9 Removed TERCNTL from block diagram. Edit EQC[4:0] to be input only on block diagram. Cor-
rected RXMUTE, TCLK, JABW, MCKLE1, CLKSEL [2:0], RXTSEL, TERSEL[1:0], RXRES[1:0], ATAOS, NLCD
in the pin descriptions section. Replaced the Functional Description section. Edits to Table 18: Microproces-
sor Register Bit Map, Table 21: Microprocessor Register #2 Bit Description, Table 35: Microprocessor Register
#16 Bit Description

Rev. P1.3.0 Table 35: Microprocessor Register #17 Bit Description, edit E1 clock MCLKRATE= "0" and T1/J1
clock MCLKRATE="1" .

ART

ACKAGE

PERATING

TEMPERATURE

ANGE

XRT83L30IV

64 Pin TQFP

-40

C to +85

HERMAL

NFORMATION

Theta - J

= 38° C/W

Theta J

= 7° C/W

Document Outline

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: XRT83L30LIU

Document Outline

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: XRT83L30LIU