Электронный компонент: XRT86L30IB

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Exar

Corporation 48720 Kato Road, Fremont CA, 94538

�

(510) 668-7000

�

FAX (510) 668-7017

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www.exar.com

PRELIMINARY

XRT86L30

PRELIMINARY

SINGLE T1/E1/J1 FRAMER/LIU COMBO

MAY 2004

REV. P1.0.1

GENERAL DESCRIPTION

The XRT86L30 is a single channel 1.544 Mbit/s or
2.048 Mbit/s DS1/E1/J1 framer and LIU integrated

solution featuring R

3

technology (Relayless, Recon-

figurable, Redundancy). The physical interface is op-
timized with internal impedance, and with the patent-
ed pad structure, the XRT86L30 provides protection
from power failures and hot swapping.

The XRT86L30 contains an integrated DS1/E1/J1
framer and LIU which provide DS1/E1/J1 framing and
error accumulation in accordance with ANSI/ITU_T
specifications. The framer has a framing synchronizer
and transmit-receive slip buffers. The slip buffers can
be independently enabled or disabled as required
and can be configured to frame to the common DS1/
E1/J1 signal formats.

The Framer block contains a Transmit and Receive
T1/E1/J1 Framing function. There are 3 Transmit
HDLC controllers which encapsulate contents of the
Transmit HDLC buffers into LAPD Message frames.
There are 3 Receive HDLC controllers which extract
the payload content of Receive LAPD Message
frames from the incoming T1/E1/J1 data stream and

write the contents into the Receive HDLC buffers.
The framer also contains a Transmit and Overhead
Data Input port, which permits Data Link Terminal
Equipment direct access to the outbound T1/E1/J1
frames. Likewise, a Receive Overhead output data
port permits Data Link Terminal Equipment direct ac-
cess to the Data Link bits of the inbound T1/E1/J1
frames.

The XRT86L30 fully meets all of the latest T1/E1/J1
specifications: ANSI T1/E1.107-1988, ANSI T1/
E1.403-1995, ANSI T1/E1.231-1993, ANSI T1/
E1.408-1990, AT&T TR 62411 (12-90) TR54016, and
ITU G-703, G.704, G706 and G.733, AT&T Pub.
43801, and ETS 300 011, 300 233, JT G.703, JT
G.704, JT G706, I.431. Extensive test and diagnostic
functions include Loop-backs, Boundary scan, Pseu-
do Random bit sequence (PRBS) test pattern gener-
ation, Performance Monitor, Bit Error Rate (BER)
meter, forced error insertion, and LAPD unchannel-
ized data payload processing according to ITU-T
standard Q.921.

Applications and Features (next page)

F

IGURE

1. XRT86L30 1-

CHANNEL

DS1 (T1/E1/J1) F

RAMER

/LIU C

OMBO

Performance

Monitor

PRBS

Generator &

Analyser

HDLC/LAPD

Controllers

LIU &

Loopback

Control

DMA

Interface

Signaling &

Alarms

JTAG

WR
ALE_AS
RD
RDY_DTACK

�

P

Select

A[11:0]

D[7:0]

Microprocessor

Interface

4

3

Tx Serial

Clock

Rx Serial

Clock

8kHz sync

OSC

Back Plane

1.544-16.384 Mbit/s

Local PCM

Highway

ST

-B

US

2-Frame

Slip Buffer

Elastic Store

Tx Serial

Data In

Tx LIU

Interface

2-Frame

Slip Buffer

Elastic Store

Rx LIU

Interface

Rx Framer

Rx Serial
Data Out

RTIP

RRING

TTIP

TRING

External Data

Link Controller

Tx Overhead In

Rx Overhead Out

XRT86L30

Tx Framer

LLB

LB

System (Terminal) Side

Line Side

1:1 Turns Ratio

1:2 Turns Ratio

Memory

Intel/Motorola �P

Configuration, Control &

Status Monitor

RxLOS

TxON

INT

XRT86L30
SINGLE T1/E1/J1 FRAMER/LIU COMBO

REV. P1.0.1

PRELIMINARY

2

APPLICATIONS

� High-Density T1/E1/J1 interfaces for Multiplexers,

Switches, LAN Routers and Digital Modems

� SONET/SDH terminal or Add/Drop multiplexers

(ADMs)

� T1/E1/J1 add/drop multiplexers (MUX)

� Channel Service Units (CSUs): T1/E1/J1 and Frac-

tional T1/E1/J1

� Digital Access Cross-connect System (DACs)

� Digital Cross-connect Systems (DCS)

� Frame Relay Switches and Access Devices

(FRADS)

� ISDN Primary Rate Interfaces (PRA)

� PBXs and PCM channel bank

� T3 channelized access concentrators and M13

MUX

� Wireless base stations

� ATM equipment with integrated DS1 interfaces

� Multichannel DS1 Test Equipment

� T1/E1/J1 Performance Monitoring

� Voice over packet gateways

� Routers

FEATURES

� Full duplex DS1 Tx and Rx Framer/LIU

� Two 512-bit (two-frame) elastic store, PCM frame

slip buffers (FIFO) on TX and Rx provide up to
8.192 MHz asynchronous back plane connections
with jitter and wander attenuation

� Supports input PCM and signaling data at 1.544,

2.048, 4.096 and 8.192 Mbits. Also supports 4-
channel multiplexed 12.352/16.384 (HMVIP/H.100)
Mbit/s on the back plane bus (with stuffed don't
care bits for the other 3 channels)

� Programmable output clocks for Fractional T1/E1/

J1

� Supports Channel Associated Signaling (CAS)

� Supports Common Channel Signalling (CCS)

� Supports ISDN Primary Rate Interface (ISDN PRI)

signaling

� Extracts and inserts robbed bit signaling (RBS)

� 3 Integrated HDLC controllers for transmit and

receive, each controller having two 96-byte buffers
(buffer 0 / buffer 1)

� HDLC Controllers Support SS7

� Timeslot assignable HDLC

� V5.1 or V5.2 Interface

� Automatic Performance Report Generation (PMON

Status) can be inserted into the transmit LAPD
interface every 1 second or for a single transmis-
sion

� Alarm Indication Signal with Customer Installation

signature (AIS-CI)

� Remote Alarm Indication with Customer Installation

(RAI-CI)

� Gapped Clock interface mode for Transmit and

Receive.

� Intel/Motorola and Power PC interfaces for configu-

ration, control and status monitoring

� Parallel search algorithm for fast frame synchroni-

zation

� Wide choice of T1 framing structures: SF/D4, ESF,

SLC�96, T1DM and N-Frame (non-signaling)

� Direct access to D and E channels for fast trans-

mission of data link information

� PRBS, QRSS, and Network Loop Code generation

and detection

� Programmable Interrupt output pin

� Supports programmed I/O and DMA modes of

Read-Write access

� Each framer block encodes and decodes the T1/

E1/J1 Frame serial data

� Detects and forces Red (SAI), Yellow (RAI) and

Blue (AIS) Alarms

� Detects OOF, LOF, LOS errors and COFA condi-

tions

� Loopbacks: Local (LLB) and Line remote (LB)

� Facilitates Inverse Multiplexing for ATM

� Performance monitor with one second polling

� Boundary scan (IEEE 1149.1) JTAG test port

� Accepts external 8kHz Sync reference

� 3.3V CMOS operation with 5V tolerant inputs

� 128-pin TQFP package with

-40

�

C to +85

�

C

opera-

tion

XRT86L30

SINGLE T1/E1/J1 FRAMER/LIU COMBO

PRELIMINARY

REV. P1.0.1

3

ORDERING INFORMATION

P

ART

N

UMBER

P

ACKAGE

O

PERATING

T

EMPERATURE

R

ANGE

XRT86L30IB

128 TQFP

-40

�

C to +85

�

C

XRT86L30

PRELIMINARY

REV. P1.0.1

SINGLE T1/E1/J1 FRAMER/LIU COMBO

I

LIST OF PARAGRAPHS

1.0 PIN LIST .................................................................................................................................................10
2.0 PIN DESCRIPTIONS ..............................................................................................................................11
3.0 MICROPROCESSOR INTERFACE BLOCK ..........................................................................................24

3.0.1 THE MICROPROCESSOR INTERFACE BLOCK SIGNALS ....................................................................................... 24

3.1 INTEL MODE PROGRAMMED I/O ACCESS (ASYNCHRONOUS) .................................................................. 27
3.2 MOTOROLA MODE PROGRAMMED I/O ACCESS (SYNCHRONOUS) .......................................................... 29

3.2.1 DMA READ/WRITE OPERATIONS .............................................................................................................................. 31

3.3 MEMORY MAPPED I/O ADDRESSING ............................................................................................................ 33
3.4 DESCRIPTION OF THE CONTROL REGISTERS ............................................................................................ 34

3.4.1 REGISTER DESCRIPTIONS ......................................................................................................................................... 40

3.5 PROGRAMMING THE LINE INTERFACE UNIT (LIU SECTION) ................................................................... 124
3.6 THE INTERRUPT STRUCTURE WITHIN THE FRAMER ............................................................................... 143

3.6.1 CONFIGURING THE INTERRUPT SYSTEM, AT THE FRAMER LEVEL .................................................................. 146

4.0 GENERAL DESCRIPTION AND INTERFACE .....................................................................................149

4.1 PHYSICAL INTERFACE .................................................................................................................................. 149
4.2 R3 TECHNOLOGY (RELAYLESS / RECONFIGURABLE / REDUNDANCY) ................................................ 150

4.2.1 LINE CARD REDUNDANCY ....................................................................................................................................... 150
4.2.2 TYPICAL REDUNDANCY SCHEMES ........................................................................................................................ 150
4.2.3 1:1 AND 1+1 REDUNDANCY WITHOUT RELAYS .................................................................................................... 150
4.2.4 TRANSMIT INTERFACE WITH 1:1 AND 1+1 REDUNDANCY .................................................................................. 150
4.2.5 RECEIVE INTERFACE WITH 1:1 AND 1+1 REDUNDANCY ..................................................................................... 151

4.3 POWER FAILURE PROTECTION ................................................................................................................... 152
4.4 OVERVOLTAGE AND OVERCURRENT PROTECTION ................................................................................ 152
4.5 NON-INTRUSIVE MONITORING ..................................................................................................................... 152
4.6 T1/E1 SERIAL PCM INTERFACE ................................................................................................................... 153
4.7 T1/E1 FRACTIONAL INTERFACE .................................................................................................................. 154
4.8 T1/E1 TIME SLOT SUBSTITUTION AND CONTROL ..................................................................................... 155
4.9 ROBBED BIT SIGNALING/CAS SIGNALING ................................................................................................. 156
4.10 OVERHEAD INTERFACE .............................................................................................................................. 158
4.11 FRAMER BYPASS MODE ............................................................................................................................. 159
4.12 HIGH-SPEED NON-MULTIPLEXED INTERFACE ........................................................................................ 160
4.13 HIGH-SPEED MULTIPLEXED INTERFACE ................................................................................................. 161

5.0 LOOPBACK MODES OF OPERATION ............................................................................................... 162

5.1 LIU PHYSICAL INTERFACE LOOPBACK DIAGNOSTICS ............................................................................ 162

5.1.1 LOCAL ANALOG LOOPBACK .................................................................................................................................. 162
5.1.2 REMOTE LOOPBACK ................................................................................................................................................ 162
5.1.3 DIGITAL LOOPBACK ................................................................................................................................................. 163
5.1.4 DUAL LOOPBACK ..................................................................................................................................................... 163
5.1.5 FRAMER REMOTE LINE LOOPBACK ...................................................................................................................... 163
5.1.6 FRAMER PAYLOAD LOOPBACK ............................................................................................................................. 164
5.1.7 FRAMER LOCAL LOOPBACK ................................................................................................................................... 164

6.0 HDLC CONTROLLERS AND LAPD MESSAGES ...............................................................................165

6.1 PROGRAMMING SEQUENCE FOR SENDING LESS THAN 96-BYTE MESSAGES .................................... 165
6.2 PROGRAMMING SEQUENCE FOR SENDING LARGE MESSAGES ........................................................... 165
6.3 PROGRAMMING SEQUENCE FOR RECEIVING LAPD MESSAGES ........................................................... 165
6.4 SS7 (SIGNALING SYSTEM NUMBER 7) FOR ESF IN DS1 ONLY ................................................................ 166
6.5 DS1/E1 DATALINK TRANSMISSION USING THE HDLC CONTROLLERS ................................................. 167
6.6 TRANSMIT BOS (BIT ORIENTED SIGNALING) PROCESSOR ..................................................................... 167

6.6.1 DESCRIPTION OF BOS .............................................................................................................................................. 167
6.6.2 PRIORITY CODEWORD MESSAGE .......................................................................................................................... 167
6.6.3 COMMAND AND RESPONSE INFORMATION .......................................................................................................... 167

6.7 TRANSMIT MOS (MESSAGE ORIENTED SIGNALING) PROCESSOR ........................................................ 168

6.7.1 DISCUSSION OF MOS ............................................................................................................................................... 168
6.7.2 PERIODIC PERFORMANCE REPORT ...................................................................................................................... 168
6.7.3 TRANSMISSION-ERROR EVENT .............................................................................................................................. 169
6.7.4 PATH AND TEST SIGNAL IDENTIFICATION MESSAGE ......................................................................................... 169
6.7.5 FRAME STRUCTURE ................................................................................................................................................. 169
6.7.6 FLAG SEQUENCE ...................................................................................................................................................... 169
6.7.7 ADDRESS FIELD ........................................................................................................................................................ 170
6.7.8 ADDRESS FIELD EXTENSION BIT (EA) ................................................................................................................... 170

PRELIMINARY

XRT86L30

SINGLE T1/E1/J1 FRAMER/LIU COMBO

REV. P1.0.1

II

6.7.9 COMMAND OR RESPONSE BIT (C/R) ...................................................................................................................... 170
6.7.10 SERVICE ACCESS POINT IDENTIFIER (SAPI) ...................................................................................................... 170
6.7.11 TERMINAL ENDPOINT IDENTIFIER (TEI) ............................................................................................................... 170
6.7.12 CONTROL FIELD ...................................................................................................................................................... 170
6.7.13 FRAME CHECK SEQUENCE (FCS) FIELD ............................................................................................................. 170
6.7.14 TRANSPARENCY (ZERO STUFFING) ..................................................................................................................... 171

6.8 TRANSMIT SLC�96 DATA LINK CONTROLLER .......................................................................................... 172
6.9 D/E TIME SLOT TRANSMIT HDLC CONTROLLER BLOCK V5.1 OR V5.2 INTERFACE ............................ 173
6.10 AUTOMATIC PERFORMANCE REPORT (APR) .......................................................................................... 173

6.10.1 BIT VALUE INTERPRETATION ............................................................................................................................... 173

7.0 OVERHEAD INTERFACE BLOCK ...................................................................................................... 175

7.1 DS1 TRANSMIT OVERHEAD INPUT INTERFACE BLOCK .......................................................................... 175

7.1.1 DESCRIPTION OF THE DS1 TRANSMIT OVERHEAD INPUT INTERFACE BLOCK .............................................. 175
7.1.2 CONFIGURE THE DS1 TRANSMIT OVERHEAD INPUT INTERFACE MODULE AS SOURCE OF THE FACILITY DATA

LINK (FDL) BITS IN ESF FRAMING FORMAT MODE ............................................................................................... 175

7.1.3 CONFIGURE THE DS1 TRANSMIT OVERHEAD INPUT INTERFACE MODULE AS SOURCE OF THE SIGNALING

FRAMING (FS) BITS IN N OR SLC�96 FRAMING FORMAT MODE ........................................................................ 177

7.1.4 CONFIGURE THE DS1 TRANSMIT OVERHEAD INPUT INTERFACE MODULE AS SOURCE OF THE REMOTE SIG-

NALING (R) BITS IN T1DM FRAMING FORMAT MODE ........................................................................................... 178

7.2 DS1 RECEIVE OVERHEAD OUTPUT INTERFACE BLOCK ......................................................................... 178

7.2.1 DESCRIPTION OF THE DS1 RECEIVE OVERHEAD OUTPUT INTERFACE BLOCK ............................................. 179
7.2.2 CONFIGURE THE DS1 RECEIVE OVERHEAD OUTPUT INTERFACE MODULE AS DESTINATION OF THE FACILITY

DATA LINK (FDL) BITS IN ESF FRAMING FORMAT MODE .................................................................................... 179

7.2.3 CONFIGURE THE DS1 RECEIVE OVERHEAD OUTPUT INTERFACE MODULE AS DESTINATION OF THE SIGNALING

FRAMING (FS) BITS IN N OR SLC�96 FRAMING FORMAT MODE ........................................................................ 180

7.2.4 CONFIGURE THE DS1 RECEIVE OVERHEAD OUTPUT INTERFACE MODULE AS DESTINATION OF THE REMOTE

SIGNALING (R) BITS IN T1DM FRAMING FORMAT MODE ..................................................................................... 181

7.3 E1 OVERHEAD INTERFACE BLOCK ............................................................................................................ 182
7.4 E1 TRANSMIT OVERHEAD INPUT INTERFACE BLOCK ............................................................................. 182

7.4.1 DESCRIPTION OF THE E1 TRANSMIT OVERHEAD INPUT INTERFACE BLOCK ................................................. 182
7.4.2 CONFIGURE THE E1 TRANSMIT OVERHEAD INPUT INTERFACE MODULE AS SOURCE OF THE NATIONAL BIT SE-

QUENCE IN E1 FRAMING FORMAT MODE .............................................................................................................. 183

7.5 E1 RECEIVE OVERHEAD INTERFACE ......................................................................................................... 185

7.5.1 DESCRIPTION OF THE E1 RECEIVE OVERHEAD OUTPUT INTERFACE BLOCK ............................................... 185
7.5.2 CONFIGURE THE E1 RECEIVE OVERHEAD OUTPUT INTERFACE MODULE AS SOURCE OF THE NATIONAL BIT

SEQUENCE IN E1 FRAMING FORMAT MODE .......................................................................................................... 186

8.0 LIU TRANSMIT PATH ......................................................................................................................... 188

8.1 TRANSMIT DIAGNOSTIC FEATURES ........................................................................................................... 188

8.1.1 TAOS (TRANSMIT ALL ONES) .................................................................................................................................. 188
8.1.2 ATAOS (AUTOMATIC TRANSMIT ALL ONES) ......................................................................................................... 189
8.1.3 NETWORK LOOP UP CODE ...................................................................................................................................... 189
8.1.4 NETWORK LOOP DOWN CODE ............................................................................................................................... 189
8.1.5 QRSS GENERATION .................................................................................................................................................. 190

8.2 T1 LONG HAUL LINE BUILD OUT (LBO) ...................................................................................................... 190
8.3 T1 SHORT HAUL LINE BUILD OUT (LBO) .................................................................................................... 191

8.3.1 ARBITRARY PULSE GENERATOR ........................................................................................................................... 191
8.3.2 DMO (DIGITAL MONITOR OUTPUT) ......................................................................................................................... 192
8.3.3 TRANSMIT JITTER ATTENUATOR ........................................................................................................................... 192

8.4 LINE TERMINATION (TTIP/TRING) ................................................................................................................ 193

9.0 LIU RECEIVE PATH ............................................................................................................................ 194

9.1 LINE TERMINATION (RTIP/RRING) ............................................................................................................... 194

9.1.1 CASE 1: INTERNAL TERMINATION .......................................................................................................................... 194
9.1.2 CASE 2: INTERNAL TERMINATION WITH ONE EXTERNAL FIXED RESISTOR FOR ALL MODES .................... 194
9.1.3 EQUALIZER CONTROL ............................................................................................................................................. 195
9.1.4 CABLE LOSS INDICATOR ......................................................................................................................................... 195

9.2 RECEIVE SENSITIVITY ................................................................................................................................... 196

9.2.1 AIS (ALARM INDICATION SIGNAL) .......................................................................................................................... 196
9.2.2 NLCD (NETWORK LOOP CODE DETECTION) ......................................................................................................... 196
9.2.3 FLSD (FIFO LIMIT STATUS DETECTION) ................................................................................................................ 197
9.2.4 RECEIVE JITTER ATTENUATOR .............................................................................................................................. 197
9.2.5 RXMUTE (RECEIVER LOS WITH DATA MUTING) ................................................................................................... 197

10.0 THE E1 TRANSMIT/RECEIVE FRAMER .......................................................................................... 199

10.1 DESCRIPTION OF THE TRANSMIT/RECEIVE PAYLOAD DATA INPUT INTERFACE BLOCK ................ 199

10.1.1 BRIEF DISCUSSION OF THE TRANSMIT/RECEIVE PAYLOAD DATA INPUT INTERFACE BLOCK OPERATING AT

Document Outline

• GENERAL DESCRIPTION
  • Figure 1. XRT86L30 1-channel DS1 (T1/E1/J1) Framer/LIU Combo
  • Applications
  • Features
  • Ordering Information
• Part Number
• Package
• Operating Temperature Range
• List of Paragraphs
• List of Figures
• List of Tables
  • 1.0 Pin List
• Pin
• Pin Name
  • 2.0 Pin Descriptions
  • Transmit Serial Data Input
• Signal Name
• Pin #
• Type
• Description
  • Overhead Interface
• Signal Name
• Pin #
• Type
• Description
  • Receive Serial Data Output
• Signal Name
• Pin #
• Type
• Description
  • Receive LiNE Interface
• Signal Name
• Pin #
• Type
• Description
  • Transmit LiNE Interface
• Signal Name
• Pin #
• Type
• Description
  • Timing interface
• Signal Name
• Pin #
• Type
• Description
  • gpio ControL
• Signal Name
• Pin #
• Type
• Description
  • JTAG
• Signal Name
• Pin #
• Type
• Description
  • Microprocessor Interface
• Signal Name
• Pin #
• Type
• Description
  • Power supply Pins
• Signal Name
• Type
• Description
  • ground Pins
• Signal Name
• Type
• Description
  • No Connect Pins
• Signal Name
• Type
• Description
  • 3.0 Microprocessor Interface Block
    • Table 2: Selecting the Microprocessor Interface Mode
• PTYPE[2:0]
• Microprocessor Mode
  • Figure 2. Simplified Block Diagram of the Microprocessor Interface Block
  • 3.0.1 The Microprocessor Interface Block Signals
    • Table 3: XRT86L30 Microprocessor Interface Signals that exhibit constant roles in both Intel and ...
• Pin Name
• Type
• Description
  • Table 4: Intel mode: Microprocessor Interface Signals
• XRT86L30
• Pin Name
• Intel
• Equivalent Pin
• Type
• Description
  • Table 5: Motorola Mode: Microprocessor Interface Signals
• XRT86L30
• Pin Name
• Motorola
• Equivalent Pin
• Type
• Description
  • 3.1 Intel Mode Programmed I/O Access (Asynchronous)
    • Figure 3. Intel �P Interface Signals During Programmed I/O Read and Write Operations
    • Table 6: Intel Microprocessor Interface Timing Specifications
• Symbol
• Parameter
• Min
• Max
• Units
  • 3.2 Motorola Mode Programmed I/O Access (Synchronous)
    • Figure 4. Motorola �P Interface Signals During Programmed I/O Read and Write Operations
    • Table 7: Intel Microprocessor Interface Timing Specifications
• Symbol
• Parameter
• Min
• Max
• Units
  • Figure 5. Motorola 68K �P Interface Signals During Programmed I/O Read and Write Operations
  • Table 8: Motorola 68K Microprocessor Interface Timing Specifications
• Symbol
• Parameter
• Min
• Max
• Units
  • 3.2.1 DMA Read/Write Operations
    • Figure 6. DMA Mode for the XRT86L30 and a Microprocessor
  • 3.3 Memory Mapped I/O Addressing
    • Table 9: XRT86L30 Framer/LIU Register Map
• Address [11:0]
• Contents
  • 3.4 Description of the Control Registers
    • Table 10: Register Summary
• Reg #
• Function
• Symbol
• Hex
• Mode
  • 3.4.1 Register Descriptions
    • Table 11: Clock Select Register E1 Mode
• Register 0 - T1/E1 Mode Clock Select Register (CSR) Hex Address: 0x0100
• Bit
• Function
• Type
• Default
• Description-Operation
  • Table 12: Line Interface Control Register T1 Mode
• Register 1 - T1/E1 Mode Line Interface Control Register (LICR) Hex Address: 0x0101
• Bit
• Function
• Type
• Default
• Description-Operation
  • Table 13: General Purpose Input/Output 0 Control Register
• Register 2 General Purpose Input/Output 0 Control Register (GPIOCR) Hex Address: 0x0102
• Bit
• Function
• Type
• Default
• Description-Operation
  • Table 14: Framing Select Register-E1 Mode
• Register 7- E1 Mode Framing Select Register (FSR) Hex Address: 0x0107
• Bit
• Function
• Type
• Default
• Description-Operation
  • Table 15: Framing Select Register-T1 Mode
• Register 7- T1 Mode Framing Select Register (FSR) Hex Address: 0x0107
• Bit
• Function
• Type
• Default
• Description-Operation
  • Table 16: Alarm Generation Register - E1 Mode
• Register 8 -E1 Mode Alarm Generation Register (AGR) Hex Address: 0x0108
• Bit
• Function
• Type
• Default
• Description-Operation
  • Table 17: Alarm Generation Register -T1 Mode
• Register 8 - T1 Mode Alarm Generation Register (AGR) Hex Address: 0x0108
• Bit
• Function
• Type
• Default
• Description-Operation
  • Table 18: Synchronization MUX Register - E1 Mode
• Register 9 - E1 Mode Synchronization MUX Register (SMR) Hex Address: 0x0109
• Bit
• Function
• Type
• Default
• Description-Operation
  • Table 19: Synchronization MUX Register - T1 Mode
• Register 9 - T1 Mode Synchronization MUX Register (SMR) Hex Address: 0x0109
• Bit
• Function
• Type
• Default
• Description-Operation
  • Table 20: Transmit Signaling and Data Link Select Register - E1 Mode
• Register 10 - E1 Mode Transmit Signaling and Data Link Select Register (TSDLSR) Hex Address:0x010A
• Bit
• Function
• Type
• Default
• Description-Operation
  • Table 21: Transmit Signaling and Data Link Select Register - T1 Mode
• Register 10 - T1 Mode Transmit Signaling and Data Link Select Register (TSDLSR) Hex Address:0x010A
• Bit
• Function
• Type
• Default
• Description-Operation
  • Table 22: Framing Control Register E1 Mode
• Register 11 -- E1 Mode Framing Control Register (FCR) Hex Address: 0x010B
• Bit
• Function
• Type
• Default
• Description-Operation
  • Table 23: Framing Control Register T1 Mode
• Register 11 -- T1 Mode Framing Control Register (FCR) Hex Address: 0x010B
• Bit
• Function
• Type
• Default
• Description-Operation
  • Table 24: Receive Signaling & Data Link Select Register - E1 Mode
• Register 12 - E1 Mode Receive Signaling & Data Link Select Register (RS&DLSR) Hex Address: 0x010C
• Bit
• Function
• Type
• Default
• Description-Operation
  • Table 25: Receive Signaling & Data Link Select Register (RS&DLSR) T1 Mode
• Register 12 - T1 Mode Receive Signaling & Data Link Select Register (RS&DLSR) Hex Address: 0x010C
• Bit
• Function
• Type
• Default
• Description-Operation
  • Table 26: Signaling Change Register 0 - T1 Mode
• Register 13 - T1/E1 Mode Signaling Change Register 0 (SCR 0) Hex Address: 0x010D
• Bit
• Function
• Type
• Default
• Description-Operation
  • Table 27: Signaling Change Register 1
• Register 14 T1/E1 Mode Signaling Change Register 1 (SCR 1) Hex Address: 0x010E
• Bit
• Function
• Type
• Default
• Description-Operation
  • Table 28: Signaling Change Register 2
• Register 15 T1/E1 Mode Signaling Change Register 2 (SCR 2) Hex Address: 0x010F
• Bit
• Function
• Type
• Default
• Description-Operation
  • Table 29: Signaling Change Register 3
• Register 16 - E1 Mode Signaling Change Register 3 (SCR 3) Hex Address: 0x0110
• Bit
• Function
• Type
• Default
• Description-Operation
  • Table 30: Receive National Bits Register
• Register 17 Receive National Bits Register (RNBR) Hex Address: 0x0111
• Bit
• Function
• Type
• Default
• Description-Operation
  • Table 31: Receive Extra Bits Register
• Register 18 Receive Extra Bits Register (REBR) Hex Address: 0x0112
• Bit
• Function
• Type
• Default
• Description-Operation
  • Table 32: Data Link Control Register
• Register 19 Data Link Control Register 1 (DLCR1) Hex Address: 0x0113
• Bit
• Function
• Type
• Default
• Description-Operation
  • Table 33: Transmit Data Link Byte Count Register
• Register 20 Transmit Data Link Byte Count Register 1 (TDLBCR1) Hex Address: 0x0114
• Bit
• Function
• Type
• Default
• Description-Operation
  • Table 34: Receive Data Link Byte Count Register
• Register 21 Receive Data Link Byte Count Register 1 (RDLBCR1) Hex Address: 0x0115
• Bit
• Function
• Type
• Default
• Description-Operation
  • Table 35: Slip Buffer Control Register
• Register 22 Slip Buffer Control Register (SBCR) Hex Address: 0x0116
• Bit
• Function
• Type
• Default
• Description-Operation
  • Table 36: FIFO Latency Register
• Register 23 FIFO Latency Register (FFOLR) Hex Address: 0x0117
• Bit
• Function
• Type
• Default
• Description-Operation
  • Table 37: DMA 0 (Write) Configuration Register
• Register 24 DMA 0 Write Configuration Register (D 0 WCR) Hex Address: 0x0118
• Bit
• Function
• Type
• Default
• Description-Operation
  • Table 38: DMA 1 (Read) Configuration Register
• Register 25 DMA 1 (Read) Configuration Register (D1CR) Hex Address: 0x0119
• Bit
• Function
• Type
• Default
• Description-Operation
  • Table 39: Interrupt Control Register
• Register 26 Interrupt Control Register (ICR) Hex Address: 0x011A
• Bit
• Function
• Type
• Default
• Description-Operation
  • Table 40: LAPD Select Register
• Register 27 LAPD Select Register (LAPDSR) Hex Address: 0x011B
• Bit
• Function
• Type
• Default
• Description-Operation
  • Table 41: Customer Installation Alarm Generation Register
• Register 28 - T1 Customer Installation Alarm Generation Register (CIAGR) Hex Address: 0x011C
• Bit
• Function
• Type
• Default
• Description-Operation
  • Table 42: Performance Report Control Register
• Register 29 - T1 Performance Report Control (PRCR) Hex Address: 0x011D
• Bit
• Function
• Type
• Default
• Description-Operation
  • Table 43: Gapped Clock Control Register
• Register 30 - T1/E1 Gapped Clock Control Register (GCCR) Hex Address: 0x011E
• Bit
• Function
• Type
• Default
• Description-Operation
  • Table 44: Gapped Clock Control Register
• Register 31 - T1/E1 Multiplexed () Hex Address: 0x011F
• Bit
• Function
• Type
• Default
• Description-Operation
  • Table 45: Transmit Interface Control Register - E1 Mode
• Register 32 - E1 Mode Transmit Interface Control Register (TICR) Hex Address:0x0120
• Bit
• Function
• Type
• Default
• Description-Operation
  • Table 46: Transmit Interface Control Register - T1 Mode
• Register 32 - T1 Mode Transmit Interface Control Register (TICR) Hex Address:0x0120
• Bit
• Function
• Type
• Default
• Description-Operation
  • Table 47: Receive Interface Control Register (RICR) - E1 Mode
• Bit
• Function
• Type
• Default
• Description-Operation
  • Table 48: Receive Interface Control Register (RICR) - T1 Mode
• Bit
• Function
• Type
• Default
• Description-Operation
  • Table 49: DS1 Test Register
• Bit
• Function
• Type
• Default
• Description-Operation
  • Table 50: Loopback Code Control Register
• Bit
• Function
• Type
• Default
• Description-Operation
  • Table 51: Transmit Loopback Coder Register
• Bit
• Function
• Type
• Default
• Description-Operation
  • Table 52: Receive Loopback Activation Code Register
• Bit
• Function
• Type
• Default
• Description-Operation
  • Table 53: Receive Loopback Deactivation Code Register
• Bit
• Function
• Type
• Default
• Description-Operation
  • Table 54: Transmit Sa Select Register
• Bit
• Function
• Type
• Default
• Description-Operation
  • Table 55: Transmit Sa Auto Control Register 1
• Bit
• Function
• Type
• Default
• Description-Operation
  • Table 56: Conditions on Receive side When TSACR1 bits Are enabled
• Conditions
• Actions - sending pattern
• Comments
• A
• Sa5
• Sa6
  • Table 57: Transmit Sa Auto Control Register 2
• Bit
• Function
• Type
• Default
• Description-Operation
  • Table 58: Conditions on Receive side When TSACR1 bits enabled
• Conditions
• Actions - sending pattern for
• A
• Sa5
• Sa6
• E
  • Table 59: Transmit Sa4 Register
• Bit
• Function
• Type
• Default
• Description-Operation
  • Table 60: Transmit Sa5 Register
• Bit
• Function
• Type
• Default
• Description-Operation
  • Table 61: Transmit Sa6 Register
• Bit
• Function
• Type
• Default
• Description-Operation
  • Table 62: Transmit Sa7 Register
• Bit
• Function
• Type
• Default
• Description-Operation
  • Table 63: Transmit Sa8 Register
• Bit
• Function
• Type
• Default
• Description-Operation
  • Table 64: Receive Sa4 Register
• Bit
• Function
• Type
• Default
• Description-Operation
  • Table 65: Receive Sa5 Register
• Bit
• Function
• Type
• Default
• Description-Operation
  • Table 66: Receive Sa6 Register
• Register 49 Receive Sa6 Register (RSA6R) 0x013D
• Bit
• Function
• Type
• Default
• Description-Operation
  • Table 67: Receive Sa7 Register
• Register 50 Receive Sa7 Register (RSA7R) 0x013E
• Bit
• Function
• Type
• Default
• Description-Operation
  • Table 68: Receive Sa8 Register
• Register 51 Receive Sa8 Register (RSA8R) 0x013F
• Bit
• Function
• Type
• Default
• Description-Operation
  • Table 69: Data Link Control Register
• Register 52 Data Link Control Register 2 (DLCR2) Hex Address: 0x0143
• Bit
• Function
• Type
• Default
• Description-Operation
  • Table 70: Transmit Data Link Byte Count Register
• Register 53 Transmit Data Link Byte Count Register 2 (TDLBCR2) Hex Address: 0x0144
• Bit
• Function
• Type
• Default
• Description-Operation
  • Table 71: Receive Data Link Byte Count Register
• Register 54 Receive Data Link Byte Count Register 2 (RDLBCR2) Hex Address: 0x0145
• Bit
• Function
• Type
• Default
• Description-Operation
  • Table 72: Data Link Control Register
• Register 55 Data Link Control Register 3 (DLCR3) Hex Address: 0x0153
• Bit
• Function
• Type
• Default
• Description-Operation
  • Table 73: Transmit Data Link Byte Count Register
• Register 56 Transmit Data Link Byte Count Register 3 (TDLBCR3) Hex Address: 0x0154
• Bit
• Function
• Type
• Default
• Description-Operation
  • Table 74: Receive Data Link Byte Count Register
• Register 57 Receive Data Link Byte Count Register 3 (RDLBCR3) Hex Address: 0x0155
• Bit
• Function
• Type
• Default
• Description-Operation
  • Table 75: Device ID Register
• Bit
• Function
• Type
• Default
• Description-Operation
  • Table 76: Revision ID Register
• Register 59 Revision ID Register (REVID) 0x01FF
• Bit
• Function
• Type
• Default
• Description-Operation
  • Table 77: Transmit Channel Control Register 0 to 31 E1 Mode
• Register 60-91 E1 Transmit Channel Control Register 0-31 (TCCR 0-31) Hex Address: 0x0300 to 0x031F
• Bit
• Mode
• Function
• Type
• Default
• Description-Operation
  • Table 78: Transmit Channel Control Register 0 to 31 T1 Mode
• Register 60-91 T1 Transmit Channel Control Register 0-23 (TCCR 0-23) Hex Address: 0x0300 to 0x0317
• Bit
• Function
• Type
• Default
• Description-Operation
  • Table 79: Transmit User Code Register 0 to 31
• Register 92-123 T1/E1 Transmit User Code Register 0 (UCR 0-31) Hex Address: 0x0320 to 0x033F
• Bit
• Function
• Type
• Default
• Description-Operation
  • Table 80: Transmit Signaling Control Register x - E1 Mode
• Register 124-155 - E1 Transmit Signaling Control Register x (TSCR 0-31) Hex Address: 0x0340 to 0x...
• Bit
• Function
• Type
• Default
• Description-Operation
  • Table 81: Transmit Signaling Control Register x - T1 Mode
• Register 124-155 - T1 Transmit Signaling Control Register x (TSCR) (0-23) Hex Address: 0x0340 to ...
• Bit
• Function
• Type
• Default
• Description-Operation
  • Table 82: Receive Channel Control Register x (RCCR 0-31) - E1 Mode
• Register 156-187 E1 Receive Channel Control Register x (RCCR 0-31) Hex Address: 0x0360 to 0x037F
• Bit
• Function
• Type
• Default
• Description-Operation
  • Table 83: Receive Channel Control Register x (RCCR 0-23) - T1 Mode
• Register 156-187 - T1 Receive Channel Control Register x (RCCR 0-23) Hex Address: 0x0360 to 0x037F
• Bit
• Function
• Type
• Default
• Description-Operation
  • Table 84: Receive User Code Register x (RUCR 0-31)
• Register 188-219 T1/E1 Receive User Code Register x (RUCR 0-31) Hex Address: 0x0380 to 0x039F
• Bit
• Function
• Type
• Default
• Description-Operation
  • Table 85: Receive Signaling Control Register x (RSCR) (0-31)
• Register 220-251 T1/E1 Receive Signaling Control Register x (RSCR) (0-31) Hex Address: 0x03A0 to ...
• Bit
• Function
• Type
• Default
• Description-Operation
  • Table 86: Receive Substitution Signaling Register (RSSR) E1 Mode
• Register 252-283 E1 Mode Receive Substitution Signaling Register (RSSR 0-31) Hex Address 0x03C0 t...
• Bit
• Function
• Type
• Default
• Description-Operation
  • Table 87: Receive Substitution Signaling Register (RSSR) T1 Mode
• Register 252-283 - T1 Receive Substitution Signaling Register (RSSR 0-23) Hex Address: 0x03C0 to ...
• Bit
• Function
• Type
• Default
• Description-Operation
  • Table 88: Receive Signaling Array Register 0 to 31
• Register 284-315 Receive Signaling Array Register (RSAR 0-31) Hex Address: 0x0500 to 0x051F
• Bit
• Function
• Type
• Default
• Description-Operation
  • Table 89: LAPD Buffer 0 Control Register
• Register 316-411 LAPD Buffer 0 Control Register (LAPDBCR0) Hex Address: 0x0600 to 0x0660
• Bit
• Function
• Type
• Default
• Description-Operation
  • Table 90: LAPD Buffer 1 Control Register
• Register 412-507 LAPD Buffer 0 Control Register (LAPDBCR1) Hex Address: 0x0700 to 0x0760
• Bit
• Function
• Type
• Default
• Description-Operation
  • Table 91: PMON T1/E1 Receive Line Code (bipolar) Violation Counter
• Register 508 PMON Receive Line Code (bipolar) Violation Counter MSB (RLCVCU) Hex Address: 0x0900
• Bit
• Function
• Type
• Default
• Description-Operation
  • Table 92: PMON T1/E1 Receive Line Code (bipolar) Violation Counter
• Register 509 PMON Receive Line Code (bipolar) Violation Counter LSB (RLCVCL) Hex Address: 0x0901
• Bit
• Function
• Type
• Default
• Description-Operation
  • Table 93: PMON T1/E1 Receive Framing Alignment Bit Error Counter
• Register 510 PMON Receive Framing Alignment Error Counter MSB (RFAECU) Hex Address: 0x0902
• Bit
• Function
• Type
• Default
• Description-Operation
  • Table 94: PMON T1/E1 Receive Framing Alignment Bit Error Counter
• Register 511 PMON Receive Framing Alignment Error Counter LSB (RFAECL) Hex Address: 0x0903
• Bit
• Function
• Type
• Default
• Description-Operation
  • Table 95: PMON T1/E1 Receive Severely Errored Frame Counter
• Register 512 PMON Receive Severely Errored Frame Counter (RSEFC) Hex Address: 0x0904
• Bit
• Function
• Type
• Default
• Description-Operation
  • Table 96: PMON T1/E1 Receive CRC-4 Block Error Counter - MSB
• Register 513 PMON Receive Synchronization Bit Block Error Counter (RSBBECU) Hex Address: 0x0905
• Bit
• Function
• Type
• Default
• Description-Operation
  • Table 97: PMON T1/E1 Receive CRC-4 Block Error Counter - LSB
• Register 514 PMON Receive Synchronization Bit Block Error Counter (RSBBECL) Hex Address: 0x0906
• Bit
• Function
• Type
• Default
• Description-Operation
  • Table 98: PMON T1/E1 Receive Far-End BLock Error Counter - MSB
• Register 515 PMON Receive Far-End Block Error Counter (RFEBECU) Hex Address: 0x0907
• Bit
• Function
• Type
• Default
• Description-Operation
  • Table 99: PMON T1/E1 Receive Far End Block Error Counter
• Register 516 PMON Receive Far End Block Error Counter (RFEBECL) Hex Address: 0x0908
• Bit
• Function
• Type
• Default
• Description-Operation
  • Table 100: PMON T1/E1 Receive Slip Counter
• Register 517 PMON Receive Slip Counter (RSC) Hex Address: 0x0909
• Bit
• Function
• Type
• Default
• Description-Operation
  • Table 101: PMON T1/E1 Receive Loss of Frame Counter
• Register 518 PMON Receive Loss of Frame Counter (RLFC) Hex Address: 0x090A
• Bit
• Function
• Type
• Default
• Description-Operation
  • Table 102: PMON T1/E1 Receive Change of Frame Alignment Counter
• Register 519 PMON Receive Change of Frame Alignment Counter (RCFAC) Hex Address: 0x090B
• Bit
• Function
• Type
• Default
• Description-Operation
  • Table 103: PMON LAPD T1/E1 Frame Check Sequence Error Counter 1
• Register 520 PMON LAPD1 Frame Check Sequence Error Counter 1 (LFCSEC1) Hex Address: 0x090C
• Bit
• Function
• Type
• Default
• Description-Operation
  • Table 104: T1/E1 PRBS Bit Error Counter MSB
• Register 521 T1/E1 PRBS Bit Error Counter MSB (PBECU) Hex Address: 0x090D
• Bit
• Function
• Type
• Default
• Description-Operation
  • Table 105: T1/E1 PRBS Bit Error Counter LSB
• Register 522 T1/E1 PRBS Bit Error Counter LSB (PBECL) Hex Address: 0x090E
• Bit
• Function
• Type
• Default
• Description-Operation
  • Table 106: T1/E1 Transmit Slip Counter
• Register 523 T1/E1 Transmit Slip Counter (T1/E1TSC) Hex Address: 0x090F
• Bit
• Function
• Type
• Default
• Description-Operation
  • Table 107: T1/E1 Excessive Zero Violation Counter MSB
• Register 524 T1/E1 Excessive Zero Violation Counter MSB (EZVCU) Hex Address: 0x0910
• Bit
• Function
• Type
• Default
• Description-Operation
  • Table 108: T1/E1 Excessive Zero Violation Counter LSB
• Register 525 T1/E1 Excessive Zero Violation Counter MSB (EZVCL) Hex Address: 0x0911
• Bit
• Function
• Type
• Default
• Description-Operation
  • Table 109: T1/E1 Frame Check Sequence Error Counter 2
• Register 526 PMON LAPD2 Frame Check Sequence Error Counter 2 (LFCSEC2) Hex Address: 0x091C
• Bit
• Function
• Type
• Default
• Description-Operation
  • Table 110: T1/E1 Frame Check Sequence Error Counter 3
• Register 527 PMON LAPD3 Frame Check Sequence Error Counter 3 (LFCSEC3) Hex Address: 0x092C
• Bit
• Function
• Type
• Default
• Description-Operation
  • Table 111: Block Interrupt Status Register
• Register 528 Block Interrupt Status Register (BISR) Hex Address: 0x0B00
• Bit
• Function
• Type
• Default
• Description-Operation
  • Table 112: Block Interrupt Enable Register
• Register 529 Block Interrupt Enable Register (BIER) Hex Address: 0x0B01
• Bit
• Function
• Type
• Default
• Description-Operation
  • Table 113: Alarm & Error Interrupt Status Register
• Register 530 Alarm & Error Interrupt Status Register (AEISR) Hex Address: 0x0B02
• Bit
• Mode
• Function
• Type
• Default
• Description-Operation
  • Table 114: Alarm & Error Interrupt Enable Register - E1 Mode
• Register 531 E1 Mode Alarm & Error Interrupt Enable Register (AEIER) Hex Address: 0x0B03
• Bit
• Function
• Type
• Default
• Description-Operation
  • Table 115: Alarm & Error Interrupt Enable Register -T1 Mode
• Register 531 T1 Mode Alarm & Error Interrupt Enable Register (AEIER) Hex Address: 0x0B03
• Bit
• Function
• Type
• Default
• Description-Operation
  • Table 116: Framer Interrupt Status Register E1 Mode
• Register 532 E1 Mode Framer Interrupt Status Register (FISR) Hex Address: 0x0B04
• Bit
• Function
• Type
• Default
• Description-Operation
  • Table 117: Framer Interrupt Status Register T1 Mode
• Register 532 T1 Mode Framer Interrupt Status Register (FISR) Hex Address: 0x0B04
• Bit
• Function
• Type
• Default
• Description-Operation
  • Table 118: Framer Interrupt Enable Register E1 Mode
• Register 533 E1 Mode Framer Interrupt Enable Register (FIER) Hex Address: 0x0B05
• Bit
• Function
• Type
• Default
• Description-Operation
  • Table 119: Framer Interrupt Enable Register T1 Mode
• Register 533 T1 Mode Framer Interrupt Enable Register (FIER) Hex Address: 0x0B05
• Bit
• Function
• Type
• Default
• Description-Operation
  • Table 120: Data Link Status Register 1
• Register 534 Data Link Status Register 1 (DLSR1) Hex Address: 0x0B06
• Bit
• Function
• Type
• Default
• Description-Operation
  • Table 121: Data Link Interrupt Enable Register 1
• Register 535 Data Link Interrupt Enable Register 1 (DLIER1) Hex Address: 0x0B07
• Bit
• Function
• Type
• Default
• Description-Operation
  • Table 122: Slip Buffer Interrupt Status Register (SBISR)
• Register 536 Slip Buffer Interrupt Status Register (SBISR) Hex Address: 0x0B08
• Bit
• Function
• Type
• Default
• Description-Operation
  • Table 123: Slip Buffer Interrupt Enable Register (SBIER)
• Register 537 Slip Buffer Interrupt Enable Register (SBIER) Hex Address: 0x0B09
• Bit
• Function
• Type
• Default
• Description-Operation
  • Table 124: Receive Loopback Code Interrupt and Status Register (RLCISR)
• Register 538 Receive Loopback Code Interrupt and Status Register (RLCISR) Hex Address: 0x0B0A
• Bit
• Function
• Type
• Default
• Description-Operation
  • Table 125: Receive Loopback Code Interrupt Enable Register (RLCIER)
• Register 539 Receive Loopback Code Interrupt Enable Register (RLCIER) Hex Address: 0x0B0B
• Bit
• Function
• Type
• Default
• Description-Operation
  • Table 126: Receive SA Interrupt Register (RSAIR)
• Register 540 Receive SA Interrupt Register (RSAIR) Hex Address: 0x0B0C
• Bit
• Function
• Type
• Default
• Description-Operation
  • Table 127: Receive SA Interrupt Enable Register (RSAIER)
• Register 541 Receive SA Interrupt Enable Register (RSAIER) Hex Address: 0x0B0D
• Bit
• Function
• Type
• Default
• Description-Operation
  • Table 128: Excessive Zero Status Register
• Register 542 Excessive Zero Status Register (EXZSR) Hex Address: 0x0B0E
• Bit
• Function
• Type
• Default
• Description-Operation
  • Table 129: Excessive Zero Enable Register
• Register 543 Excessive Zero Enable Register (EXZER) Hex Address: 0x0B0F
• Bit
• Function
• Type
• Default
• Description-Operation
  • Table 130: SS7 Status Register for LAPD1
• Register 544 SS7 Status Register for LAPD1 (SS7SR1) Hex Address: 0x0B10
• Bit
• Function
• Type
• Default
• Description-Operation
  • Table 131: SS7 Enable Register for LAPD1
• Register 545 SS7 Enable Register for LAPD1 (SS7ER1) Hex Address: 0x0B11
• Bit
• Function
• Type
• Default
• Description-Operation
  • Table 132: Data Link Status Register 2
• Register 546 Data Link Status Register 2 (DLSR2) Hex Address: 0x0B16
• Bit
• Function
• Type
• Default
• Description-Operation
  • Table 133: Data Link Interrupt Enable Register 2
• Register 547 Data Link Interrupt Enable Register 2 (DLIER2) Hex Address: 0x0B17
• Bit
• Function
• Type
• Default
• Description-Operation
  • Table 134: SS7 Status Register for LAPD2
• Register 548 SS7 Status Register for LAPD2 (SS7SR2) Hex Address: 0x0B18
• Bit
• Function
• Type
• Default
• Description-Operation
  • Table 135: SS7 Enable Register for LAPD2
• Register 549 SS7 Enable Register for LAPD2 (SS7ER2) Hex Address: 0x0B19
• Bit
• Function
• Type
• Default
• Description-Operation
  • Table 136: Data Link Status Register 3
• Bit
• Function
• Type
• Default
• Description-Operation
  • Table 137: Data Link Interrupt Enable Register 3
• Register 551 Data Link Interrupt Enable Register 3 (DLIER3) Hex Address: 0x0B27
• Bit
• Function
• Type
• Default
• Description-Operation
  • Table 138: SS7 Status Register for LAPD3
• Register 552 SS7 Status Register for LAPD3 (SS7SR3) Hex Address: 0x0B28
• Bit
• Function
• Type
• Default
• Description-Operation
  • Table 139: SS7 Enable Register for LAPD3
• Register 553 SS7 Enable Register for LAPD3 (SS7ER3) Hex Address: 0x0B29
• Bit
• Function
• Type
• Default
• Description-Operation
  • Table 140: Customer Installation Alarm Status Register
• Register 554 Customer Installation Alarm Status Register (CIASR) Hex Address: 0x0B40
• Bit
• Function
• Type
• Default
• Description-Operation
  • Table 141: Customer Installation Alarm Status Register
• Register 555 Customer Installation Alarm Interrupt Enable Register (CIAIER) Hex Address: 0x0B41
• Bit
• Function
• Type
• Default
• Description-Operation
  • 3.5 Programming the Line Interface Unit (LIU Section)
    • Table 142: Microprocessor Register #556 Bit Description
• Register Address
• 0x0F00h
• Channel 0
• Function
• Register Type
• Reset Value
• Bit #
• Name
  • Table 143: Equalizer Control and Transmit Line Build Out
• EQC[4:0]
• T1/E1 Mode/Receive Sensitivity
• Transmit LBO
• Cable
  • Table 144: Microprocessor Register #557 Bit Description
• Register Address
• 0x0F01h
• Channel_0
• Function
• Register Type
• Reset Value
• Bit #
• Name
  • Table 145: Microprocessor Register #558 Bit Description
• Register Address
• 0x0F02h
• Channel_0
• Function
• Register Type
• Reset Value
• Bit #
• Name
  • Table 146: Microprocessor Register #559 Bit Description
• Register Address
• 0x0F03h
• Channel_0
• Function
• Register Type
• Reset Value
• Name
  • Table 147: Microprocessor Register #560 Bit Description
• Register Address
• 0x0F04h
• Channel_0
• Function
• Register Type
• Reset Value
• Name
  • Table 148: Microprocessor Register #561 Bit Description
• Register Address
• 0x0F05h
• Channel_0
• Function
• Register Type
• Reset Value
• Name
  • Table 149: Microprocessor Register #562 Bit Description
• Register Address
• 0x0F06h
• Channel_0
• Function
• Register Type
• Reset Value
• Name
  • Table 150: Microprocessor Register #563 Bit Description
• Register Address
• 0x0F07h
• Channel_0
• Function
• Register Type
• Reset Value
• Name
  • Table 151: Microprocessor Register #564 Bit Description
• Register Address
• 0x0F08h
• Channel_0
• Function
• Register Type
• Reset Value
• Name
  • Table 152: Microprocessor Register #565 Bit Description
• Register Address
• 0x0F09h
• Channel_0
• Function
• Register Type
• Reset Value
• Name
  • Table 153: Microprocessor Register #566 Bit Description
• Register Address
• 0x0F0Ah
• Channel_0
• Function
• Register Type
• Reset Value
• Name
  • Table 154: Microprocessor Register #567 Bit Description
• Register Address
• 0x0F0Bh
• Channel_0
• Function
• Register Type
• Reset Value
• Name
  • Table 155: Microprocessor Register #568 Bit Description
• Register Address
• 0x0F0Ch
• Channel_0
• Function
• Register Type
• Reset Value
• Name
  • Table 156: Microprocessor Register #569 Bit Description
• Register Address
• 0x0F0Dh
• Channel_0
• Function
• Register Type
• Reset Value
• Name
  • Table 157: Microprocessor Register #570 Bit Description
• Register Address
• 0x0F0Eh
• Channel_0
• Function
• Register Type
• Reset Value
• Name
  • Table 158: Microprocessor Register #571 Bit Description
• Register Address
• 0x0F0Fh
• Channel_0
• Function
• Register Type
• Reset Value
• Name
  • Table 159: Microprocessor Register #700 Bit Description - Global Register 0
• Register Address
• 0x0FE0h
• Name
• Function
• Register Type
• Reset Value
  • Table 160: Microprocessor Register #701, Bit Description - Global Register 1
• Register Address
• Name
• Function
• Register Type
• Reset Value
  • Table 161: Microprocessor Register #702, Bit Description - Global Register 2
• Register Address
• Name
• Function
• Register Type
• Reset Value
  • Table 162: Microprocessor Register #703, Bit Description - Global Register 3
• Register Address
• Name
• Function
• Register Type
• Reset Value
  • Table 163: Microprocessor Register #704, Bit Description - Global Register 4
• Register Address
• Name
• Function
• Register Type
• Reset Value
  • 3.6 The Interrupt Structure within the Framer
    • Table 164: List of the Possible Conditions that can Generate Interrupts, in each Framer
• Interrupt Block
• Interrupting Condition
  • Table 165: Address of the Block Interrupt Status Registers
• Framer Number
• Address of Block Interrupt Status Register
  • Table 166: Block Interrupt Status Register
• Register 321 Block Interrupt Status Register (BISR) Hex Address: 0x0B00
• Bit
• Function
• Type
• Default
• Description-Operation
  • Table 167: Block Interrupt Enable Register
• Register 322 Block Interrupt Enable Register (BIER) Hex Address: 0x0B01
• Bit
• Function
• Type
• Default
• Description-Operation
  • 3.6.1 Configuring the Interrupt System, at the Framer Level
    • 3.6.1.1 Enabling/Disabling the Framer for Interrupt Generation
    • Table 168: Interrupt Control Register
• Register 26 Interrupt Control Register (ICR) Hex Address: 0x011A
• Bit
• Mode
• Function
• Type
• Default
• Description-Operation
  • 3.6.1.2 Configuring the "Interrupt Status Bits", within a given Framer to be "Reset-upon-Read" or...
  • 3.6.1.3 Automatic Reset of Interrupt Enable Bits
  • 4.0 General description and interface
    • 4.1 Physical Interface
      • Figure 7. LIU Transmit Connection Diagram Using Internal Termination
      • Figure 8. LIU Receive Connection Diagram Using Internal Termination
    • 4.2 R3 Technology (Relayless / Reconfigurable / Redundancy)
      • 4.2.1 Line Card Redundancy
      • 4.2.2 Typical Redundancy Schemes
      • 4.2.3 1:1 and 1+1 Redundancy Without Relays
      • 4.2.4 Transmit Interface with 1:1 and 1+1 Redundancy
        • Figure 9. Simplified Block Diagram of the Transmit Interface for 1:1 and 1+1 Redundancy
      • 4.2.5 Receive Interface with 1:1 and 1+1 Redundancy
        • Figure 10. Simplified Block Diagram of the Receive Interface for 1:1 and 1+1 Redundancy
    • 4.3 Power Failure Protection
    • 4.4 Overvoltage and Overcurrent Protection
    • 4.5 Non-Intrusive Monitoring
      • Figure 11. Simplified Block Diagram of a Non-Intrusive Monitoring Application
    • 4.6 T1/E1 Serial PCM Interface
      • Figure 12. Transmit T1/E1 Serial PCM Interface
      • Figure 13. Receive T1/E1 Serial PCM Interface
    • 4.7 T1/E1 Fractional Interface
      • Figure 14. T1 Fractional Interface
    • 4.8 T1/E1 Time Slot Substitution and Control
      • Figure 15. T1/E1 Time Slot Substitution and Control
    • 4.9 Robbed Bit Signaling/CAS Signaling
      • Figure 16. Robbed Bit Signaling / CAS Signaling
      • Figure 17. ESF / CAS External Signaling Bus
      • Figure 18. SF / SLC-96 or 4-code Signaling in ESF / CAS External Signaling Bus
    • 4.10 Overhead Interface
      • Figure 19. T1/E1 Overhead Interface
      • Figure 20. T1 External Overhead Datalink Bus
      • Figure 21. E1 Overhead External Datalink Bus
    • 4.11 Framer Bypass Mode
      • Figure 22. Simplified Block Diagram of the Framer Bypass Mode
    • 4.12 High-Speed Non-Multiplexed Interface
      • Figure 23. T1 High-Speed Non-Multiplexed Interface
      • Figure 24. E1 High-Speed Non-Multiplexed Interface
    • 4.13 High-Speed Multiplexed Interface
      • Figure 25. Transmit High-Speed Bit Multiplexed Block Diagram
      • Figure 26. Receive High-Speed Bit Multiplexed Block Diagram
  • 5.0 Loopback modes of operation
    • 5.1 LIU Physical Interface Loopback Diagnostics
      • 5.1.1 Local Analog Loopback
        • Figure 27. Simplified Block Diagram of Local Analog Loopback
      • 5.1.2 Remote Loopback
        • Figure 28. Simplified Block Diagram of Remote Loopback
      • 5.1.3 Digital Loopback
        • Figure 29. Simplified Block Diagram of Digital Loopback
      • 5.1.4 Dual Loopback
        • Figure 30. Simplified Block Diagram of Dual Loopback
      • 5.1.5 Framer Remote Line Loopback
        • Figure 31. Simplified Block Diagram of the Framer Remote Line Loopback
      • 5.1.6 Framer Payload Loopback
        • Figure 32. Simplified Block Diagram of the Framer Local Loopback
      • 5.1.7 Framer Local Loopback
        • Figure 33. Simplified Block Diagram of the Framer Local Loopback
  • 6.0 HDLC Controllers and lapd Messages
    • Figure 34. HDLC Controllers
    • 6.1 Programming Sequence for Sending Less Than 96-Byte Messages
    • 6.2 Programming Sequence for Sending Large Messages
    • 6.3 Programming Sequence for Receiving LAPD Messages
    • 6.4 SS7 (Signaling System Number 7) for ESF in DS1 Only
    • 6.5 DS1/E1 Datalink Transmission Using the HDLC Controllers
    • 6.6 Transmit BOS (Bit Oriented Signaling) Processor
      • 6.6.1 Description of BOS
• BOS Message Format
  • 6.6.2 Priority Codeword Message
  • 6.6.3 Command and Response Information
  • 6.7 Transmit MOS (Message Oriented Signaling) Processor
    • 6.7.1 Discussion of MOS
      • Figure 35. LAPD Frame Structure
    • 6.7.2 Periodic Performance Report
    • 6.7.3 Transmission-Error Event
    • 6.7.4 Path and Test Signal Identification Message
    • 6.7.5 Frame Structure
    • 6.7.6 Flag Sequence
    • 6.7.7 Address Field
    • 6.7.8 Address Field Extension bit (EA)
    • 6.7.9 Command or Response bit (C/R)
    • 6.7.10 Service Access Point Identifier (SAPI)
    • 6.7.11 Terminal Endpoint Identifier (TEI)
    • 6.7.12 Control Field
    • 6.7.13 Frame Check Sequence (FCS) Field
    • 6.7.14 Transparency (Zero Stuffing)
  • 6.8 Transmit SLC�96 Data link Controller
  • Transmit SLC�96 Message Registers
• Byte
• 5
• 4
• 3
• 2
• 1
• 0
  • 6.9 D/E Time Slot Transmit HDLC Controller Block V5.1 or V5.2 Interface
  • 6.10 Automatic Performance Report (APR)
    • Table 169: Framing Format for PMON Status Inserted within LAPD by Initiating APR
    • 6.10.1 Bit Value Interpretation
  • 7.0 Overhead Interface Block
    • 7.1 DS1 Transmit Overhead Input Interface Block
      • 7.1.1 Description of the DS1 Transmit Overhead Input Interface Block
        • Figure 36. Block Diagram of the DS1 Transmit Overhead Input Interface of the XRT86L30
      • 7.1.2 Configure the DS1 Transmit Overhead Input Interface module as source of the Facility Data L...
  • Transmit Data Link Select Register (TDLSR) (Address = 0x010AH)
• Bit Number
• Bit Name
• Bit Type
• Bit Description
  • Transmit Data Link Select Register (TDLSR) (Address = 0x010AH)
• Bit Number
• Bit Name
• Bit Type
• Bit Description
  • Figure 37. DS1 Transmit Overhead Input Interface Timing in ESF Framing Format mode
  • 7.1.3 Configure the DS1 Transmit Overhead Input Interface module as source of the Signaling Frami...
  • Transmit Data Link Select Register (TDLSR) (Address = 0x010AH)
• Bit Number
• Bit Name
• Bit Type
• Bit Description
  • Figure 38. DS1 Transmit Overhead Input Timing in N or SLC�96 Framing Format Mode
  • 7.1.4 Configure the DS1 Transmit Overhead Input Interface module as source of the Remote Signalin...
  • Transmit Data link select register (tdlsr) (address = 0x010AH)
• Bit Number
• Bit Name
• Bit Type
• Bit Description
  • Figure 39. DS1 Transmit Overhead Input Interface module in T1DM Framing Format mode
  • 7.2 DS1 Receive Overhead Output Interface Block
    • 7.2.1 Description of the DS1 Receive Overhead Output Interface Block
      • Figure 40. Block Diagram of the DS1 Receive Overhead Output Interface of XRT86L30
    • 7.2.2 Configure the DS1 Receive Overhead Output Interface module as destination of the Facility D...
  • Receive Data Link Select Register (TDLSR) (Address = 0x010AH)
• Bit Number
• Bit Name
• Bit Type
• Bit Description
  • Receive Data Link Select Register (TDLSR) (Address = 0x010AH)
• Bit Number
• Bit Name
• Bit Type
• Bit Description
  • Figure 41. DS1 Receive Overhead Output Interface module in ESF framing format mode
  • 7.2.3 Configure the DS1 Receive Overhead Output Interface module as destination of the Signaling ...
  • Receive Data Link Select Register (TDLSR) (Address = 0x010AH)
• Bit Number
• Bit Name
• Bit Type
• Bit Description
  • Figure 42. DS1 Receive Overhead Output Interface Timing in N or SLC�96 Framing Format mode
  • 7.2.4 Configure the DS1 Receive Overhead Output Interface module as destination of the Remote Sig...
  • Receive Data Link Select Register (RDLSR) (Address = 0x010AH)
• Bit Number
• Bit Name
• Bit Type
• Bit Description
  • Figure 43. DS1 Receive Overhead Output Interface Timing in T1DM Framing Format mode
  • 7.3 E1 Overhead Interface Block
  • 7.4 E1 Transmit Overhead Input Interface Block
    • 7.4.1 Description of the E1 Transmit Overhead Input Interface Block
      • Figure 44. Block Diagram of the E1 Transmit Overhead Input Interface of XRT86L30
    • 7.4.2 Configure the E1 Transmit Overhead Input Interface module as source of the National Bit Seq...
  • Synchronization MUX Register (SMR) (Address = 0x0109H)
• Bit Number
• Bit Name
• Bit Type
• Bit Description
  • Transmit Signaling and Data Link Select Register (TSDLSR) (Address = 0x010AH)
• Bit Number
• Bit Name
• Bit Type
• Bit Description
  • Figure 45. E1 Transmit Overhead Input Interface Timing
  • 7.5 E1 Receive Overhead Interface
    • 7.5.1 Description of the E1 Receive Overhead Output Interface Block
      • Figure 46. Block Diagram of the E1 Receive Overhead Output Interface of XRT86L30
    • 7.5.2 Configure the E1 Receive Overhead Output Interface module as source of the National Bit Seq...
  • Receive Signaling and Data Link Select Register (RSDLSR) (Address = 0x010CH)
• Bit Number
• Bit Name
• Bit Type
• Bit Description
  • Figure 47. E1 Receive Overhead Output Interface Timing
  • 8.0 LIU transmit path
    • 8.1 Transmit Diagnostic Features
      • 8.1.1 TAOS (Transmit All Ones)
        • Figure 48. TAOS (Transmit All Ones)
      • 8.1.2 ATAOS (Automatic Transmit All Ones)
        • Figure 49. Simplified Block Diagram of the ATAOS Function
      • 8.1.3 Network Loop Up Code
        • Figure 50. Network Loop Up Code Generation
      • 8.1.4 Network Loop Down Code
        • Figure 51. Network Loop Down Code Generation
      • 8.1.5 QRSS Generation
        • Table 170: Random Bit Sequence Polynomials
• Random Pattern
• T1
• E1
  • 8.2 T1 Long Haul Line Build Out (LBO)
    • Figure 52. Long Haul Line Build Out with -7.5dB Attenuation
    • Figure 53. Long Haul Line Build Out with -15dB Attenuation
    • Figure 54. Long Haul Line Build Out with -22.5dB Attenuation
  • 8.3 T1 Short Haul Line Build Out (LBO)
    • Table 171: Short Haul Line Build Out
• LBO setting EQC[4:0]
• Range of Cable Attenuation
  • 8.3.1 Arbitrary Pulse Generator
    • Figure 55. Arbitrary Pulse Segment Assignment
  • 8.3.2 DMO (Digital Monitor Output)
  • 8.3.3 Transmit Jitter Attenuator
  • 8.4 Line Termination (TTIP/TRING)
    • Figure 56. Typical Connection Diagram Using Internal Termination
  • 9.0 liu Receive path
    • 9.1 Line Termination (RTIP/RRING)
      • 9.1.1 CASE 1: Internal Termination
        • Table 172: Selecting the Internal Impedance
• TERSEL[1:0]
• Receive Termination
  • Figure 57. Typical Connection Diagram Using Internal Termination
  • 9.1.2 CASE 2: Internal Termination With One External Fixed Resistor for All Modes
    • Table 173: Selecting the Value of the External Fixed Resistor
• RxRES[1:0]
• External Fixed Resistor
  • Figure 58. Typical Connection Diagram Using One External Fixed Resistor
  • 9.1.3 Equalizer Control
    • Figure 59. Simplified Block Diagram of the Equalizer and Peak Detector
  • 9.1.4 Cable Loss Indicator
    • Figure 60. Simplified Block Diagram of the Cable Loss Indicator
  • 9.2 Receive Sensitivity
    • Figure 61. Test Configuration for Measuring Receive Sensitivity
    • 9.2.1 AIS (Alarm Indication Signal)
    • 9.2.2 NLCD (Network Loop Code Detection)
      • Figure 62. Process Block for Automatic Loop Code Detection
    • 9.2.3 FLSD (FIFO Limit Status Detection)
    • 9.2.4 Receive Jitter Attenuator
    • 9.2.5 RxMUTE (Receiver LOS with Data Muting)
      • Figure 63. Simplified Block Diagram of the RxMUTE Function
  • 10.0 The E1 Transmit/receive framer
    • 10.1 Description of the Transmit/Receive Payload Data Input Interface Block
      • 10.1.1 Brief Discussion of the Transmit/Receive Payload Data Input Interface Block Operating at X...
        • Figure 64. Interfacing the Transmit Path to local terminal equipment
        • Figure 65. Interfacing the Receive Path to local terminal equipment
        • Figure 66. Waveforms for connecting the Transmit Payload Data Input Interface Block to local Term...
        • Figure 67. Waveforms for connecting the Receive Payload Data Input Interface Block to local Termi...
    • 10.2 Transmit/Receive High-Speed Back-Plane Interface
      • 10.2.1 Non-Multiplexed High-Speed Mode
        • Figure 68. Transmit Non-Multiplexed High-Speed Connection to local terminal equipment using MVIP ...
        • Figure 69. Receive Non-Multiplexed High-Speed Connection to local terminal equipment using MVIP 2...
        • Figure 70. Waveforms for Connecting the Transmit Non-Multiplexed High-Speed Input Interface at MV...
        • Figure 71. Waveforms for Connecting the Receive Non-Multiplexed High-Speed Input Interface at MVI...
      • 10.2.2 Multiplexed High-Speed Mode
  • First Octet of 16.384Mbit/s Data Stream
• Bit 0
• Bit 1
• Bit 2
• Bit 3
• Bit 4
• Bit 5
• Bit 6
• Bit 7
  • Second Octet of 16.384Mbit/s Data Stream
• Bit 0
• Bit 1
• Bit 2
• Bit 3
• Bit 4
• Bit 5
• Bit 6
• Bit 7
  • Fifth Octet of 16.384Mbit/s Data Stream
• Bit 0
• Bit 1
• Bit 2
• Bit 3
• Bit 4
• Bit 5
• Bit 6
• Bit 7
  • Sixth Octet of 16.384Mbit/s Data Stream
• Bit 0
• Bit 1
• Bit 2
• Bit 3
• Bit 4
• Bit 5
• Bit 6
• Bit 7
  • Seventh Octet of 16.384Mbit/s Data Stream
• Bit 0
• Bit 1
• Bit 2
• Bit 3
• Bit 4
• Bit 5
• Bit 6
• Bit 7
  • Eighth Octet of 16.384Mbit/s Data Stream
• Bit 0
• Bit 1
• Bit 2
• Bit 3
• Bit 4
• Bit 5
• Bit 6
• Bit 7
  • Figure 72. Interfacing XRT86L30 Transmit to local terminal equipment using 16.384Mbit/s, HMVIP 16...
  • Figure 73. Interfacing XRT86L30 Receive to local terminal equipment using 16.384Mbit/s, HMVIP 16....
  • Figure 74. Waveforms for Connecting the Transmit Multiplexed High-Speed Input Interface at HMVIP ...
  • Figure 75. Waveforms for Connecting the Receive Multiplexed High-Speed Input Interface at HMVIP 1...
  • Figure 76. Waveforms for Connecting the Receive Multiplexed High-Speed Input Interface at H.100 1...
  • 10.3 Brief Discussion of Common Channel Signaling in E1 Framing Format
  • 10.4 Brief Discussion of Channel Associated Signaling in E1 Framing Format
  • 10.5 Insert/Extract Signaling Bits from TSCR Register
  • 10.6 Insert/Extract Signaling Bits from TxCHN[0]_n/TxSIG Pin
    • Figure 77. Timing Diagram of the TxSIG Input
    • Figure 78. Timing Diagram of the RxSIG Output
  • 10.7 Enable Channel Associated Signaling and Signaling Data Source Control
  • 11.0 The DS1 Transmit/receive framer
    • 11.1 Description of the Transmit/Receive Payload Data Input Interface Block
      • 11.1.1 Brief Discussion of the Transmit/Receive Payload Data Input Interface Block Operating at 1...
        • Figure 79. Interfacing the Transmit Path to local terminal equipment
        • Figure 80. Interfacing the Receive Path to local terminal equipment
        • Figure 81. Waveforms for connecting the Transmit Payload Data Input Interface Block to local Term...
        • Figure 82. Waveforms for connecting the Receive Payload Data Input Interface Block to local Termi...
    • 11.2 Transmit/Receive High-Speed Back-Plane Interface
      • 11.2.1 T1 Transmit/Receive Interface - MVIP 2.048 MHz
        • Table 174: The mapping of T1 frame into E1 framing format
      • 11.2.2 Non-Multiplexed High-Speed Mode
        • Figure 83. Transmit Non-Multiplexed High-Speed Connection to local terminal equipment using MVIP ...
        • Figure 84. Receive Non-Multiplexed High-Speed Connection to local terminal equipment using MVIP 2...
        • Figure 85. Waveforms for Connecting the Transmit Non-Multiplexed High-Speed Input Interface at MV...
        • Figure 86. Waveforms for Connecting the Receive Non-Multiplexed High-Speed Input Interface at MVI...
      • 11.2.3 Multiplexed High-Speed Mode
  • First Octet of 12.352Mbit/s Data Stream
• Bit 0
• Bit 1
• Bit 2
• Bit 3
• Bit 4
• Bit 5
• Bit 6
• Bit 7
  • Second Octet of 12.352Mbit/s Data Stream
• Bit 0
• Bit 1
• Bit 2
• Bit 3
• Bit 4
• Bit 5
• Bit 6
• Bit 7
  • Third Octet of 12.352Mbit/s Data Stream
• Bit 0
• Bit 1
• Bit 2
• Bit 3
• Bit 4
• Bit 5
• Bit 6
• Bit 7
  • Sixth Octet of 12.352Mbit/s Data Stream
• Bit 0
• Bit 1
• Bit 2
• Bit 3
• Bit 4
• Bit 5
• Bit 6
• Bit 7
  • Seventh Octet of 12.352Mbit/s Data Stream
• Bit 0
• Bit 1
• Bit 2
• Bit 3
• Bit 4
• Bit 5
• Bit 6
• Bit 7
  • Eighth Octet of 12.352Mbit/s Data Stream
• Bit 0
• Bit 1
• Bit 2
• Bit 3
• Bit 4
• Bit 5
• Bit 6
• Bit 7
  • Ninth Octet of 12.352Mbit/s Data Stream
• Bit 0
• Bit 1
• Bit 2
• Bit 3
• Bit 4
• Bit 5
• Bit 6
• Bit 7
  • Figure 87. Interfacing XRT86L30 Transmit to local terminal equipment using 16.384Mbit/s, HMVIP 16...
  • Figure 88. Interfacing XRT86L30 Receive to local terminal equipment using 16.384Mbit/s, HMVIP 16....
  • Figure 89. Waveforms for Connecting the Transmit Multiplexed High-Speed Input Interface at 12.352...
  • Figure 90. Waveforms for Connecting the Transmit Multiplexed High-Speed Input Interface at 16.384...
  • Figure 91. Waveforms for Connecting the Transmit Multiplexed High-Speed Input Interface at HMVIP ...
  • Figure 92. Waveforms for Connecting the Receive Multiplexed High-Speed Input Interface at 12.352M...
  • Figure 93. Waveforms for Connecting the Receive Multiplexed High-Speed Input Interface at 16.384M...
  • Figure 94. Waveforms for Connecting the Receive Multiplexed High-Speed Input Interface at HMVIP 1...
  • Figure 95. Waveforms for Connecting the Receive Multiplexed High-Speed Input Interface at H.100 1...
  • 11.3 Brief Discussion of Robbed-bit Signaling in DS1 Framing Format
• Frame Number
• Signaling Bit
• Frame Number
• Signaling Bit
  • 11.3.1 Configure the framer to transmit Robbed-bit Signaling
  • 11.3.2 Insert Signaling Bits from TSCR Register
  • Transmit Signaling Control Register (TSCR) (Address = 0x0340H - 0x0357H)
• Bit Number
• Bit Name
• Bit Type
• Bit Description
  • 11.3.3 Insert Signaling Bits from TxSig_n Pin
    • Figure 96. Timing Diagram of the TxSig_n Input
  • Transmit Interface Control Register (TICR) (Address = 0x0120H)
• Bit Number
• Bit Name
• Bit Type
• Bit Description
  • 12.0 Alarms and Error Conditions
    • 12.1 AIS Alarm
  • Alarm Generation Register (AGR) (Address = 0x0108H)
• Bit Number
• Bit Name
• Bit Type
• Bit Description
  • Alarm and Error Interrupt Enable Register (AEIER) (Address = 0x0B03H)
• Bit Number
• Bit Name
• Bit Type
• Bit Description
  • Block Interrupt Enable Register (BIER) (Address = 0x0B01H)
• Bit Number
• Bit Name
• Bit Type
• Bit Description
  • Alarm and Error Status Register (AESR) (Address = 0x0B02H)
• Bit Number
• Bit Name
• Bit Type
• Bit Description
  • Alarm and Error Status Register (AESR) (Address = 0x0B02H)
• Bit Number
• Bit Name
• Bit Type
• Bit Description
  • 12.2 Red Alarm
  • Alarm and Error Interrupt Enable Register (AEIER) (Address = 0x0B03H)
• Bit Number
• Bit Name
• Bit Type
• Bit Description
  • Block Interrupt Enable Register (BIER) (Address = 0x0B01H)
• Bit Number
• Bit Name
• Bit Type
• Bit Description
  • Alarm and Error Status Register (AESR) (Address = 0x0B02H)
• Bit Number
• Bit Name
• Bit Type
• Bit Description
  • Alarm and Error Status Register (AESR) (Address = 0x0B02H)
• Bit Number
• Bit Name
• Bit Type
• Bit Description
  • 12.3 Yellow Alarm
  • Alarm and Error Interrupt Enable Register (AEIER) (Address = 0x0B03H)
• Bit Number
• Bit Name
• Bit Type
• Bit Description
  • Block Interrupt Enable Register (BIER) (Address = 0x0B01H)
• Bit Number
• Bit Name
• Bit Type
• Bit Description
  • Alarm and Error Status Register (AESR) (Address = 0x0B02H)
• Bit Number
• Bit Name
• Bit Type
• Bit Description
  • Alarm and Error Status Register (AESR) (Address = 0x0B02H)
• Bit Number
• Bit Name
• Bit Type
• Bit Description
  • 12.4 Bipolar Violation
  • Alarm and Error Interrupt Enable Register (AEIER) (Address = 0x0B03H)
• Bit Number
• Bit Name
• Bit Type
• Bit Description
  • Block Interrupt Enable Register (BIER) (Address = 0x0B01H)
• Bit Number
• Bit Name
• Bit Type
• Bit Description
  • Alarm and Error Status Register (AESR) (Address = 0x0B02H)
• Bit Number
• Bit Name
• Bit Type
• Bit Description
  • Alarm and Error Interrupt Enable Register (AEIER) (Address = 0x0B03H)
• Bit Number
• Bit Name
• Bit Type
• Bit Description
  • Block Interrupt Enable Register (BIER) (Address = 0x0B01H)
• Bit Number
• Bit Name
• Bit Type
• Bit Description
  • Alarm and Error Status Register (AESR) (Address = 0x0B02H)
• Bit Number
• Bit Name
• Bit Type
• Bit Description
  • 12.5 E1 Brief discussion of alarms and error conditions
    • Figure 97. Simple Diagram of E1 system model
    • Figure 98. Generation of Yellow Alarm by the Repeater upon detection of line failure
    • Figure 99. Generation of AIS by the Repeater upon detection of line failure
    • Figure 100. Generation of Yellow Alarm by the CPE upon detection of AIS originated by the Repeater
    • Figure 101. Generation of CAS Multi-frame Yellow Alarm and AIS16 by the Repeater
    • Figure 102. Generation of CAS Multi-frame Yellow Alarm by the CPE upon detection of �AIS16� patte...
    • 12.5.1 How to configure the framer to transmit AIS
  • Alarm Generation Register (AGR) (Address = 0x0108H)
• Bit Number
• Bit Name
• Bit Type
• Bit Description
  • 12.5.2 How to configure the framer to generate Red Alarm
  • Alarm Generation Register (AGR) (Address = 0x0108H)
• Bit Number
• Bit Name
• Bit Type
• Bit Description
  • 12.5.3 How to configure the framer to transmit Yellow Alarm
  • 12.5.4 Transmit Yellow Alarm
  • 12.5.5 Transmit CAS Multi-frame Yellow Alarm
  • 12.6 T1 Brief discussion of alarms and error conditions
    • Figure 103. Simple Diagram of DS1 System Model
    • Figure 104. Generation of Yellow Alarm by the CPE upon detection of line failure
    • Figure 105. Generation of AIS by the Repeater upon detection of Yellow Alarm originated by the CPE
    • Figure 106. Generation of Yellow Alarm by the CPE upon detection of AIS originated by the Repeater
    • 12.6.1 How to configure the framer to transmit AIS
  • Alarm Generation Register (AGR) (Address = 0x0108H)
• Bit Number
• Bit Name
• Bit Type
• Bit Description
  • 12.6.2 How to configure the framer to generate Red Alarm
  • Alarm Generation Register (AGR) (Address = 0x0108H)
• Bit Number
• Bit Name
• Bit Type
• Bit Description
  • 12.6.3 How to configure the framer to transmit Yellow Alarm
  • 12.6.4 Transmit Yellow Alarm in SF Mode
  • 12.6.5 Transmit Yellow Alarm in ESF Mode
  • 12.6.6 Transmit Yellow Alarm in N Mode
  • 12.6.7 Transmit Yellow Alarm in T1DM Mode
  • Alarm Generation Register (AGR) (Address = 0x0108H)
• Bit Number
• Bit Name
• Bit Type
• Bit Description
  • 13.0 Performance monitoring (pmon)
    • 13.1 Receive Line Code Violation Counter (16-Bit)
    • 13.2 16-Bit Receive Frame Alignment Error Counter (16-Bit)
    • 13.3 Receive Severely Errored Frame Counter (8-Bit)
    • 13.4 Receive CRC-6/4 Block Error Counter (16-Bit)
    • 13.5 Receive Far-End Block Error Counter (16-Bit)
    • 13.6 Receive Slip Counter (8-Bit)
    • 13.7 Receive Loss of Frame Counter (8-Bit)
    • 13.8 Receive Change of Frame Alignment Counter (8-Bit)
    • 13.9 Frame Check Sequence Error Counters 1, 2, and 3 (8-Bit Each)
    • 13.10 PRBS Error Counter (16-Bit)
    • 13.11 Transmit Slip Counter (8-Bit)
    • 13.12 Excessive Zero Violation Counter (16-Bit)
  • 14.0 Appendix A: DS-1/E1 Framing formats
    • 14.1 The E1 Framing Structure
      • Figure 107. Single E1 Frame Diagram
      • 14.1.1 FAS Frame
        • Table 175: Bit Format of Timeslot 0 octet within a FAS E1 Frame
• Bit
• 0
• 1
• 2
• 3
• 4
• 5
• 6
• 7
  • 14.1.2 Non-FAS Frame
    • Table 176: Bit Format of Timeslot 0 octet within a Non-FAS E1 Frame
• Bit
• 0
• 1
• 2
• 3
• 4
• 5
• 6
• 7
  • 14.2 The E1 Multi-frame Structure
    • 14.2.1 The CRC Multi-frame Structure
      • Table 177: Bit Format of all Timeslot 0 octets within a CRC Multi-frame
    • 14.2.2 CAS Multi-Frames and Channel Associated Signaling
      • 14.2.2.1 Channel Associated Signaling
      • Figure 108. Frame/Byte Format of the CAS Multi-Frame Structure
      • 14.2.2.2 Common Channel Signaling (CCS)
      • Figure 109. E1 Frame Format
  • 14.3 The DS1 Framing Structure
    • Figure 110. T1 Frame Format
  • 14.4 T1 Super Frame Format (SF)
    • Figure 111. T1 Superframe PCM Format
    • Table 178: Superframe Format
• Frame
• Bit
• F-Bits
• Bit Use in Each Timeslot
• Signalling
• Channel
• Terminal
• Framing Ft
• Terminal
• Framing Fs
• Traffic
• Sig
  • 14.5 T1 Extended Superframe Format (ESF)
    • Figure 112. T1 Extended Superframe Format
    • Table 179: Extended Superframe Format
• Frame
• Bit
• F-Bits
• Bit Use in Each Timeslot
• Signalling Channel
• FPS
• DL
• CRC
• Traffic
• Sig
• 16
• 4
• 2
  • 14.6 T1 Non-Signaling Frame Format
    • Table 180: Non-Signaling Framing Format
• Frame
• Bit
• F-Bits
• Terminal
• Framing Ft
• Terminal
• Framing Fs
  • 14.7 T1 Data Multiplexed Framing Format (T1DM)
    • Figure 113. T1DM Frame Format
  • 14.8 SLC-96 Format (SLC-96)
    • Table 181: SLC�96 Fs Bit Contents
• Frame #
• FS Bit
• Frame #
• FS Bit
• Frame #
• FS Bit
  • Electrical Characteristics (framer block)
  • Absolute Maximums
  • DC Electrical Characteristics
• Symbol
• Parameter
• Min.
• Typ.
• Max.
• Units
• Conditions
  • AC Electrical Characteristics Transmit Framer
• Symbol
• Parameter
• Min.
• Typ.
• Max.
• Units
• Conditions
  • Figure 114. Framer System Transmit Timing Diagram
  • AC Electrical Characteristics Receive Framer
• Symbol
• Parameter
• Min.
• Typ.
• Max.
• Units
• Conditions
  • Figure 115. Framer System Receive Timing Diagram (RxSERCLK as an Output)
  • Figure 116. Framer System Receive Timing Diagram (RxSERCLK as an Input)
  • AC Electrical Characteristics Transmit Overhead Framer
• Symbol
• Parameter
• Min.
• Typ.
• Max.
• Units
• Conditions
  • Figure 117. Framer System Transmit Overhead Timing Diagram
  • AC Electrical Characteristics Receive Overhead Framer
• Symbol
• Parameter
• Min.
• Typ.
• Max.
• Units
• Conditions
  • Figure 118. Framer System Receive Overhead Timing Diagram (RxSERCLK as an Output)
  • Figure 119. Framer System Receive Overhead Timing Diagram (RxSERCLK as an Input)
• ELECTRICAL CHARACTERISTICS
  • Table 182: XRT83L38 Power Consumption
• VDD=3.3V�5%, TA=25C, unless otherwise specified
• Mode
• Supply
• Voltage
• Impedance
• termination
• Resistor
• Transformer Ratio
• Typ.
• Max.
• Unit
• Test
• Conditions
• Receiver
• Transmitter
  • Table 183: E1 Receiver Electrical Characteristics
• VDD=3.3V�5%, TA= -40� to 85C, unless otherwise specified
• Parameter
• Min.
• Typ.
• Max.
• Unit
• Test Conditions
  • Table 184: T1 Receiver Electrical Characteristics
• VDD=3.3V�5%, TA=-40� to 85C, unless otherwise specified
• Parameter
• Min.
• Typ.
• Max.
• Unit
• Test Conditions
  • Table 185: E1 Transmit Return Loss Requirement
• Frequency
• Return Loss
• G.703/CH-PTT
• ETS 300166
  • Table 186: E1 Transmitter Electrical Characteristics
• VDD=3.3V�5%, TA=-40� to 85C, unless otherwise specified
• Parameter
• Min.
• Typ.
• Max.
• Unit
• Test Conditions
  • Table 187: T1 Transmitter Electrical Characteristics
• VDD=3.3V�5%, TA=-40� to 85C, unless otherwise specified
• Parameter
• Min.
• Typ.
• Max.
• Unit
• Test Conditions
  • Figure 120. ITU G.703 Pulse Template
  • Table 188: Transmit Pulse Mask Specification
  • Figure 121. DSX-1 Pulse Template (normalized amplitude)
  • Table 189: DSX1 Interface Isolated pulse mask and corner points
• Minimum curve
• Maximum curve
• Time (UI)
• Normalized amplitude
• Time (UI)
• Normalized amplitude
  • Table 190: AC Electrical Characteristics
• VDD=3.3V�5%, Ta=25C, unless otherwise specified
• Parameter
• Symbol
• Min.
• Typ.
• Max.
• Units
• Ordering information
• Package dimensions
  • Revision History
• Revision #
• Date
• Description