2000 Fairchild Semiconductor Corporation
DS010250
www.fairchildsemi.com
October 1989
Revised August 2000
1
00343 Low
Power 8-Bi
t Lat
c
h
100343
Low Power 8-Bit Latch
General Description
The 100343 contains eight D-type latches, individual
inputs, (D
n
), outputs (Q
n
), a common enable pin (E), and a
latch enable pin (LE). A Q output follows its D input when
both E and LE are LOW. When either E or LE (or both) are
HIGH, a latch stores the last valid data present on its D
input prior to E or LE going HIGH.
The 100343 outputs are designed to drive a 50
termina-
tion resistor to
-
2.0V. All inputs have 50 k
pull-down
resistors.
Features
s
Low power operation
s
2000V ESD protection
s
Voltage compensated operating range
=
-
4.2V to
-
5.7V
s
Available to industrial grade temperature range
Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter "X" to the ordering code.
Logic Symbol
Pin Descriptions
Connection Diagrams
24-Pin DIP
28-Pin PLCC
Order Number
Package Number
Package Description
100343PC
N24E
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.400 Wide
100343QC
V28A
28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square
100343QI
V28A
28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square
Industrial Temperature Range (
-
40
C to
+
85
C)
Pin Names
Description
D
0
D
7
Data Inputs
E
Enable Input
LE
Latch Enable Input
Q
0
Q
7
Data Inputs
NC
No Connect
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2
100343
Truth Table
H
=
HIGH Voltage Level
L
=
LOW Voltage Level
X
=
Don't Care
Note 1: Retains data present before either LE or E went HIGH
Logic Diagram
Inputs
Outputs
D
n
E
LE
Q
n
L
L
L
L
H
L
L
H
X
H
X
Latched (Note 1)
X
X
H
Latched (Note 1)
3
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1
00343
Absolute Maximum Ratings
(Note 2)
Recommended Operating
Conditions
Note 2: The "Absolute Maximum Ratings" re those values beyond which
the safety of the device cannot be guaranteed. The device should not be
operated at these limits. The parametric values defined in the absolute
maximum rating. The "Recommended Operating Conditions" table will
define the conditions for actual device operation.
Note 3: ESD testing conforms to MIL-STD-883, Method 3015.
Commercial Version
DC Electrical Characteristics
(Note 4)
V
EE
=
-
4.2V to
-
5.7V, V
CC
=
V
CCA
=
GND, T
C
=
0
C to
+
85
C
Note 4: The specified limits represent the "worst case" value for the parameter. Since these values normally occur at the temperature extremes, additional
noise immunity and guardbanding can be achieved by decreasing the allowable system operating ranges. Conditions for testing shown in the tables are cho-
sen to guarantee operation under "worst case" conditions.
AC Electrical Characteristics
V
EE
=
-
4.2V to
-
5.7V, V
CC
=
V
CCA
=
GND
Note 5: The propagation delay specified is for single output switching. Delays may vary up to 300 ps with multiple outputs switching.
Storage Temperature (T
STG
)
-
65
C to
+
150
C
Maximum Junction Temperature (T
J
)
+
150
C
V
EE
Pin Potential to Ground Pin
-
7.0V to
+
0.5V
Input Voltage (DC)
V
EE
to
+
0.5V
Output Current (DC Output HIGH)
-
50 mA
ESD (Note 3)
2000V
Case Temperature (T
C
)
Commercial
0
C to
+
85
C
Industrial
-
40
C to
+
85
C
Supply Voltage (V
EE
)
-
5.7V to
-
4.2V
Symbol
Parameter
Min
Typ
Max
Units
Conditions
V
OH
Output HIGH Voltage
-
1025
-
955
-
870
mV
V
IN
=
V
IH
(Max)
Loading with
V
OL
Output LOW Voltage
-
1830
-
1705
-
1620
mV
or V
IL
(Min)
50
to
-
2.0V
V
OHC
Output HIGH Voltage
-
1035
mV
V
IN
=
V
IH
(Min)
Loading with
V
OLC
Output LOW Voltage
-
1610
mV
or V
IL
(Max)
50
to
-
2.0V
V
IH
Input HIGH Voltage
-
1165
-
870
mV
Guaranteed HIGH Signal for All Inputs
V
IL
Input LOW Voltage
-
1830
-
1475
mV
Guaranteed LOW Signal for All Inputs
I
IL
Input LOW Current
0.50
A
V
IN
=
V
IL
(Min)
I
IH
Input HIGH Current
240
A
V
IN
=
V
IH
(Max)
I
EE
Power Supply Current
Inputs Open
-
95
-
55
mA
V
EE
=
-
4.2V to
-
4.8V
-
97
-
55
V
EE
=
-
4.2V to
-
5.7V
Symbol
Parameter
T
C
=
0
C
T
C
=
+
25
C
T
C
=
+
85
C
Units
Conditions
Min
Max
Min
Max
Min
Max
t
PLH
Propagation Delay
0.80
2.00
0.80
2.00
0.80
2.20
ns
Figures 1, 2, 3
t
PHL
D
n
to Output
(Note 5)
t
PLH
Propagation Delay
1.40
2.90
1.40
2.90
1.60
3.10
ns
Figures 1, 2, 3
t
PHL
LE, E to Output
(Note 5)
t
TLH
Transition Time
0.45
2.00
0.45
2.00
0.45
2.00
ns
Figures 1, 3
t
THL
20% to 80%, 80% to 20%
t
S
Setup Time
D
0
D
7
1.0
1.0
1.1
ns
Figures 1, 4
t
H
Hold Time
D
0
D
7
0.1
0.1
0.1
ns
Figures 1, 4
t
PW
(H)
Pulse Width HIGH
LE, E
2.00
2.00
2.00
ns
Figures 1, 4
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4
100343
Commercial Version
(Continued)
PLCC AC Electrical Characteristics
V
EE
=
-
4.2V to
-
5.7V, V
CC
=
V
CCA
=
GND
Note 6: The propagation delay specified is for single output switching. Delays may vary up to 300 ps with multiple outputs switching.
Note 7: Output-to-Output Skew is defined as the absolute value of the difference between the actual propagation delay for any outputs within the same pack-
aged device. The specifications apply to any outputs switching in the same direction either HIGH-to-LOW (t
OSHL
), or LOW-to-HIGH (t
OSLH
), or in opposite
directions both HL and LH (t
OST
). Parameters t
OST
and t
PS
guaranteed by design.
Symbol
Parameter
T
C
=
0
C
T
C
=
+
25
C
T
C
=
+
85
C
Units
Conditions
Min
Max
Min
Max
Min
Max
t
PLH
Propagation Delay
0.80
1.80
0.80
1.80
0.80
2.00
ns
Figures 1, 2, 3
t
PHL
D
n
to Output
(Note 6)
t
PLH
Propagation Delay
1.40
2.70
1.40
2.70
1.60
2.90
ns
Figures 1, 2, 3
t
PHL
LE, E to Output
(Note 6)
t
TLH
Transition Time
0.45
1.90
0.45
1.90
0.45
1.90
ns
Figures 1, 3
t
THL
20% to 80%, 80% to 20%
t
S
Setup Time
D
0
D
7
0.90
0.90
1.00
ns
Figures 1, 4
t
H
Hold Time
D
0
D
7
0.0
0.0
0.0
ns
Figures 1, 4
t
PW
(H)
Pulse Width HIGH
LE, E
2.00
2.00
2.00
ns
Figures 1, 4
t
OSHL
Maximum Skew Common Edge
PLCC Only
Output-to-Output Variation
340
340
340
ps
(Note 7)
Data to Output Path
t
OSLH
Maximum Skew Common Edge
PLCC Only
Output-to-Output Variation
440
440
440
ps
(Note 7)
Data to Output Path
t
OST
Maximum Skew Opposite Edge
PLCC Only
Output-to-Output Variation
480
480
480
ps
(Note 7)
Data to Output Path
t
PS
Maximum Skew
PLCC Only
Pin (Signal) Transition Variation
300
300
300
ps
(Note 7)
Data to Output Path
5
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1
00343
Industrial Version
PLCC DC Electrical Characteristics
(Note 8)
V
EE
=
-
4.2V to
-
5.7V, V
CC
=
V
CCA
=
GND, T
C
=
-
40
C to
+
85
C
Note 8: The specified limits represent the "worst case" value for the parameter. Since these values normally occur at the temperature extremes, additional
noise immunity and guardbanding can be achieved by decreasing the allowable system operating ranges. Conditions for testing shown in the tables are cho-
sen to guarantee operation under "worst case" conditions.
PLCC AC Electrical Characteristics
V
EE
=
-
4.2V to
-
5.7V, V
CC
=
V
CCA
=
GND
Note 9: The propagation delay specified is for single output switching. Delays may vary up to 300 ps with multiple outputs switching.
Symbol
Parameter
T
C
=
-
40
C
T
C
=
0
C to
+
85
C
Units
Conditions
Min
Max
Min
Max
V
OH
Output HIGH Voltage
-
1085
-
870
-
1025
-
870
mV
V
IN
=
V
IH (Max)
Loading with
V
OL
Output LOW Voltage
-
1830
-
1575
-
1830
-
1620
mV
or V
IL (Min)
50
to
-
2.0V
V
OHC
Output HIGH Voltage
-
1095
-
1035
mV
V
IN
=
V
IH (Min)
Loading with
V
OLC
Output LOW Voltage
-
1565
-
1610
mV
or V
IL (Max)
50
to
-
2.0V
V
IH
Input HIGH Voltage
-
1170
-
870
-
1165
-
870
mV
Guaranteed HIGH Signal
for All Inputs
V
IL
Input LOW Voltage
-
1830
-
1480
-
1830
-
1475
mV
Guaranteed LOW Signal
for All Inputs
I
IL
Input LOW Current
0.50
0.50
A
V
IN
=
V
IL
(Min)
I
IH
Input HIGH Current
240
240
A
V
IN
=
V
IH
(Max)
I
EE
Power Supply Current
Inputs Open
-
95
-
50
-
95
-
55
mA
V
EE
=
-
4.2V to
-
4.8V
-
97
-
50
-
97
-
55
V
EE
=
-
4.2V to
-
5.7V
Symbol
Parameter
T
C
=
-
40
C
T
C
=
+
25
C
T
C
=
+
85
C
Units
Conditions
Min
Max
Min
Max
Min
Max
t
PLH
Propagation Delay
0.80
1.80
0.80
1.80
0.80
2.00
ns
Figures 1, 2, 3
t
PHL
D
n
to Output
(Note 9)
t
PLH
Propagation Delay
1.40
2.70
1.40
2.70
1.60
2.90
ns
Figures 1, 2, 3
t
PHL
LE, E to Output
(Note 9)
t
TLH
Transition Time
0.40
2.50
0.45
1.90
0.45
1.90
ns
Figures 1, 3
t
THL
20% to 80%, 80% to 20%
t
s
Setup Time
D
0
D
7
0.60
0.90
1.00
ns
Figures 1, 4
t
H
Hold Time
D
0
D
7
0.8
0.0
0.0
ns
Figures 1, 4
t
pw
(H)
Pulse Width HIGH
LE, E
2.40
2.00
2.00
ns
Figures 1, 4
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