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Электронный компонент: 100355QC

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2000 Fairchild Semiconductor Corporation
DS010147
www.fairchildsemi.com
July 1989
Revised August 2000
1
00355 Low
Power Quad
Mul
t
i
p
lexe
r/
Latch
100355
Low Power Quad Multiplexer/Latch
General Description
The 100355 contains four transparent latches, each of
which can accept and store data from two sources. When
both Enable (E
n
) inputs are LOW, the data that appears at
an output is controlled by the Select (S
n
) inputs, as shown
in the Operating Mode table. In addition to routing data
from either D
0
or D
1
, the Select inputs can force the out-
puts LOW for the case where the latch is transparent (both
Enables are LOW) and can steer a HIGH signal from either
D
0
or D
1
to an output. The Select inputs can be tied
together for applications requiring only that data be steered
from either D
0
or D
1
. A positive-going signal on either
Enable input latches the outputs. A HIGH signal on the
Master Reset (MR) input overrides all the other inputs and
forces the Q outputs LOW. All inputs have 50 k
pull-down
resistors.
Features
s
Greater than 40% power reduction of the 100155
s
2000V ESD protection
s
Pin/function compatible with 100155
s
Voltage compensated operating range
=
-
4.2V to
-
5.7V
s
Available to industrial grade temperature range
Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter "X" to the ordering code.
Logic Symbol
Pin Descriptions
Connection Diagrams
24-Pin DIP
28-Pin PLCC
Order Number
Package Number
Package Description
100355PC
N24E
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.400 Wide
100355QC
V28A
28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square
100355QI
V28A
28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square
Industrial Temperature Range (
-
40
C to
+
85
C)
Pin Names
Description
E
1
, E
2
Enable Inputs (Active LOW)
S
0
, S
1
Select Inputs
MR
Master Reset
D
na
D
nd
Data Inputs
Q
a
Q
d
Data Outputs
Q
a
Q
d
Complementary Data Outputs
www.fairchildsemi.com
2
100355
Operating Mode Table
H
=
HIGH Voltage Level
L
=
LOW Voltage Level
X
=
Don't Care
Note 1: Stores data present before E went HIGH
Truth Table
Logic Diagram
Controls
Outputs
E
1
E
2
S
1
S
0
Q
n
H
X
X
X
Latched (Note 1)
X
H
X
X
Latched (Note 1)
L
L
L
L
D
0x
L
L
H
L
D
0x
+
D
1x
L
L
L
H
L
L
L
H
H
D
1x
Inputs
Outputs
MR
E
1
E
2
S
1
S
0
D
1x
D
0x
Q
x
Q
x
H
X
X
X
X
X
X
H
L
L
L
L
H
H
H
X
L
H
L
L
L
H
H
L
X
H
L
L
L
L
L
L
X
H
L
H
L
L
L
L
L
X
L
H
L
L
L
L
L
H
X
X
H
L
L
L
L
H
L
H
X
L
H
L
L
L
H
L
X
H
L
H
L
L
L
H
L
L
L
H
L
L
H
X
X
X
X
X
Latched (Note 1)
L
X
H
X
X
X
X
Latched (Note 1)
3
www.fairchildsemi.com
1
00355
Absolute Maximum Ratings
(Note 2)
Recommended Operating
Conditions
Note 2: The "Absolute Maximum Ratings" are those values beyond which
the safety of the device cannot be guaranteed. The device should not be
operated at these limits. The parametric values defined in the Electrical
Characteristics tables are not guaranteed at the absolute maximum rating.
The "Recommended Operating Conditions" table will define the conditions
for actual device operation.
Note 3: ESD testing conforms to MIL-STD-883, Method 3015.
Commercial Version
DC Electrical Characteristics
(Note 4)
V
EE
=
-
4.2V to
-
5.7V, V
CC
=
V
CCA
=
GND, T
C
=
0
C to
+
85
C
Note 4: The specified limits represent the "worst case" value for the parameter. Since these values normally occur at the temperature extremes, additional
noise immunity and guard banding can be achieved by decreasing the allowable system operating ranges. Conditions for testing shown in the tables are cho-
sen to guarantee operation under "worst case" conditions.
Storage Temperature (T
STG
)
-
65
C to
+
150
C
Maximum Junction Temperature (T
J
)
+
150
C
V
EE
Pin Potential to Ground Pin
-
7.0V to
+
0.5V
Input Voltage (DC)
V
EE
to
+
0.5V
Output Current (DC Output HIGH)
-
50 mA
ESD (Note 3)
2000V
Case Temperature (T
C
)
Commercial
0
C to
+
85
C
Industrial
-
40
C to
+
85
C
Supply Voltage (V
EE
)
-
5.7V to
-
4.2V
Symbol
Parameter
Min
Typ
Max
Units
Conditions
V
OH
Output HIGH Voltage
-
1025
-
955
-
870
mV
V
IN
=
V
IH (Max)
Loading with
V
OL
Output LOW Voltage
-
1830
-
1705
-
1620
mV
or V
IL (Min)
50
to
-
2.0V
V
OHC
Output HIGH Voltage
-
1035
mV
V
IN
=
V
IH (Min)
Loading with
V
OLC
Output LOW Voltage
-
1610
mV
or V
IL (Max)
50
to
-
2.0V
V
IH
Input HIGH Voltage
-
1165
-
870
mV
Guaranteed HIGH Signal
for ALL Inputs
V
IL
Input LOW Voltage
-
1830
-
1475
mV
Guaranteed LOW Signal
for ALL Inputs
I
IL
Input LOW Current
0.50
A
V
IN
=
V
IL (Min)
I
IH
Input HIGH Current
S
0
, S
1
220
E
1
, E
2
350
A
V
IN
=
V
IH (Max)
D
na
D
nd
340
MR
430
I
EE
Power Supply Current
-
87
-
40
mA
Inputs Open
www.fairchildsemi.com
4
100355
Commercial Version
(Continued)
DIP AC Electrical Characteristics
V
EE
=
-
4.2V to
-
5.7V, V
CC
=
V
CCA
=
GND
Symbol
Parameter
T
C
=
0
C
T
C
=
+
25
C
T
C
=
+
85
C
Units
Conditions
Min
Max
Min
Max
Min
Max
t
PLH
Propagation Delay
t
PHL
D
na
D
nd
to Output
0.60
1.90
0.60
1.90
0.70
2.00
ns
(Transparent Mode)
t
PLH
Propagation Delay
Figures 1, 2
t
PHL
S
0
, S
1
to Output
1.00
2.60
1.00
2.60
1.20
2.70
ns
(Transparent Mode)
t
PLH
Propagation Delay
0.80
2.00
0.80
2.00
0.80
2.10
ns
t
PHL
E
1
, E
2
to Output
t
PLH
Propagation Delay
0.80
2.30
0.80
2.30
0.80
2.30
ns
Figures 1, 3
t
PHL
MR to Output
t
TLH
Transition Time
0.60
1.40
0.60
1.40
0.60
1.40
ns
Figures 1, 2
t
THL
20% to 80%, 80% to 20%
t
S
Setup Time
D
na
D
nd
0.90
0.90
0.90
ns
Figure 4
S
0
, S
1
1.70
1.70
1.70
MR (Release Time)
1.50
1.50
1.50
Figure 3
t
H
Hold Time
D
na
D
nd
0.40
0.40
0.40
ns
Figure 4
S
0
, S
1
0.00
0.00
0.00
t
PW
(L)
Pulse Width LOW E
1
, E
2
2.00
2.00
2.00
ns
Figure 2
t
PW
(H)
Pulse Width HIGH MR
2.00
2.00
2.00
ns
Figure 3
5
www.fairchildsemi.com
1
00355
Commercial Version
(Continued)
PLCC AC Electrical Characteristics
V
EE
=
-
4.2V to
-
5.7V, V
CC
=
V
CCA
=
GND
Note 5: Output-to-Output Skew is defined as the absolute value of the difference between the actual propagation delay for any outputs within the same pack-
aged device. The specifications apply to any outputs switching in the same direction either HIGH-to-LOW (t
OSHL
), or LOW-to-HIGH (t
OSLH
), or in opposite
directions both HL and LH (t
OST
). Parameters t
OST
and t
PS
guaranteed by design.
Symbol
Parameter
T
C
=
0
C
T
C
=
+
25
C
T
C
=
+
85
C
Units
Conditions
Min
Max
Min
Max
Min
Max
t
PLH
Propagation Delay
t
PHL
D
na
D
nd
to Output
0.60
1.70
0.60
1.70
0.70
1.80
ns
(Transparent Mode)
t
PLH
Propagation Delay
Figures 1, 2
t
PHL
S
0
, S
1
to Output
1.00
2.40
1.00
2.40
1.20
2.50
ns
(Transparent Mode)
t
PLH
Propagation Delay
0.80
1.80
0.80
1.80
0.80
1.90
ns
t
PHL
E
1
, E
2
to Output
t
PLH
Propagation Delay
0.80
2.10
0.80
2.10
0.80
2.10
ns
Figures 1, 3
t
PHL
MR to Output
t
TLH
Transition Time
0.60
1.30
0.60
1.30
0.60
1.30
ns
Figures 1, 2
t
THL
20% to 80%, 80% to 20%
t
S
Setup Time
D
na
D
nd
0.80
0.80
0.80
ns
Figure 4
S
0
, S
1
1.60
1.60
1.60
MR (Release Time)
1.40
1.40
1.40
Figure 3
t
H
Hold Time
D
na
D
nd
0.30
0.30
0.30
ns
Figure 4
S
0
, S
1
-
0.10
-
0.10
-
0.10
t
PW
(L)
Pulse Width LOW E
1
, E
2
2.00
2.00
2.00
ns
Figure 2
t
PW
(H)
Pulse Width HIGH MR
2.00
2.00
2.00
ns
Figure 3
t
OSHL
Maximum Skew Common Edge
PLCC only
Output-to-Output Variation
330
330
330
ps
(Note 5)
Data to Output Path
t
OSLH
Maximum Skew Common Edge
PLCC only
Output-to-Output Variation
370
370
370
ps
(Note 5)
Data to Output Path
t
OST
Maximum Skew Opposite Edge
PLCC only
Output-to-Output Variation
370
370
370
ps
(Note 5)
Data to Output Path
t
PS
Maximum Skew
PLCC only
Pin (Signal) Transition Variation
270
270
270
ps
(Note 5)
Data to Output Path