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Электронный компонент: 100390QI

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2000 Fairchild Semiconductor Corporation
DS010897
www.fairchildsemi.com
September 1990
Revised August 2000
1
00390 Low
Power Singl
e S
u
pply Hex
PECL-
to-
TTL T
r
ansl
at
or
100390
Low Power Single Supply Hex PECL-to-TTL Translator
General Description
The 100390 is a hex translator for converting F100K logic
levels to TTL logic levels. Unlike other level translators, the
100390 operates using only one
+
5V supply. Differential
inputs allow each circuit to be used as an inverting, nonin-
verting, or differential receiver. An internal reference gener-
ator provides V
BB
for single-ended operation. The standard
FAST
3-STATE outputs are enabled by a common active
low TTL compatible OE input. Partitioned V
CC
s on chip are
brought out on separate power pins, allowing the noisy TTL
V
CC
power plane to be isolated from the relatively quiet
ECL V
CC
. The 100390 is ideal for applications limited to a
single
+
5V supply, allowing for easy ECL to TTL Interfac-
ing.
Features
s
Operates from a single
+
5V supply
s
3-STATE outputs
s
2000V ESD protection
s
V
BB
supplied for single-ended operation
Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter "X" to the ordering code.
Connection Diagrams
24-Pin DIP/SOIC
28-Pin PLCC
FAST
is a registered trademark of Fairchild Semiconductor.
Order Number
Package Number
Package Description
100390SC
M24B
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
100390PC
N24E
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.400 Wide
100390QC
V28A
28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square
100390QI
V28A
28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square
Industrial Temperature Range (
-
40
C to
+
85
C)
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2
100390
Logic Symbol
Pin Descriptions
Truth Table
H
=
HIGH Voltage Level
L
=
LOW Voltage Level
Z
=
HIGH Impedance
U
=
Undefined
Logic Diagram
Detail
Pin Names
Description
D
0
D
5
Data Inputs (PECL)
D
0
D
5
Inverting Data Inputs (PECL)
Q
0
Q
5
Data Outputs (TTL)
OE
Output Enable (TTL)
V
BB
Reference Voltage (PECL)
Data
Control
TTL
Comments
Inputs
Input
Outputs
(PECL)
(TTL)
D
n
D
n
OE
Q
n
X
X
H
Z
Outputs Disable
L
H
L
L
Differential Operation
H
L
L
H
Differential Operation
L
L
L
U
Invalid Input States
H
H
L
U
Invalid Input States
OPEN
OPEN
L
U
Invalid Input States
L
V
BB
L
L
Single Ended Operation
H
V
BB
L
H
Single Ended Operation
V
BB
L
L
H
Single Ended Operation
V
BB
H
L
L
Single Ended Operation
V
BB
OPEN
L
H
Single Ended Operation
OPEN
V
BB
L
L
Single Ended Operation
3
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1
00390
Absolute Maximum Ratings
(Note 1)
Recommended Operating
Conditions
Note 1: The "Absolute Maximum Ratings" are those values beyond which
the safety of the device cannot be guaranteed. The device should not be
operated at these limits. The parametric values defined in the Electrical
Characteristics tables are not guaranteed at the absolute maximum rating.
The "Recommended Operating Conditions" table will define the conditions
for actual device operation.
Note 2: Either voltage limit or current limit is sufficient to protect inputs.
DC Electrical Characteristics
ECL V
CC
=
+
5.0V
5%, TTL V
CC
=
+
5.0V
5%, GND
=
0V
Storage Temperature
-
65
C to
+
150
C
Maximum Junction Temperature
+
150
C
V
CC
Pin Potential to Ground Pin
-
0.5V to
+
7.0V
TTL Input Voltage (Note 2)
-
0.5V to
+
7.0V
TTL Input Current (Note 2)
-
30 mA to
+
5.0 mA
V
BB
Output Current
-
5.0 mA to
+
1.0 mA
ECL Input Potential
GND to ECL V
CC
+
0.5V
V
CC
Differential
ECL V
CC
to TTL V
CC
-
1.0V to
+
1.0V
Voltage Applied to Output
in High State (with V
CC
=
0V)
3-STATE Output
-
0.5V to
+
5.5V
Current Applied to Output
in Low State (Max)
Twice the Rated I
OL
(mA)
ESD Last Passing Voltage (Min)
2000V
Case Temperature
0
C to
+
85
C
Supply Voltage
+
4.75V to
+
5.25V
Symbol
Parameter
Min
Max
Units
Conditions
V
IH
Input HIGH Voltage
Data
ECL V
CC
-
1.165 ECL V
CC
-
0.870
V
Guaranteed HIGH Signal for ALL
Inputs (with One Input Tied to V
BB
)
OE
2.0
V
Guaranteed HIGH Signal (TTL)
V
IL
Input LOW Voltage
Data
ECL V
CC
-
1.830 ECL V
CC
-
1.475
V
Guaranteed LOW Signal for ALL
Inputs (with One Input Tied to V
BB
)
OE
0.8
V
Guaranteed LOW Signal (TTL)
V
BB
Output Reference Voltage
ECL V
CC
-
1.38
ECL V
CC
-
1.26
V
I
BB
=
0.0 mA or
-
1.0 mA
V
OH
Output HIGH Voltage (TTL)
2.7
V
I
OH
=
-
3 mA
V
OL
Output LOW Voltage (TTL)
0.5
V
I
OL
=
24 mA
I
IH
Input HIGH Current
Data
50
A
V
IN
=
V
IH
(Max), D
0
D
5
=
V
BB
,
D
0
D
5
=
V
IL
(Min)
OE
20
A
V
IN
=
2.7V (TTL)
I
IL
Input LOW Current
OE
-
200
A
V
IN
=
0.5V (TTL)
I
BVI
Input Breakdown Current
OE
10
A
V
IN
=
7.0V (TTL)
I
CBO
Input Leakage Current
-
10
A
V
IN
=
GND, D
0
D
5
=
V
BB
D
0
D
5
=
V
IL
(Min)
I
OZH
3-STATE Current Output HIGH
50
A
V
OUT
=
+
2.7V
I
OZL
3-STATE Current Output LOW
-
50
A
V
OUT
=
+
0.5V
I
CC
ECL Supply Current
13
30
mA
I
CCZ
TTL Supply Current
10
20
mA
3-STATE
I
CCL
TTL Supply Current
8
17
mA
Low State
I
CCH
TTL Supply Current HIGH
0.4
2.0
mA
HIGH State
I
OS
Output Short-Circuit Current
-
150
-
60
mA
V
OUT
=
0.0V, V
CC
=
+
5.25
V
Diff
Differential Input Voltage
150
mV
Required for Full Output Swing
V
CM
Common Mode Voltage
ECL V
CC
-
2.0
ECL V
CC
-
0.5
V
V
CD
Clamp Diode Voltage
-
1.2
V
I
IN
=
-
18 mA
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4
100390
DIP AC Electrical Characteristics
V
CC
=
5.0V
5%; T
C
=
0
C to
+
85
C
SOIC and PLCC Package AC Electrical Characteristics
V
CC
=
5.0V
5%; T
C
=
0
C to
+
85
C
Symbol
Parameter
T
C
=
0
C
T
C
=
+
25
C
T
C
=
+
85
C
Units
Figure
Min
Max
Min
Max
Min
Max
Number
f
MAX
Maximum Clock Frequency
100
100
100
MHz
t
PLH
Propagation Delay
3.5
7.2
3.5
6.8
3.5
6.7
ns
Figure 1
t
PHL
Data to Output
t
PZH
Output Enable Time
2.7
4.8
2.7
4.8
3.0
5.1
ns
Figure 2
t
PZL
2.4
4.0
2.4
4.0
2.6
4.2
t
PHZ
Output Disable Time
2.9
5.8
2.9
5.4
2.7
5.1
ns
Figure 2
t
PLZ
2.3
3.9
2.2
3.9
2.2
3.9
Symbol
Parameter
T
C
=
0
C
T
C
=
+
25
C
T
C
=
+
85
C
Units
Figure
Min
Max
Min
Max
Min
Max
Number
f
MAX
Maximum Clock Frequency
100
100
100
MHz
t
PLH
Propagation Delay
3.5
7.0
3.5
6.6
3.5
6.5
ns
Figure 1
t
PHL
Data to Output
t
PZH
Output Enable Time
2.7
4.6
2.7
4.6
3.0
4.9
ns
Figure 2
t
PZL
2.4
3.8
2.4
3.8
2.6
4.0
t
PHZ
Output Disable Time
2.9
5.6
2.9
5.2
2.7
4.9
ns
Figure 2
t
PLZ
2.3
3.7
2.2
3.7
2.2
3.7
5
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1
00390
Switching Waveforms
FIGURE 1. Data to Output Propagation Delay
FIGURE 2. Enable/Disable Propagation Delay
Test Circuit
Notes:
GND
=
0V, ECL V
CC
=
+
5V, TTL V
CC
=
+
5V
L1 and L2
=
equal length 50
impedance lines
50
terminators are internal to S/H measurement unit
Decoupling 0.1
F from GND to ECL V
CC
and TTL V
CC
All unused outputs are loaded with 500
to GND
C
L
=
Fixture and stray capacitance
=
50 pF
Switch S1 is open for t
PLH
, t
PHL
, t
PHZ
and t
PZH
tests
Switch S1 is closed only for t
PLZ
and t
PZL
tests
FIGURE 3. AC Test Circuit