DS500769

www.fairchildsemi.com

January 2003

Revised January 2003

00EL1

1 5

ECL 1

:
2

Dif
f
er
enti

Fanout

Buf

f
e

100EL11
5V ECL 1:2 Differential Fanout Buffer

General Description

The 100EL11 is a 5V 1:2 differential fanout buffer. One dif-
ferential input signal is fanned out to two identical differen-
tial outputs. By supplying a constant reference level to one
input pin a single ended input condition is created.

With inputs open or both inputs at V

the differential Q

outputs default LOW and Q outputs default HIGH.

The 100 series is temperature compensated.

Features

Typical propagation delay of 265 ps

Typical I

of 26 mA

Typical Skew of 5 ps between outputs

Internal pull-down resistors on inputs

Fairchild MSOP-8 package is a drop-in replacement to
ON TSSOP-8

Meets or exceeds JEDEC specification EIA/JESD78 IC
latch-up test

Moisture Sensitivity Level 1

ESD Performance:

Human Body Model

2000V

Machine Model

200V

Ordering Code:

Devices also available in Tape and Reel. Specify by appending suffix letter "X" to the ordering code.

Connection Diagram

Top View

Pin Descriptions

Logic Diagram

Order Number

Product

Package Description

Package

Code

Number

Top Mark

100EL11M

M08A

KEL11

8-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow

100EL11M8
(Preliminary)

MA08D

KL11

8-Lead Molded Small Outline Package (MSOP), JEDEC MO-187, 3.0mm Wide

Pin Name

Description

, Q

ECL Data Outputs

D, D

ECL Data Inputs

Positive Supply

Negative Supply

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100EL1

Absolute Maximum Ratings

(Note 1)

Recommended Operating
Conditions

Note 1: The "Absolute Maximum Ratings" are those values beyond which
the safety of the device cannot be guaranteed. The device should not be
operated at these limits. The parametric values defined in the Electrical
Characteristics tables are not guaranteed at the absolute maximum rating.
The "Recommended Operating Conditions" table will define the conditions
for actual device operation.

100EL PECL DC Electrical Characteristics

5.0V; V

0.0V (Note 2)

Note 2: Input and output parameters vary 1 to 1 with V

. V

can vary

0.8V/

0.5V.

Note 3: Outputs are terminated through a 50

Resistor to V

2.0V.

Note 4: V

IHCMR

minimum varies 1 to 1 with V

. V

IHCMR

maximum varies 1 to 1 with V

. The V

IHCMR

range is referenced to the most positive side of the dif-

ferential input signal. Normal operation is obtained if the HIGH level falls within the specified range and the peak-to-peak voltage lies between V

PPMIN

and

1V.

Note 5: Absolute value of the input HIGH and LOW current should not exceed the absolute value of the stated MIn or Max specification.

Note: Devices are designed to meet the DC specifications after thermal equilibrium has been established. Circuit is tested with air flow greater than
500LFPM maintained.

PECL Supply Voltage (V

) V

0.0V to

8.0V

NECL Supply Voltage (V

) V

0.0V to

8.0V

PECL DC Input Voltage (V

) V

0.0V to

6.0V

NECL DC Input Voltage (V

) V

0.0V to

6.0V

DC Output Current (I

OUT

)

Continuous

50 mA

Surge

100 mA

Storage Temperature (T

STG

)

C to

150

PECL Power Supply

0V)

4.2V to 5.5V

NECL Power Supply

0V)

4.2V to

5.5V

Free Air Operating Temperature (T

)

C to

Symbol

Parameter

Units

Min

Typ

Max

Min

Typ

Max

Min

Typ

Max

Power Supply Current

Output HIGH Voltage (Note 3)

3915

3995

4120

3975

4045

4120

3975

4050

4120

Output LOW Voltage (Note 3)

3170

3305

3445

3190

3295

3380

3190

3295

3380

Input HIGH Voltage (Single Ended)

3835

4120

3835

4120

3835

4120

Input LOW Voltage (Single Ended)

3190

3525

3190

3525

3190

3525

IHCMR

Input HIGH Voltage Common Mode

2.5

4.6

2.5

4.6

2.5

4.6

Range (Differential) (Note 4)

Input HIGH Current (Note 5)

150

Input LOW Current (Note 5)

0.5

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00EL1

100EL NECL DC Electrical Characteristics

0.0V; V

5.0V (Note 6)

Note 6: Input and output parameters vary 1 to 1 with V

. V

can vary

0.8V/

0.5V.

Note 7: Outputs are terminated through a 50

Resistor to V

2.0V.

Note 8: V

IHCMR

minimum varies 1 to 1 with V

. V

IHCMR

maximum varies 1 to 1 with V

. The V

IHCMR

range is referenced to the most positive side of the dif-

ferential input signal. Normal operation is obtained if the HIGH level falls within the specified range and the peak-to-peak voltage lies between V

PPMIN

and

1V.

Note 9: Absolute value of the input HIGH and LOW current should not exceed the absolute value of the stated Min or Max specification.

Note: Devices are designed to meet the DC specifications after thermal equilibrium has been established. Circuit is tested with air flow greater than
500LFPM maintained.

AC Electrical Characteristics

5V; V

0.0V or V

0.0V; V

5V (Note 10)(Note 11)

Note 10: V

can vary

0.8V /

0.5V.

Note 11: Measured using a 750 mV input swing centered at V

- 1.32V; 50% duty cycle clock source; t

250 ps (20% - 80%) at f

1 MHz. All loading

with 50

to V

2.0V.

Note 12: Within-device skew defined as identical transitions on similar paths through a device.

Note 13: Duty cycle skew is the difference between a t

PLH

and t

PHL

propagation delay through a device under identical conditions.

Switching Waveforms

FIGURE 1. Differential to Differential Propagation Delay

FIGURE 2. Differential Output Edge Rates

Symbol

Parameter

Units

Min

Typ

Max

Min

Typ

Max

Min

Typ

Max

Power Supply Current

Output HIGH Voltage (Note 7)

1085

1005

880

1025

955

880

1025

955

880

Output LOW Voltage (Note 7)

1830

1695

1555

1810

1705

1620

1810

1705

1620

Input HIGH Voltage (Single Ended)

1165

880

1165

880

1165

880

Input LOW Voltage (Single Ended)

1810

1475

1810

1475

1810

-1475

IHCMR

Input HIGH Voltage Common Mode

2.5

0.4

2.5

0.4

2.5

0.4

Range (Differential) (Note 8)

Input HIGH Current (Note 9)

150

Input LOW Current (Note 9)

0.5

Symbol

Parameter

Units

Figure

Min

Typ

Max

Min

Typ

Max

Min

Typ

Max

Number

MAX

Maximum Toggle Frequency

TBD

GHz

PLH

, t

PHL

Propagation Delay to Output

135

260

385

190

265

340

215

290

365

Figure 1

SKEW

Within Device Skew (Note 12)

Duty Cycle Skew (Note 13)

JITTER

Cycle-to-Cycle Jitter

TBD

Input Swing

150

1000

150

100

150

1000

Figure 1

, t

Output Rise Times Q

100

225

350

100

225

350

100

225

350

Figure 2

(20% to 80%)

Physical Dimensions

inches (millimeters) unless otherwise noted (Continued)

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00EL1

1 5

ECL 1

:
2

Dif
f
er
enti

Fanout

Buf

f
e

Physical Dimensions

inches (millimeters) unless otherwise noted (Continued)

8-Lead Molded Small Outline Package (MSOP), JEDEC MO-187, 3.0mm Wide

Package Number MA08D

Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.

LIFE SUPPORT POLICY

FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:

1. Life support devices or systems are devices or systems

which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.

2. A critical component in any component of a life support

device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.

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