Preliminary
2002 Fairchild Semiconductor Corporation
DS500774
www.fairchildsemi.com
September 2002
Revised September 2002
1
00EL
T
23
5V Dual Dif
f
e
r
ent
i
al
PECL to TTL T
r
ansl
ator
(
P
rel
i
mi
nary)
100ELT23
5V Dual Differential PECL to TTL Translator (Preliminary)
General Description
The 100ELT23 is a dual differential PECL to TTL translator
operating from a single
+
5V supply.
The dual gate design of the 100ELT23 makes it ideal for
applications which require the translation of a clock and a
data signal.
The 100 series is temperature compensated.
Features
s
Typical propagation delay of 3.5 ns
s
TTL output drive: I
OH
=
24 mA; I
OL
=
-
3 mA
s
Flow through pinout
s
Q Output will default to a LOW with the inputs left Open
s
Internal pull-down resistors on inputs
s
Fairchild MSOP-8 package is a drop-in replacement to
ON TSSOP-8
s
Typical I
CCH
of 23 mA, I
CCL
of 26 mA
s
Meets or exceeds JEDEC specification EIA/JESD78 IC
latch-up test
s
Moisture Sensitivity Level TBD
s
ESD Performance:
Human Body Model
>
TBD
Machine Model
>
TBD
Ordering Code:
Devices also available in Tape and Reel. Specify by appending suffix letter "X" to the ordering code.
Connection Diagram
Top View
Pin Descriptions
Logic Diagram
Order Number
Product
Package Description
Package
Code
Number
Top Mark
100ELT23M
M08A
KLT23
8-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
100ELT23M8
(Preliminary)
MA08D
KT23
8-Lead Molded Small Outline Package (MSOP), JEDEC MO-187, 3.0mm Wide
Pin Name
Description
D
0
, D
0
, D
1
, D
1
PECL Differential Inputs
Q
0
, Q
1
TTL Outputs
V
CC
Positive Supply
GND
Ground
Preliminary
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2
100
E
L
T23
Absolute Maximum Ratings
(Note 1)
Thermal Resistance
Recommended Operating
Conditions
Note 1: The "Absolute Maximum Ratings" are those values beyond which
the safety of the device cannot be guaranteed. The device should not be
operated at these limits. The parametric values defined in the Electrical
Characteristics tables are not guaranteed at the absolute maximum rating.
The "Recommended Operating Conditions" table will define the conditions
for actual device operation.
PECL DC Electrical Characteristics
V
CC
=
5.0V; GND
=
0.0V (Note 2)
Note 2: V
IH
and V
IL
values vary 1 to 1 with V
CC
. V
CC
can vary
0.25V.
Note 3: V
IHCMR
minimum varies 1 to 1 with GND. V
IHCMR
maximum varies 1 to 1 with V
CC
.
Note: Devices are designed to meet the DC specifications after thermal equilibrium has been established. Circuit is tested with air flow greater than
500LFPM maintained.
TTL DC Electrical Characteristics
V
CC
=
5.0V; GND
=
0.0V (Note 4)
Note 4: V
CC
can vary
0.25V.
Note 5: For I
OS
, the use of high-speed test apparatus and/or sample-and-hold techniques are preferable in order to minimize internal chip heating and more
accurately reflect operational values. Otherwise, prolonged shorting of a HIGH output may raise the chip temperature well above normal and thereby cause
invalid readings in other parameter tests. In any sequence of parameter tests, I
OS
tests should be performed last.
Note: Devices are designed to meet the DC specifications after thermal equilibrium has been established. Circuit is tested with air flow greater than
500LFPM maintained.
PECL Supply Voltage (V
CC
)
0.0V to
+
7V
Input Voltage (V
I
) V
I
V
CC
0.0V to
+
6V
Storage Temperature (T
STG
)
-
65
C to
+
150
C
Junction to Ambient (
JA
) SOIC
0LFPM
TBD
500LFPM
TBD
Junction to Case (
JC
)
SOIC
std bd
TBD
Junction to Ambient (
JA
) MSOP
0LFPM
TBD
500LFPM
TBD
Junction to Case (
JC
)
MSOP
std bd
TBD
Power Supply Operating
V
CC
=
4.75V to 5.25V
ECL Input Voltage
0.0V to V
CC
Free Air Operating Temperature (T
A
)
-
40
C to
+
85
C
Symbol
Parameter
-
40
C
25
C
85
C
Units
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
V
IH
Input HIGH Voltage (Single Ended)
3835
4120
3835
4120
3835
4120
mV
V
IL
Input LOW Voltage (Single Ended)
3190
3525
3190
3525
3190
3525
mV
V
IHCMR
Input HIGH Voltage Common
2.2
5.0
2.2
5.0
2.2
5.0
V
Mode Range (Differential) (Note 3)
I
IH
Input HIGH Current
150
150
150
A
I
IL
Input LOW Current
0.5
0.5
0.5
A
Symbol
Parameter
T
A
=
-
40
C to 85
C
Units
Condition
Min
Typ
Max
V
OH
Output HIGH Voltage
2.4
V
I
OH
=
-
3.0 mA
V
OL
Output LOW Voltage
0.5
V
I
OL
=
24 mA
I
CCH
Power Supply Current (Outputs set to HIGH)
23
33
mA
I
CCL
Power Supply Current (Outputs set to LOW)
26
36
mA
I
OS
Output Short Circuit Current (Note 5)
-
150
-
60
mA
Preliminary
3
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1
00EL
T
23
AC Electrical Characteristics
V
CC
=
5.0V; GND
=
0.0V (Note 6)(Note 7)
Note 6: V
CC
can vary
0.25V.
Note 7: All Loading with 500
to GND, C
L
=
20 pF.
Switching Waveforms
Note: V
M
varies 1:1 with V
EE
FIGURE 1. Differential PECL to TTL Output Propagation Delay
FIGURE 2. TTL Output Edge Rates
Symbol
Parameter
-
40
C
25
C
85
C
Units
Figure
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Number
f
MAX
Maximum Toggle Frequency
TBD
TBD
TBD
MHz
t
JITTER
Cycle-to-Cycle Jitter
TBD
TBD
TBD
ps
t
PLH
, t
PHL
Propagation Delay to Output
2.0
5.5
2.0
5.5
2.0
5.5
ns
Figure 1
V
PP
Input Swing
200
1000
200
1000
200
1000
mV
Figure 1
t
r
, t
f
Output Rise Time (10% to 90%)
1.6
ns
Figure 2
Output Fall Time (10% to 90%)
1.1
Preliminary
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4
100
E
L
T23
Physical Dimensions
inches (millimeters) unless otherwise noted
8-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
Package Number M08A
Physical Dimensions
inches (millimeters) unless otherwise noted (Continued)
Preliminary
5
www.fairchildsemi.com
1
00EL
T
23
5V Dual Dif
f
e
r
ent
i
al
PECL to TTL T
r
ansl
ator
(
P
rel
i
mi
nary)
Physical Dimensions
inches (millimeters) unless otherwise noted (Continued)
8-Lead Molded Small Outline Package (MSOP), JEDEC MO-187, 3.0mm Wide
Package Number MA08D
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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